diff options
Diffstat (limited to 'include/linux/ssb')
| -rw-r--r-- | include/linux/ssb/ssb_driver_chipcommon.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h index 4cb995494662..35717b400cef 100644 --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h | |||
| @@ -51,9 +51,12 @@ | |||
| 51 | #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ | 51 | #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ |
| 52 | #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ | 52 | #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ |
| 53 | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ | 53 | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ |
| 54 | #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ | ||
| 55 | #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ | ||
| 54 | #define SSB_CHIPCO_CORECTL 0x0008 | 56 | #define SSB_CHIPCO_CORECTL 0x0008 |
| 55 | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ | 57 | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ |
| 56 | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | 58 | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ |
| 59 | #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ | ||
| 57 | #define SSB_CHIPCO_BIST 0x000C | 60 | #define SSB_CHIPCO_BIST 0x000C |
| 58 | #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ | 61 | #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ |
| 59 | #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 | 62 | #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 |