diff options
Diffstat (limited to 'include/linux/ssb/ssb.h')
-rw-r--r-- | include/linux/ssb/ssb.h | 97 |
1 files changed, 34 insertions, 63 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h index 2b5c312c4960..e18f5c23b930 100644 --- a/include/linux/ssb/ssb.h +++ b/include/linux/ssb/ssb.h | |||
@@ -15,22 +15,19 @@ struct pcmcia_device; | |||
15 | struct ssb_bus; | 15 | struct ssb_bus; |
16 | struct ssb_driver; | 16 | struct ssb_driver; |
17 | 17 | ||
18 | 18 | struct ssb_sprom { | |
19 | struct ssb_sprom_r1 { | 19 | u8 revision; |
20 | u16 pci_spid; /* Subsystem Product ID for PCI */ | ||
21 | u16 pci_svid; /* Subsystem Vendor ID for PCI */ | ||
22 | u16 pci_pid; /* Product ID for PCI */ | ||
23 | u8 il0mac[6]; /* MAC address for 802.11b/g */ | 20 | u8 il0mac[6]; /* MAC address for 802.11b/g */ |
24 | u8 et0mac[6]; /* MAC address for Ethernet */ | 21 | u8 et0mac[6]; /* MAC address for Ethernet */ |
25 | u8 et1mac[6]; /* MAC address for 802.11a */ | 22 | u8 et1mac[6]; /* MAC address for 802.11a */ |
26 | u8 et0phyaddr:5; /* MII address for enet0 */ | 23 | u8 et0phyaddr; /* MII address for enet0 */ |
27 | u8 et1phyaddr:5; /* MII address for enet1 */ | 24 | u8 et1phyaddr; /* MII address for enet1 */ |
28 | u8 et0mdcport:1; /* MDIO for enet0 */ | 25 | u8 et0mdcport; /* MDIO for enet0 */ |
29 | u8 et1mdcport:1; /* MDIO for enet1 */ | 26 | u8 et1mdcport; /* MDIO for enet1 */ |
30 | u8 board_rev; /* Board revision */ | 27 | u8 board_rev; /* Board revision number from SPROM. */ |
31 | u8 country_code:4; /* Country Code */ | 28 | u8 country_code; /* Country Code */ |
32 | u8 antenna_a:2; /* Antenna 0/1 available for A-PHY */ | 29 | u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */ |
33 | u8 antenna_bg:2; /* Antenna 0/1 available for B-PHY and G-PHY */ | 30 | u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */ |
34 | u16 pa0b0; | 31 | u16 pa0b0; |
35 | u16 pa0b1; | 32 | u16 pa0b1; |
36 | u16 pa0b2; | 33 | u16 pa0b2; |
@@ -41,61 +38,26 @@ struct ssb_sprom_r1 { | |||
41 | u8 gpio1; /* GPIO pin 1 */ | 38 | u8 gpio1; /* GPIO pin 1 */ |
42 | u8 gpio2; /* GPIO pin 2 */ | 39 | u8 gpio2; /* GPIO pin 2 */ |
43 | u8 gpio3; /* GPIO pin 3 */ | 40 | u8 gpio3; /* GPIO pin 3 */ |
44 | u16 maxpwr_a; /* A-PHY Power Amplifier Max Power (in dBm Q5.2) */ | 41 | u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */ |
45 | u16 maxpwr_bg; /* B/G-PHY Power Amplifier Max Power (in dBm Q5.2) */ | 42 | u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */ |
46 | u8 itssi_a; /* Idle TSSI Target for A-PHY */ | 43 | u8 itssi_a; /* Idle TSSI Target for A-PHY */ |
47 | u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ | 44 | u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ |
48 | u16 boardflags_lo; /* Boardflags (low 16 bits) */ | 45 | u16 boardflags_lo; /* Boardflags (low 16 bits) */ |
49 | u8 antenna_gain_a; /* A-PHY Antenna gain (in dBm Q5.2) */ | ||
50 | u8 antenna_gain_bg; /* B/G-PHY Antenna gain (in dBm Q5.2) */ | ||
51 | u8 oem[8]; /* OEM string (rev 1 only) */ | ||
52 | }; | ||
53 | |||
54 | struct ssb_sprom_r2 { | ||
55 | u16 boardflags_hi; /* Boardflags (high 16 bits) */ | 46 | u16 boardflags_hi; /* Boardflags (high 16 bits) */ |
56 | u8 maxpwr_a_lo; /* A-PHY Max Power Low */ | ||
57 | u8 maxpwr_a_hi; /* A-PHY Max Power High */ | ||
58 | u16 pa1lob0; /* A-PHY PA Low Settings */ | ||
59 | u16 pa1lob1; /* A-PHY PA Low Settings */ | ||
60 | u16 pa1lob2; /* A-PHY PA Low Settings */ | ||
61 | u16 pa1hib0; /* A-PHY PA High Settings */ | ||
62 | u16 pa1hib1; /* A-PHY PA High Settings */ | ||
63 | u16 pa1hib2; /* A-PHY PA High Settings */ | ||
64 | u8 ofdm_pwr_off; /* OFDM Power Offset from CCK Level */ | ||
65 | u8 country_str[2]; /* Two char Country Code */ | ||
66 | }; | ||
67 | |||
68 | struct ssb_sprom_r3 { | ||
69 | u32 ofdmapo; /* A-PHY OFDM Mid Power Offset */ | ||
70 | u32 ofdmalpo; /* A-PHY OFDM Low Power Offset */ | ||
71 | u32 ofdmahpo; /* A-PHY OFDM High Power Offset */ | ||
72 | u8 gpioldc_on_cnt; /* GPIO LED Powersave Duty Cycle ON count */ | ||
73 | u8 gpioldc_off_cnt; /* GPIO LED Powersave Duty Cycle OFF count */ | ||
74 | u8 cckpo_1M:4; /* CCK Power Offset for Rate 1M */ | ||
75 | u8 cckpo_2M:4; /* CCK Power Offset for Rate 2M */ | ||
76 | u8 cckpo_55M:4; /* CCK Power Offset for Rate 5.5M */ | ||
77 | u8 cckpo_11M:4; /* CCK Power Offset for Rate 11M */ | ||
78 | u32 ofdmgpo; /* G-PHY OFDM Power Offset */ | ||
79 | }; | ||
80 | |||
81 | struct ssb_sprom_r4 { | ||
82 | /* TODO */ | ||
83 | }; | ||
84 | 47 | ||
85 | struct ssb_sprom { | 48 | /* Antenna gain values for up to 4 antennas |
86 | u8 revision; | 49 | * on each band. Values in dBm/4 (Q5.2). Negative gain means the |
87 | u8 crc; | 50 | * loss in the connectors is bigger than the gain. */ |
88 | /* The valid r# fields are selected by the "revision". | 51 | struct { |
89 | * Revision 3 and lower inherit from lower revisions. | ||
90 | */ | ||
91 | union { | ||
92 | struct { | 52 | struct { |
93 | struct ssb_sprom_r1 r1; | 53 | s8 a0, a1, a2, a3; |
94 | struct ssb_sprom_r2 r2; | 54 | } ghz24; /* 2.4GHz band */ |
95 | struct ssb_sprom_r3 r3; | 55 | struct { |
96 | }; | 56 | s8 a0, a1, a2, a3; |
97 | struct ssb_sprom_r4 r4; | 57 | } ghz5; /* 5GHz band */ |
98 | }; | 58 | } antenna_gain; |
59 | |||
60 | /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */ | ||
99 | }; | 61 | }; |
100 | 62 | ||
101 | /* Information about the PCB the circuitry is soldered on. */ | 63 | /* Information about the PCB the circuitry is soldered on. */ |
@@ -270,7 +232,8 @@ struct ssb_bus { | |||
270 | struct ssb_device *mapped_device; | 232 | struct ssb_device *mapped_device; |
271 | /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ | 233 | /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ |
272 | u8 mapped_pcmcia_seg; | 234 | u8 mapped_pcmcia_seg; |
273 | /* Lock for core and segment switching. */ | 235 | /* Lock for core and segment switching. |
236 | * On PCMCIA-host busses this is used to protect the whole MMIO access. */ | ||
274 | spinlock_t bar_lock; | 237 | spinlock_t bar_lock; |
275 | 238 | ||
276 | /* The bus this backplane is running on. */ | 239 | /* The bus this backplane is running on. */ |
@@ -288,6 +251,7 @@ struct ssb_bus { | |||
288 | /* ID information about the Chip. */ | 251 | /* ID information about the Chip. */ |
289 | u16 chip_id; | 252 | u16 chip_id; |
290 | u16 chip_rev; | 253 | u16 chip_rev; |
254 | u16 sprom_size; /* number of words in sprom */ | ||
291 | u8 chip_package; | 255 | u8 chip_package; |
292 | 256 | ||
293 | /* List of devices (cores) on the backplane. */ | 257 | /* List of devices (cores) on the backplane. */ |
@@ -402,6 +366,13 @@ static inline void ssb_pcihost_unregister(struct pci_driver *driver) | |||
402 | { | 366 | { |
403 | pci_unregister_driver(driver); | 367 | pci_unregister_driver(driver); |
404 | } | 368 | } |
369 | |||
370 | static inline | ||
371 | void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state) | ||
372 | { | ||
373 | if (sdev->bus->bustype == SSB_BUSTYPE_PCI) | ||
374 | pci_set_power_state(sdev->bus->host_pci, state); | ||
375 | } | ||
405 | #endif /* CONFIG_SSB_PCIHOST */ | 376 | #endif /* CONFIG_SSB_PCIHOST */ |
406 | 377 | ||
407 | 378 | ||