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Diffstat (limited to 'include/linux/serial_sci.h')
-rw-r--r--include/linux/serial_sci.h52
1 files changed, 1 insertions, 51 deletions
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 50fe651da965..22b3640c9424 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -10,15 +10,6 @@
10 10
11#define SCIx_NOT_SUPPORTED (-1) 11#define SCIx_NOT_SUPPORTED (-1)
12 12
13enum {
14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
16 SCBRR_ALGO_3, /* (((clk * 2) + 16 * bps) / (16 * bps) - 1) */
17 SCBRR_ALGO_4, /* (((clk * 2) + 16 * bps) / (32 * bps) - 1) */
18 SCBRR_ALGO_5, /* (((clk * 1000 / 32) / bps) - 1) */
19 SCBRR_ALGO_6, /* HSCIF variable sample rate algorithm */
20};
21
22#define SCSCR_TIE (1 << 7) 13#define SCSCR_TIE (1 << 7)
23#define SCSCR_RIE (1 << 6) 14#define SCSCR_RIE (1 << 6)
24#define SCSCR_TE (1 << 5) 15#define SCSCR_TE (1 << 5)
@@ -59,28 +50,6 @@ enum {
59/* HSSRR HSCIF */ 50/* HSSRR HSCIF */
60#define HSCIF_SRE 0x8000 51#define HSCIF_SRE 0x8000
61 52
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73/* Offsets into the sci_port->gpios array */
74enum {
75 SCIx_SCK,
76 SCIx_RXD,
77 SCIx_TXD,
78 SCIx_CTS,
79 SCIx_RTS,
80
81 SCIx_NR_FNS,
82};
83
84enum { 53enum {
85 SCIx_PROBE_REGTYPE, 54 SCIx_PROBE_REGTYPE,
86 55
@@ -99,19 +68,6 @@ enum {
99 SCIx_NR_REGTYPES, 68 SCIx_NR_REGTYPES,
100}; 69};
101 70
102#define SCIx_IRQ_MUXED(irq) \
103{ \
104 [SCIx_ERI_IRQ] = (irq), \
105 [SCIx_RXI_IRQ] = (irq), \
106 [SCIx_TXI_IRQ] = (irq), \
107 [SCIx_BRI_IRQ] = (irq), \
108}
109
110#define SCIx_IRQ_IS_MUXED(port) \
111 ((port)->cfg->irqs[SCIx_ERI_IRQ] == \
112 (port)->cfg->irqs[SCIx_RXI_IRQ]) || \
113 ((port)->cfg->irqs[SCIx_ERI_IRQ] && \
114 !(port)->cfg->irqs[SCIx_RXI_IRQ])
115/* 71/*
116 * SCI register subset common for all port types. 72 * SCI register subset common for all port types.
117 * Not all registers will exist on all parts. 73 * Not all registers will exist on all parts.
@@ -140,22 +96,16 @@ struct plat_sci_port_ops {
140 * Platform device specific platform_data struct 96 * Platform device specific platform_data struct
141 */ 97 */
142struct plat_sci_port { 98struct plat_sci_port {
143 unsigned long mapbase; /* resource base */
144 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
145 unsigned int gpios[SCIx_NR_FNS]; /* SCK, RXD, TXD, CTS, RTS */
146 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */ 99 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
147 upf_t flags; /* UPF_* flags */ 100 upf_t flags; /* UPF_* flags */
148 unsigned long capabilities; /* Port features/capabilities */ 101 unsigned long capabilities; /* Port features/capabilities */
149 102
150 unsigned int scbrr_algo_id; /* SCBRR calculation algo */ 103 unsigned int sampling_rate;
151 unsigned int scscr; /* SCSCR initialization */ 104 unsigned int scscr; /* SCSCR initialization */
152 105
153 /* 106 /*
154 * Platform overrides if necessary, defaults otherwise. 107 * Platform overrides if necessary, defaults otherwise.
155 */ 108 */
156 int overrun_bit;
157 unsigned int error_mask;
158
159 int port_reg; 109 int port_reg;
160 unsigned char regshift; 110 unsigned char regshift;
161 unsigned char regtype; 111 unsigned char regtype;