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-rw-r--r--include/linux/platform_data/clk-realview.h1
-rw-r--r--include/linux/platform_data/clk-ux500.h17
-rw-r--r--include/linux/platform_data/gpio-omap.h217
-rw-r--r--include/linux/platform_data/max310x.h67
-rw-r--r--include/linux/platform_data/omap1_bl.h11
-rw-r--r--include/linux/platform_data/sccnxp.h93
6 files changed, 406 insertions, 0 deletions
diff --git a/include/linux/platform_data/clk-realview.h b/include/linux/platform_data/clk-realview.h
new file mode 100644
index 000000000000..2e426a7dbc51
--- /dev/null
+++ b/include/linux/platform_data/clk-realview.h
@@ -0,0 +1 @@
void realview_clk_init(void __iomem *sysbase, bool is_pb1176);
diff --git a/include/linux/platform_data/clk-ux500.h b/include/linux/platform_data/clk-ux500.h
new file mode 100644
index 000000000000..3af0da1f3be5
--- /dev/null
+++ b/include/linux/platform_data/clk-ux500.h
@@ -0,0 +1,17 @@
1/*
2 * Clock definitions for ux500 platforms
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#ifndef __CLK_UX500_H
11#define __CLK_UX500_H
12
13void u8500_clk_init(void);
14void u9540_clk_init(void);
15void u8540_clk_init(void);
16
17#endif /* __CLK_UX500_H */
diff --git a/include/linux/platform_data/gpio-omap.h b/include/linux/platform_data/gpio-omap.h
new file mode 100644
index 000000000000..e8741c2678d5
--- /dev/null
+++ b/include/linux/platform_data/gpio-omap.h
@@ -0,0 +1,217 @@
1/*
2 * OMAP GPIO handling defines and functions
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 *
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __ASM_ARCH_OMAP_GPIO_H
25#define __ASM_ARCH_OMAP_GPIO_H
26
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <mach/irqs.h>
30
31#define OMAP1_MPUIO_BASE 0xfffb5000
32
33/*
34 * These are the omap15xx/16xx offsets. The omap7xx offset are
35 * OMAP_MPUIO_ / 2 offsets below.
36 */
37#define OMAP_MPUIO_INPUT_LATCH 0x00
38#define OMAP_MPUIO_OUTPUT 0x04
39#define OMAP_MPUIO_IO_CNTL 0x08
40#define OMAP_MPUIO_KBR_LATCH 0x10
41#define OMAP_MPUIO_KBC 0x14
42#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
43#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
44#define OMAP_MPUIO_KBD_INT 0x20
45#define OMAP_MPUIO_GPIO_INT 0x24
46#define OMAP_MPUIO_KBD_MASKIT 0x28
47#define OMAP_MPUIO_GPIO_MASKIT 0x2c
48#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
49#define OMAP_MPUIO_LATCH 0x34
50
51#define OMAP34XX_NR_GPIOS 6
52
53/*
54 * OMAP1510 GPIO registers
55 */
56#define OMAP1510_GPIO_DATA_INPUT 0x00
57#define OMAP1510_GPIO_DATA_OUTPUT 0x04
58#define OMAP1510_GPIO_DIR_CONTROL 0x08
59#define OMAP1510_GPIO_INT_CONTROL 0x0c
60#define OMAP1510_GPIO_INT_MASK 0x10
61#define OMAP1510_GPIO_INT_STATUS 0x14
62#define OMAP1510_GPIO_PIN_CONTROL 0x18
63
64#define OMAP1510_IH_GPIO_BASE 64
65
66/*
67 * OMAP1610 specific GPIO registers
68 */
69#define OMAP1610_GPIO_REVISION 0x0000
70#define OMAP1610_GPIO_SYSCONFIG 0x0010
71#define OMAP1610_GPIO_SYSSTATUS 0x0014
72#define OMAP1610_GPIO_IRQSTATUS1 0x0018
73#define OMAP1610_GPIO_IRQENABLE1 0x001c
74#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
75#define OMAP1610_GPIO_DATAIN 0x002c
76#define OMAP1610_GPIO_DATAOUT 0x0030
77#define OMAP1610_GPIO_DIRECTION 0x0034
78#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
79#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
80#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
81#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
82#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
83#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
84#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
85#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
86
87/*
88 * OMAP7XX specific GPIO registers
89 */
90#define OMAP7XX_GPIO_DATA_INPUT 0x00
91#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
92#define OMAP7XX_GPIO_DIR_CONTROL 0x08
93#define OMAP7XX_GPIO_INT_CONTROL 0x0c
94#define OMAP7XX_GPIO_INT_MASK 0x10
95#define OMAP7XX_GPIO_INT_STATUS 0x14
96
97/*
98 * omap2+ specific GPIO registers
99 */
100#define OMAP24XX_GPIO_REVISION 0x0000
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_WAKE_EN 0x0020
106#define OMAP24XX_GPIO_CTRL 0x0030
107#define OMAP24XX_GPIO_OE 0x0034
108#define OMAP24XX_GPIO_DATAIN 0x0038
109#define OMAP24XX_GPIO_DATAOUT 0x003c
110#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112#define OMAP24XX_GPIO_RISINGDETECT 0x0048
113#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
115#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
116#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
117#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
118#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
119#define OMAP24XX_GPIO_SETWKUENA 0x0084
120#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
121#define OMAP24XX_GPIO_SETDATAOUT 0x0094
122
123#define OMAP4_GPIO_REVISION 0x0000
124#define OMAP4_GPIO_EOI 0x0020
125#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
126#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
127#define OMAP4_GPIO_IRQSTATUS0 0x002c
128#define OMAP4_GPIO_IRQSTATUS1 0x0030
129#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
130#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
131#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
132#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
133#define OMAP4_GPIO_IRQWAKEN0 0x0044
134#define OMAP4_GPIO_IRQWAKEN1 0x0048
135#define OMAP4_GPIO_IRQENABLE1 0x011c
136#define OMAP4_GPIO_WAKE_EN 0x0120
137#define OMAP4_GPIO_IRQSTATUS2 0x0128
138#define OMAP4_GPIO_IRQENABLE2 0x012c
139#define OMAP4_GPIO_CTRL 0x0130
140#define OMAP4_GPIO_OE 0x0134
141#define OMAP4_GPIO_DATAIN 0x0138
142#define OMAP4_GPIO_DATAOUT 0x013c
143#define OMAP4_GPIO_LEVELDETECT0 0x0140
144#define OMAP4_GPIO_LEVELDETECT1 0x0144
145#define OMAP4_GPIO_RISINGDETECT 0x0148
146#define OMAP4_GPIO_FALLINGDETECT 0x014c
147#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
148#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
149#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
150#define OMAP4_GPIO_SETIRQENABLE1 0x0164
151#define OMAP4_GPIO_CLEARWKUENA 0x0180
152#define OMAP4_GPIO_SETWKUENA 0x0184
153#define OMAP4_GPIO_CLEARDATAOUT 0x0190
154#define OMAP4_GPIO_SETDATAOUT 0x0194
155
156#define OMAP_MAX_GPIO_LINES 192
157
158#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
159#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
160
161struct omap_gpio_dev_attr {
162 int bank_width; /* GPIO bank width */
163 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
164};
165
166struct omap_gpio_reg_offs {
167 u16 revision;
168 u16 direction;
169 u16 datain;
170 u16 dataout;
171 u16 set_dataout;
172 u16 clr_dataout;
173 u16 irqstatus;
174 u16 irqstatus2;
175 u16 irqstatus_raw0;
176 u16 irqstatus_raw1;
177 u16 irqenable;
178 u16 irqenable2;
179 u16 set_irqenable;
180 u16 clr_irqenable;
181 u16 debounce;
182 u16 debounce_en;
183 u16 ctrl;
184 u16 wkup_en;
185 u16 leveldetect0;
186 u16 leveldetect1;
187 u16 risingdetect;
188 u16 fallingdetect;
189 u16 irqctrl;
190 u16 edgectrl1;
191 u16 edgectrl2;
192 u16 pinctrl;
193
194 bool irqenable_inv;
195};
196
197struct omap_gpio_platform_data {
198 int bank_type;
199 int bank_width; /* GPIO bank width */
200 int bank_stride; /* Only needed for omap1 MPUIO */
201 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
202 bool loses_context; /* whether the bank would ever lose context */
203 bool is_mpuio; /* whether the bank is of type MPUIO */
204 u32 non_wakeup_gpios;
205
206 struct omap_gpio_reg_offs *regs;
207
208 /* Return context loss count due to PM states changing */
209 int (*get_context_loss_count)(struct device *dev);
210};
211
212extern void omap2_gpio_prepare_for_idle(int off_mode);
213extern void omap2_gpio_resume_after_idle(void);
214extern void omap_set_gpio_debounce(int gpio, int enable);
215extern void omap_set_gpio_debounce_time(int gpio, int enable);
216
217#endif
diff --git a/include/linux/platform_data/max310x.h b/include/linux/platform_data/max310x.h
new file mode 100644
index 000000000000..91648bf5fc5c
--- /dev/null
+++ b/include/linux/platform_data/max310x.h
@@ -0,0 +1,67 @@
1/*
2 * Maxim (Dallas) MAX3107/8 serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _MAX310X_H_
17#define _MAX310X_H_
18
19/*
20 * Example board initialization data:
21 *
22 * static struct max310x_pdata max3107_pdata = {
23 * .driver_flags = MAX310X_EXT_CLK,
24 * .uart_flags[0] = MAX310X_ECHO_SUPRESS | MAX310X_AUTO_DIR_CTRL,
25 * .frequency = 3686400,
26 * .gpio_base = -1,
27 * };
28 *
29 * static struct spi_board_info spi_device_max3107[] = {
30 * {
31 * .modalias = "max3107",
32 * .irq = IRQ_EINT3,
33 * .bus_num = 1,
34 * .chip_select = 1,
35 * .platform_data = &max3107_pdata,
36 * },
37 * };
38 */
39
40#define MAX310X_MAX_UARTS 1
41
42/* MAX310X platform data structure */
43struct max310x_pdata {
44 /* Flags global to driver */
45 const u8 driver_flags:2;
46#define MAX310X_EXT_CLK (0x00000001) /* External clock enable */
47#define MAX310X_AUTOSLEEP (0x00000002) /* Enable AutoSleep mode */
48 /* Flags global to UART port */
49 const u8 uart_flags[MAX310X_MAX_UARTS];
50#define MAX310X_LOOPBACK (0x00000001) /* Loopback mode enable */
51#define MAX310X_ECHO_SUPRESS (0x00000002) /* Enable echo supress */
52#define MAX310X_AUTO_DIR_CTRL (0x00000004) /* Enable Auto direction
53 * control (RS-485)
54 */
55 /* Frequency (extrenal clock or crystal) */
56 const int frequency;
57 /* GPIO base number (can be negative) */
58 const int gpio_base;
59 /* Called during startup */
60 void (*init)(void);
61 /* Called before finish */
62 void (*exit)(void);
63 /* Suspend callback */
64 void (*suspend)(int do_suspend);
65};
66
67#endif
diff --git a/include/linux/platform_data/omap1_bl.h b/include/linux/platform_data/omap1_bl.h
new file mode 100644
index 000000000000..881a8e92d605
--- /dev/null
+++ b/include/linux/platform_data/omap1_bl.h
@@ -0,0 +1,11 @@
1#ifndef __OMAP1_BL_H__
2#define __OMAP1_BL_H__
3
4#include <linux/device.h>
5
6struct omap_backlight_config {
7 int default_intensity;
8 int (*set_power)(struct device *dev, int state);
9};
10
11#endif
diff --git a/include/linux/platform_data/sccnxp.h b/include/linux/platform_data/sccnxp.h
new file mode 100644
index 000000000000..7311ccd3217f
--- /dev/null
+++ b/include/linux/platform_data/sccnxp.h
@@ -0,0 +1,93 @@
1/*
2 * NXP (Philips) SCC+++(SCN+++) serial driver
3 *
4 * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef __SCCNXP_H
15#define __SCCNXP_H
16
17#define SCCNXP_MAX_UARTS 2
18
19/* Output lines */
20#define LINE_OP0 1
21#define LINE_OP1 2
22#define LINE_OP2 3
23#define LINE_OP3 4
24#define LINE_OP4 5
25#define LINE_OP5 6
26#define LINE_OP6 7
27#define LINE_OP7 8
28
29/* Input lines */
30#define LINE_IP0 9
31#define LINE_IP1 10
32#define LINE_IP2 11
33#define LINE_IP3 12
34#define LINE_IP4 13
35#define LINE_IP5 14
36#define LINE_IP6 15
37
38/* Signals */
39#define DTR_OP 0 /* DTR */
40#define RTS_OP 4 /* RTS */
41#define DSR_IP 8 /* DSR */
42#define CTS_IP 12 /* CTS */
43#define DCD_IP 16 /* DCD */
44#define RNG_IP 20 /* RNG */
45
46#define DIR_OP 24 /* Special signal for control RS-485.
47 * Goes high when transmit,
48 * then goes low.
49 */
50
51/* Routing control signal 'sig' to line 'line' */
52#define MCTRL_SIG(sig, line) ((line) << (sig))
53
54/*
55 * Example board initialization data:
56 *
57 * static struct resource sc2892_resources[] = {
58 * DEFINE_RES_MEM(UART_PHYS_START, 0x10),
59 * DEFINE_RES_IRQ(IRQ_EXT2),
60 * };
61 *
62 * static struct sccnxp_pdata sc2892_info = {
63 * .frequency = 3686400,
64 * .mctrl_cfg[0] = MCTRL_SIG(DIR_OP, LINE_OP0),
65 * .mctrl_cfg[1] = MCTRL_SIG(DIR_OP, LINE_OP1),
66 * };
67 *
68 * static struct platform_device sc2892 = {
69 * .name = "sc2892",
70 * .id = -1,
71 * .resource = sc2892_resources,
72 * .num_resources = ARRAY_SIZE(sc2892_resources),
73 * .dev = {
74 * .platform_data = &sc2892_info,
75 * },
76 * };
77 */
78
79/* SCCNXP platform data structure */
80struct sccnxp_pdata {
81 /* Frequency (extrenal clock or crystal) */
82 int frequency;
83 /* Shift for A0 line */
84 const u8 reg_shift;
85 /* Modem control lines configuration */
86 const u32 mctrl_cfg[SCCNXP_MAX_UARTS];
87 /* Called during startup */
88 void (*init)(void);
89 /* Called before finish */
90 void (*exit)(void);
91};
92
93#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-05 11:54:06 -0400