diff options
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 495d368390e0..c1914a8b94a9 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
| @@ -147,7 +147,7 @@ | |||
| 147 | #define PCI_BRIDGE_CONTROL 0x3e | 147 | #define PCI_BRIDGE_CONTROL 0x3e |
| 148 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ | 148 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
| 149 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ | 149 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
| 150 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ | 150 | #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ |
| 151 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ | 151 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
| 152 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ | 152 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
| 153 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ | 153 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |
| @@ -202,8 +202,12 @@ | |||
| 202 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ | 202 | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
| 203 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ | 203 | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| 204 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ | 204 | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| 205 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ | 205 | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ |
| 206 | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ | ||
| 207 | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ | ||
| 206 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ | 208 | #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| 209 | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ | ||
| 210 | #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ | ||
| 207 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ | 211 | #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| 208 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ | 212 | #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| 209 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ | 213 | #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| @@ -316,7 +320,20 @@ | |||
| 316 | #define PCI_X_CMD 2 /* Modes & Features */ | 320 | #define PCI_X_CMD 2 /* Modes & Features */ |
| 317 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ | 321 | #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ |
| 318 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ | 322 | #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ |
| 323 | #define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ | ||
| 324 | #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ | ||
| 325 | #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ | ||
| 326 | #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ | ||
| 319 | #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ | 327 | #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ |
| 328 | /* Max # of outstanding split transactions */ | ||
| 329 | #define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ | ||
| 330 | #define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ | ||
| 331 | #define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ | ||
| 332 | #define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ | ||
| 333 | #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ | ||
| 334 | #define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ | ||
| 335 | #define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ | ||
| 336 | #define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ | ||
| 320 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ | 337 | #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ |
| 321 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ | 338 | #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ |
| 322 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ | 339 | #define PCI_X_STATUS 4 /* PCI-X capabilities */ |