1 files changed, 12 insertions, 4 deletions

diff --git a/include/linux/pci.h b/include/linux/pci.h
index c739df91bac9..0769aa409085 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -132,9 +132,10 @@ static inline const char *pci_power_name(pci_power_t state)
         return pci_power_names[1 + (int) state];
 }
 
-#define PCI_PM_D2_DELAY 200
-#define PCI_PM_D3_WAIT  10
-#define PCI_PM_BUS_WAIT 50
+#define PCI_PM_D2_DELAY         200
+#define PCI_PM_D3_WAIT          10
+#define PCI_PM_D3COLD_WAIT      100
+#define PCI_PM_BUS_WAIT         50
 
 /** The pci_channel state describes connectivity between the CPU and
  *  the pci device.  If some PCI bus between here and the pci device
@@ -278,11 +279,18 @@ struct pci_dev {
         unsigned int    pme_poll:1;     /* Poll device's PME status bit */
         unsigned int    d1_support:1;   /* Low power state D1 is supported */
         unsigned int    d2_support:1;   /* Low power state D2 is supported */
-        unsigned int    no_d1d2:1;      /* Only allow D0 and D3 */
+        unsigned int    no_d1d2:1;      /* D1 and D2 are forbidden */
+        unsigned int    no_d3cold:1;    /* D3cold is forbidden */
+        unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
                                                    decoding during bar sizing */
         unsigned int    wakeup_prepared:1;
+        unsigned int    runtime_d3cold:1;       /* whether go through runtime
+                                                   D3cold, not set for devices
+                                                   powered on/off by the
+                                                   corresponding bridge */
         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
+        unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */
 
 #ifdef CONFIG_PCIEASPM
         struct pcie_link_state  *link_state;    /* ASPM link state. */