3 files changed, 2 insertions, 98 deletions
diff --git a/include/linux/mtd/iflash.h b/include/linux/mtd/iflash.h
deleted file mode 100644
index 9aa5b4f02666..000000000000
--- a/include/linux/mtd/iflash.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $Id: iflash.h,v 1.2 2000/11/13 18:01:54 dwmw2 Exp $ */
-#ifndef __MTD_IFLASH_H__
-#define __MTD_IFLASH_H__
-/* Extended CIS registers for Series 2 and 2+ cards */
-/* The registers are all offsets from 0x4000 */
-#define CISREG_CSR              0x0100
-#define CISREG_WP               0x0104
-#define CISREG_RDYBSY           0x0140
-/* Extended CIS registers for Series 2 cards */
-#define CISREG_SLEEP            0x0118
-#define CISREG_RDY_MASK         0x0120
-#define CISREG_RDY_STATUS       0x0130
-/* Extended CIS registers for Series 2+ cards */
-#define CISREG_VCR              0x010c
-/* Card Status Register */
-#define CSR_SRESET              0x20    /* Soft reset */
-#define CSR_CMWP                0x10    /* Common memory write protect */
-#define CSR_PWRDOWN             0x08    /* Power down status */
-#define CSR_CISWP               0x04    /* Common memory CIS WP */
-#define CSR_WP                  0x02    /* Mechanical write protect */
-#define CSR_READY               0x01    /* Ready/busy status */
-/* Write Protection Register */
-#define WP_BLKEN                0x04    /* Enable block locking */
-#define WP_CMWP                 0x02    /* Common memory write protect */
-#define WP_CISWP                0x01    /* Common memory CIS WP */
-/* Voltage Control Register */
-#define VCR_VCC_LEVEL           0x80    /* 0 = 5V, 1 = 3.3V */
-#define VCR_VPP_VALID           0x02    /* Vpp Valid */
-#define VCR_VPP_GEN             0x01    /* Integrated Vpp generator */
-/* Ready/Busy Mode Register */
-#define RDYBSY_RACK             0x02    /* Ready acknowledge */
-#define RDYBSY_MODE             0x01    /* 1 = high performance */
-#define LOW(x) ((x) & 0xff)
-/* 28F008SA-Compatible Command Set */
-#define IF_READ_ARRAY           0xffff
-#define IF_INTEL_ID             0x9090
-#define IF_READ_CSR             0x7070
-#define IF_CLEAR_CSR            0x5050
-#define IF_WRITE                0x4040
-#define IF_BLOCK_ERASE          0x2020
-#define IF_ERASE_SUSPEND        0xb0b0
-#define IF_CONFIRM              0xd0d0
-/* 28F016SA Performance Enhancement Commands */
-#define IF_READ_PAGE            0x7575
-#define IF_PAGE_SWAP            0x7272
-#define IF_SINGLE_LOAD          0x7474
-#define IF_SEQ_LOAD             0xe0e0
-#define IF_PAGE_WRITE           0x0c0c
-#define IF_RDY_MODE             0x9696
-#define IF_RDY_LEVEL            0x0101
-#define IF_RDY_PULSE_WRITE      0x0202
-#define IF_RDY_PULSE_ERASE      0x0303
-#define IF_RDY_DISABLE          0x0404
-#define IF_LOCK_BLOCK           0x7777
-#define IF_UPLOAD_STATUS        0x9797
-#define IF_READ_ESR             0x7171
-#define IF_ERASE_UNLOCKED       0xa7a7
-#define IF_SLEEP                0xf0f0
-#define IF_ABORT                0x8080
-#define IF_UPLOAD_DEVINFO       0x9999
-/* Definitions for Compatible Status Register */
-#define CSR_WR_READY            0x8080  /* Write state machine status */
-#define CSR_ERA_SUSPEND         0x4040  /* Erase suspend status */
-#define CSR_ERA_ERR             0x2020  /* Erase status */
-#define CSR_WR_ERR              0x1010  /* Data write status */
-#define CSR_VPP_LOW             0x0808  /* Vpp status */
-/* Definitions for Global Status Register */
-#define GSR_WR_READY            0x8080  /* Write state machine status */
-#define GSR_OP_SUSPEND          0x4040  /* Operation suspend status */
-#define GSR_OP_ERR              0x2020  /* Device operation status */
-#define GSR_SLEEP               0x1010  /* Device sleep status */
-#define GSR_QUEUE_FULL          0x0808  /* Queue status */
-#define GSR_PAGE_AVAIL          0x0404  /* Page buffer available status */
-#define GSR_PAGE_READY          0x0202  /* Page buffer status */
-#define GSR_PAGE_SELECT         0x0101  /* Page buffer select status */
-/* Definitions for Block Status Register */
-#define BSR_READY               0x8080  /* Block status */
-#define BSR_UNLOCK              0x4040  /* Block lock status */
-#define BSR_FAILED              0x2020  /* Block operation status */
-#define BSR_ABORTED             0x1010  /* Operation abort status */
-#define BSR_QUEUE_FULL          0x0808  /* Queue status */
-#define BSR_VPP_LOW             0x0404  /* Vpp status */
-#endif /* __MTD_IFLASH_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 3d956c3abb31..45d482ce8397 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -53,6 +53,7 @@ struct mtd_erase_region_info {
        u_int32_t offset;                       /* At which this region starts, from the beginning of the MTD */
        u_int32_t erasesize;            /* For this region */
        u_int32_t numblocks;            /* Number of blocks of erasesize in this region */
+        unsigned long *lockmap;         /* If keeping bitmap of locks */
 };
 /*
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 97523887fe5d..cf197ad62da6 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -431,6 +431,7 @@ struct nand_chip {
 #define NAND_MFR_RENESAS        0x07
 #define NAND_MFR_STMICRO        0x20
 #define NAND_MFR_HYNIX          0xad
+#define NAND_MFR_MICRON         0x2c
 /**
 * struct nand_flash_dev - NAND Flash Device ID Structure

diff --git a/include/linux/mtd/iflash.h b/include/linux/mtd/iflash.h deleted file mode 100644 index 9aa5b4f02666..000000000000 --- a/include/linux/mtd/iflash.h +++ /dev/null
@@ -1,98 +0,0 @@
1	/* $Id: iflash.h,v 1.2 2000/11/13 18:01:54 dwmw2 Exp $ */
2
3	#ifndef __MTD_IFLASH_H__
4	#define __MTD_IFLASH_H__
5
6	/* Extended CIS registers for Series 2 and 2+ cards */
7	/* The registers are all offsets from 0x4000 */
8	#define CISREG_CSR 0x0100
9	#define CISREG_WP 0x0104
10	#define CISREG_RDYBSY 0x0140
11
12	/* Extended CIS registers for Series 2 cards */
13	#define CISREG_SLEEP 0x0118
14	#define CISREG_RDY_MASK 0x0120
15	#define CISREG_RDY_STATUS 0x0130
16
17	/* Extended CIS registers for Series 2+ cards */
18	#define CISREG_VCR 0x010c
19
20	/* Card Status Register */
21	#define CSR_SRESET 0x20 /* Soft reset */
22	#define CSR_CMWP 0x10 /* Common memory write protect */
23	#define CSR_PWRDOWN 0x08 /* Power down status */
24	#define CSR_CISWP 0x04 /* Common memory CIS WP */
25	#define CSR_WP 0x02 /* Mechanical write protect */
26	#define CSR_READY 0x01 /* Ready/busy status */
27
28	/* Write Protection Register */
29	#define WP_BLKEN 0x04 /* Enable block locking */
30	#define WP_CMWP 0x02 /* Common memory write protect */
31	#define WP_CISWP 0x01 /* Common memory CIS WP */
32
33	/* Voltage Control Register */
34	#define VCR_VCC_LEVEL 0x80 /* 0 = 5V, 1 = 3.3V */
35	#define VCR_VPP_VALID 0x02 /* Vpp Valid */
36	#define VCR_VPP_GEN 0x01 /* Integrated Vpp generator */
37
38	/* Ready/Busy Mode Register */
39	#define RDYBSY_RACK 0x02 /* Ready acknowledge */
40	#define RDYBSY_MODE 0x01 /* 1 = high performance */
41
42	#define LOW(x) ((x) & 0xff)
43
44	/* 28F008SA-Compatible Command Set */
45	#define IF_READ_ARRAY 0xffff
46	#define IF_INTEL_ID 0x9090
47	#define IF_READ_CSR 0x7070
48	#define IF_CLEAR_CSR 0x5050
49	#define IF_WRITE 0x4040
50	#define IF_BLOCK_ERASE 0x2020
51	#define IF_ERASE_SUSPEND 0xb0b0
52	#define IF_CONFIRM 0xd0d0
53
54	/* 28F016SA Performance Enhancement Commands */
55	#define IF_READ_PAGE 0x7575
56	#define IF_PAGE_SWAP 0x7272
57	#define IF_SINGLE_LOAD 0x7474
58	#define IF_SEQ_LOAD 0xe0e0
59	#define IF_PAGE_WRITE 0x0c0c
60	#define IF_RDY_MODE 0x9696
61	#define IF_RDY_LEVEL 0x0101
62	#define IF_RDY_PULSE_WRITE 0x0202
63	#define IF_RDY_PULSE_ERASE 0x0303
64	#define IF_RDY_DISABLE 0x0404
65	#define IF_LOCK_BLOCK 0x7777
66	#define IF_UPLOAD_STATUS 0x9797
67	#define IF_READ_ESR 0x7171
68	#define IF_ERASE_UNLOCKED 0xa7a7
69	#define IF_SLEEP 0xf0f0
70	#define IF_ABORT 0x8080
71	#define IF_UPLOAD_DEVINFO 0x9999
72
73	/* Definitions for Compatible Status Register */
74	#define CSR_WR_READY 0x8080 /* Write state machine status */
75	#define CSR_ERA_SUSPEND 0x4040 /* Erase suspend status */
76	#define CSR_ERA_ERR 0x2020 /* Erase status */
77	#define CSR_WR_ERR 0x1010 /* Data write status */
78	#define CSR_VPP_LOW 0x0808 /* Vpp status */
79
80	/* Definitions for Global Status Register */
81	#define GSR_WR_READY 0x8080 /* Write state machine status */
82	#define GSR_OP_SUSPEND 0x4040 /* Operation suspend status */
83	#define GSR_OP_ERR 0x2020 /* Device operation status */
84	#define GSR_SLEEP 0x1010 /* Device sleep status */
85	#define GSR_QUEUE_FULL 0x0808 /* Queue status */
86	#define GSR_PAGE_AVAIL 0x0404 /* Page buffer available status */
87	#define GSR_PAGE_READY 0x0202 /* Page buffer status */
88	#define GSR_PAGE_SELECT 0x0101 /* Page buffer select status */
89
90	/* Definitions for Block Status Register */
91	#define BSR_READY 0x8080 /* Block status */
92	#define BSR_UNLOCK 0x4040 /* Block lock status */
93	#define BSR_FAILED 0x2020 /* Block operation status */
94	#define BSR_ABORTED 0x1010 /* Operation abort status */
95	#define BSR_QUEUE_FULL 0x0808 /* Queue status */
96	#define BSR_VPP_LOW 0x0404 /* Vpp status */
97
98	#endif /* __MTD_IFLASH_H__ */


diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 3d956c3abb31..45d482ce8397 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h
@@ -53,6 +53,7 @@ struct mtd_erase_region_info {
53	u_int32_t offset; /* At which this region starts, from the beginning of the MTD */	53	u_int32_t offset; /* At which this region starts, from the beginning of the MTD */
54	u_int32_t erasesize; /* For this region */	54	u_int32_t erasesize; /* For this region */
55	u_int32_t numblocks; /* Number of blocks of erasesize in this region */	55	u_int32_t numblocks; /* Number of blocks of erasesize in this region */
		56	unsigned long lockmap; / If keeping bitmap of locks */
56	};	57	};
57		58
58	/*	59	/*


diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 97523887fe5d..cf197ad62da6 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h
@@ -431,6 +431,7 @@ struct nand_chip {
431	#define NAND_MFR_RENESAS 0x07	431	#define NAND_MFR_RENESAS 0x07
432	#define NAND_MFR_STMICRO 0x20	432	#define NAND_MFR_STMICRO 0x20
433	#define NAND_MFR_HYNIX 0xad	433	#define NAND_MFR_HYNIX 0xad
		434	#define NAND_MFR_MICRON 0x2c
434		435
435	/**	436	/**
436	* struct nand_flash_dev - NAND Flash Device ID Structure	437	* struct nand_flash_dev - NAND Flash Device ID Structure