1 files changed, 40 insertions, 0 deletions

diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 9cf4c4c79555..a38e1fa8af01 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -23,6 +23,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/pm_qos.h>
 
 /* FLCTL registers */
 #define FLCMNCR(f)              (f->reg + 0x0)
@@ -38,6 +39,7 @@
 #define FLDTFIFO(f)             (f->reg + 0x24)
 #define FLECFIFO(f)             (f->reg + 0x28)
 #define FLTRCR(f)               (f->reg + 0x2C)
+#define FLHOLDCR(f)             (f->reg + 0x38)
 #define FL4ECCRESULT0(f)        (f->reg + 0x80)
 #define FL4ECCRESULT1(f)        (f->reg + 0x84)
 #define FL4ECCRESULT2(f)        (f->reg + 0x88)
@@ -67,6 +69,30 @@
 #define CE0_ENABLE      (0x1 << 3)      /* Chip Enable 0 */
 #define TYPESEL_SET     (0x1 << 0)
 
+/*
+ * Clock settings using the PULSEx registers from FLCMNCR
+ *
+ * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E
+ * to control the clock divider used between the High-Speed Peripheral Clock
+ * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit
+ * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16
+ * bit version the divider is seperate for the pulse width of high and low
+ * signals.
+ */
+#define PULSE3  (0x1 << 27)
+#define PULSE2  (0x1 << 17)
+#define PULSE1  (0x1 << 15)
+#define PULSE0  (0x1 << 9)
+#define CLK_8B_0_5                      PULSE1
+#define CLK_8B_1                        0x0
+#define CLK_8B_1_5                      (PULSE1 | PULSE2)
+#define CLK_8B_2                        PULSE0
+#define CLK_8B_3                        (PULSE0 | PULSE1 | PULSE2)
+#define CLK_8B_4                        (PULSE0 | PULSE2)
+#define CLK_16B_6L_2H                   PULSE0
+#define CLK_16B_9L_3H                   (PULSE0 | PULSE1 | PULSE2)
+#define CLK_16B_12L_4H                  (PULSE0 | PULSE2)
+
 /* FLCMDCR control bits */
 #define ADRCNT2_E       (0x1 << 31)     /* 5byte address enable */
 #define ADRMD_E         (0x1 << 26)     /* Sector address access */
@@ -85,6 +111,15 @@
 #define TRSTRT          (0x1 << 0)      /* translation start */
 #define TREND           (0x1 << 1)      /* translation end */
 
+/*
+ * FLHOLDCR control bits
+ *
+ * HOLDEN: Bus Occupancy Enable (inverted)
+ * Enable this bit when the external bus might be used in between transfers.
+ * If not set and the bus gets used by other modules, a deadlock occurs.
+ */
+#define HOLDEN          (0x1 << 0)
+
 /* FL4ECCCR control bits */
 #define _4ECCFA         (0x1 << 2)      /* 4 symbols correct fault */
 #define _4ECCEND        (0x1 << 1)      /* 4 symbols end */
@@ -97,6 +132,7 @@ struct sh_flctl {
         struct mtd_info         mtd;
         struct nand_chip        chip;
         struct platform_device  *pdev;
+        struct dev_pm_qos_request pm_qos;
         void __iomem            *reg;
 
         uint8_t done_buff[2048 + 64];   /* max size 2048 + 64 */
@@ -108,11 +144,14 @@ struct sh_flctl {
         int     erase1_page_addr;       /* page_addr in ERASE1 cmd */
         uint32_t erase_ADRCNT;          /* bits of FLCMDCR in ERASE1 cmd */
         uint32_t rw_ADRCNT;     /* bits of FLCMDCR in READ WRITE cmd */
+        uint32_t flcmncr_base;  /* base value of FLCMNCR */
 
         int     hwecc_cant_correct[4];
 
         unsigned page_size:1;   /* NAND page size (0 = 512, 1 = 2048) */
         unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */
+        unsigned holden:1;      /* Hardware has FLHOLDCR and HOLDEN is set */
+        unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
 };
 
 struct sh_flctl_platform_data {
@@ -121,6 +160,7 @@ struct sh_flctl_platform_data {
         unsigned long           flcmncr_val;
 
         unsigned has_hwecc:1;
+        unsigned use_holden:1;
 };
 
 static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)