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-rw-r--r--include/linux/mtd/nand.h355
1 files changed, 206 insertions, 149 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index da5e67b3fc70..66559272ebcb 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -11,52 +11,15 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * Info: 14 * Info:
15 * Contains standard defines and IDs for NAND flash devices 15 * Contains standard defines and IDs for NAND flash devices
16 * 16 *
17 * Changelog: 17 * Changelog:
18 * 01-31-2000 DMW Created 18 * See git changelog.
19 * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
20 * so it can be used by other NAND flash device
21 * drivers. I also changed the copyright since none
22 * of the original contents of this file are specific
23 * to DoC devices. David can whack me with a baseball
24 * bat later if I did something naughty.
25 * 10-11-2000 SJH Added private NAND flash structure for driver
26 * 10-24-2000 SJH Added prototype for 'nand_scan' function
27 * 10-29-2001 TG changed nand_chip structure to support
28 * hardwarespecific function for accessing control lines
29 * 02-21-2002 TG added support for different read/write adress and
30 * ready/busy line access function
31 * 02-26-2002 TG added chip_delay to nand_chip structure to optimize
32 * command delay times for different chips
33 * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
34 * defines in jffs2/wbuf.c
35 * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
36 * CONFIG_MTD_NAND_ECC_JFFS2 is not set
37 * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
38 *
39 * 08-29-2002 tglx nand_chip structure: data_poi for selecting
40 * internal / fs-driver buffer
41 * support for 6byte/512byte hardware ECC
42 * read_ecc, write_ecc extended for different oob-layout
43 * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
44 * NAND_YAFFS_OOB
45 * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
46 * Split manufacturer and device ID structures
47 *
48 * 02-08-2004 tglx added option field to nand structure for chip anomalities
49 * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
50 * update of nand_chip structure description
51 * 01-17-2005 dmarlin added extended commands for AG-AND device and added option
52 * for BBT_AUTO_REFRESH.
53 * 01-20-2005 dmarlin added optional pointer to hardware specific callback for
54 * extra error status checks.
55 */ 19 */
56#ifndef __LINUX_MTD_NAND_H 20#ifndef __LINUX_MTD_NAND_H
57#define __LINUX_MTD_NAND_H 21#define __LINUX_MTD_NAND_H
58 22
59#include <linux/config.h>
60#include <linux/wait.h> 23#include <linux/wait.h>
61#include <linux/spinlock.h> 24#include <linux/spinlock.h>
62#include <linux/mtd/mtd.h> 25#include <linux/mtd/mtd.h>
@@ -67,10 +30,6 @@ extern int nand_scan (struct mtd_info *mtd, int max_chips);
67/* Free resources held by the NAND device */ 30/* Free resources held by the NAND device */
68extern void nand_release (struct mtd_info *mtd); 31extern void nand_release (struct mtd_info *mtd);
69 32
70/* Read raw data from the device without ECC */
71extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
72
73
74/* The maximum number of NAND chips in an array */ 33/* The maximum number of NAND chips in an array */
75#define NAND_MAX_CHIPS 8 34#define NAND_MAX_CHIPS 8
76 35
@@ -79,44 +38,45 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
79 * adjust this accordingly. 38 * adjust this accordingly.
80 */ 39 */
81#define NAND_MAX_OOBSIZE 64 40#define NAND_MAX_OOBSIZE 64
41#define NAND_MAX_PAGESIZE 2048
82 42
83/* 43/*
84 * Constants for hardware specific CLE/ALE/NCE function 44 * Constants for hardware specific CLE/ALE/NCE function
85*/ 45 *
46 * These are bits which can be or'ed to set/clear multiple
47 * bits in one go.
48 */
86/* Select the chip by setting nCE to low */ 49/* Select the chip by setting nCE to low */
87#define NAND_CTL_SETNCE 1 50#define NAND_NCE 0x01
88/* Deselect the chip by setting nCE to high */
89#define NAND_CTL_CLRNCE 2
90/* Select the command latch by setting CLE to high */ 51/* Select the command latch by setting CLE to high */
91#define NAND_CTL_SETCLE 3 52#define NAND_CLE 0x02
92/* Deselect the command latch by setting CLE to low */
93#define NAND_CTL_CLRCLE 4
94/* Select the address latch by setting ALE to high */ 53/* Select the address latch by setting ALE to high */
95#define NAND_CTL_SETALE 5 54#define NAND_ALE 0x04
96/* Deselect the address latch by setting ALE to low */ 55
97#define NAND_CTL_CLRALE 6 56#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
98/* Set write protection by setting WP to high. Not used! */ 57#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
99#define NAND_CTL_SETWP 7 58#define NAND_CTRL_CHANGE 0x80
100/* Clear write protection by setting WP to low. Not used! */
101#define NAND_CTL_CLRWP 8
102 59
103/* 60/*
104 * Standard NAND flash commands 61 * Standard NAND flash commands
105 */ 62 */
106#define NAND_CMD_READ0 0 63#define NAND_CMD_READ0 0
107#define NAND_CMD_READ1 1 64#define NAND_CMD_READ1 1
65#define NAND_CMD_RNDOUT 5
108#define NAND_CMD_PAGEPROG 0x10 66#define NAND_CMD_PAGEPROG 0x10
109#define NAND_CMD_READOOB 0x50 67#define NAND_CMD_READOOB 0x50
110#define NAND_CMD_ERASE1 0x60 68#define NAND_CMD_ERASE1 0x60
111#define NAND_CMD_STATUS 0x70 69#define NAND_CMD_STATUS 0x70
112#define NAND_CMD_STATUS_MULTI 0x71 70#define NAND_CMD_STATUS_MULTI 0x71
113#define NAND_CMD_SEQIN 0x80 71#define NAND_CMD_SEQIN 0x80
72#define NAND_CMD_RNDIN 0x85
114#define NAND_CMD_READID 0x90 73#define NAND_CMD_READID 0x90
115#define NAND_CMD_ERASE2 0xd0 74#define NAND_CMD_ERASE2 0xd0
116#define NAND_CMD_RESET 0xff 75#define NAND_CMD_RESET 0xff
117 76
118/* Extended commands for large page devices */ 77/* Extended commands for large page devices */
119#define NAND_CMD_READSTART 0x30 78#define NAND_CMD_READSTART 0x30
79#define NAND_CMD_RNDOUTSTART 0xE0
120#define NAND_CMD_CACHEDPROG 0x15 80#define NAND_CMD_CACHEDPROG 0x15
121 81
122/* Extended commands for AG-AND device */ 82/* Extended commands for AG-AND device */
@@ -138,6 +98,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
138#define NAND_CMD_STATUS_RESET 0x7f 98#define NAND_CMD_STATUS_RESET 0x7f
139#define NAND_CMD_STATUS_CLEAR 0xff 99#define NAND_CMD_STATUS_CLEAR 0xff
140 100
101#define NAND_CMD_NONE -1
102
141/* Status bits */ 103/* Status bits */
142#define NAND_STATUS_FAIL 0x01 104#define NAND_STATUS_FAIL 0x01
143#define NAND_STATUS_FAIL_N1 0x02 105#define NAND_STATUS_FAIL_N1 0x02
@@ -148,21 +110,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
148/* 110/*
149 * Constants for ECC_MODES 111 * Constants for ECC_MODES
150 */ 112 */
151 113typedef enum {
152/* No ECC. Usage is not recommended ! */ 114 NAND_ECC_NONE,
153#define NAND_ECC_NONE 0 115 NAND_ECC_SOFT,
154/* Software ECC 3 byte ECC per 256 Byte data */ 116 NAND_ECC_HW,
155#define NAND_ECC_SOFT 1 117 NAND_ECC_HW_SYNDROME,
156/* Hardware ECC 3 byte ECC per 256 Byte data */ 118} nand_ecc_modes_t;
157#define NAND_ECC_HW3_256 2
158/* Hardware ECC 3 byte ECC per 512 Byte data */
159#define NAND_ECC_HW3_512 3
160/* Hardware ECC 3 byte ECC per 512 Byte data */
161#define NAND_ECC_HW6_512 4
162/* Hardware ECC 8 byte ECC per 512 Byte data */
163#define NAND_ECC_HW8_512 6
164/* Hardware ECC 12 byte ECC per 2048 Byte data */
165#define NAND_ECC_HW12_2048 7
166 119
167/* 120/*
168 * Constants for Hardware ECC 121 * Constants for Hardware ECC
@@ -201,6 +154,10 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
201 * bits from adjacent blocks from 'leaking' in altering data. 154 * bits from adjacent blocks from 'leaking' in altering data.
202 * This happens with the Renesas AG-AND chips, possibly others. */ 155 * This happens with the Renesas AG-AND chips, possibly others. */
203#define BBT_AUTO_REFRESH 0x00000080 156#define BBT_AUTO_REFRESH 0x00000080
157/* Chip does not require ready check on read. True
158 * for all large page devices, as they do not support
159 * autoincrement.*/
160#define NAND_NO_READRDY 0x00000100
204 161
205/* Options valid for Samsung large page devices */ 162/* Options valid for Samsung large page devices */
206#define NAND_SAMSUNG_LP_OPTIONS \ 163#define NAND_SAMSUNG_LP_OPTIONS \
@@ -219,18 +176,12 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
219/* Use a flash based bad block table. This option is passed to the 176/* Use a flash based bad block table. This option is passed to the
220 * default bad block table function. */ 177 * default bad block table function. */
221#define NAND_USE_FLASH_BBT 0x00010000 178#define NAND_USE_FLASH_BBT 0x00010000
222/* The hw ecc generator provides a syndrome instead a ecc value on read
223 * This can only work if we have the ecc bytes directly behind the
224 * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
225#define NAND_HWECC_SYNDROME 0x00020000
226/* This option skips the bbt scan during initialization. */ 179/* This option skips the bbt scan during initialization. */
227#define NAND_SKIP_BBTSCAN 0x00040000 180#define NAND_SKIP_BBTSCAN 0x00020000
228 181
229/* Options set by nand scan */ 182/* Options set by nand scan */
230/* Nand scan has allocated oob_buf */ 183/* Nand scan has allocated controller struct */
231#define NAND_OOBBUF_ALLOC 0x40000000 184#define NAND_CONTROLLER_ALLOC 0x80000000
232/* Nand scan has allocated data_buf */
233#define NAND_DATABUF_ALLOC 0x80000000
234 185
235 186
236/* 187/*
@@ -264,45 +215,102 @@ struct nand_hw_control {
264}; 215};
265 216
266/** 217/**
218 * struct nand_ecc_ctrl - Control structure for ecc
219 * @mode: ecc mode
220 * @steps: number of ecc steps per page
221 * @size: data bytes per ecc step
222 * @bytes: ecc bytes per step
223 * @total: total number of ecc bytes per page
224 * @prepad: padding information for syndrome based ecc generators
225 * @postpad: padding information for syndrome based ecc generators
226 * @hwctl: function to control hardware ecc generator. Must only
227 * be provided if an hardware ECC is available
228 * @calculate: function for ecc calculation or readback from ecc hardware
229 * @correct: function for ecc correction, matching to ecc generator (sw/hw)
230 * @read_page: function to read a page according to the ecc generator requirements
231 * @write_page: function to write a page according to the ecc generator requirements
232 */
233struct nand_ecc_ctrl {
234 nand_ecc_modes_t mode;
235 int steps;
236 int size;
237 int bytes;
238 int total;
239 int prepad;
240 int postpad;
241 struct nand_ecclayout *layout;
242 void (*hwctl)(struct mtd_info *mtd, int mode);
243 int (*calculate)(struct mtd_info *mtd,
244 const uint8_t *dat,
245 uint8_t *ecc_code);
246 int (*correct)(struct mtd_info *mtd, uint8_t *dat,
247 uint8_t *read_ecc,
248 uint8_t *calc_ecc);
249 int (*read_page)(struct mtd_info *mtd,
250 struct nand_chip *chip,
251 uint8_t *buf);
252 void (*write_page)(struct mtd_info *mtd,
253 struct nand_chip *chip,
254 const uint8_t *buf);
255 int (*read_oob)(struct mtd_info *mtd,
256 struct nand_chip *chip,
257 int page,
258 int sndcmd);
259 int (*write_oob)(struct mtd_info *mtd,
260 struct nand_chip *chip,
261 int page);
262};
263
264/**
265 * struct nand_buffers - buffer structure for read/write
266 * @ecccalc: buffer for calculated ecc
267 * @ecccode: buffer for ecc read from flash
268 * @oobwbuf: buffer for write oob data
269 * @databuf: buffer for data - dynamically sized
270 * @oobrbuf: buffer to read oob data
271 *
272 * Do not change the order of buffers. databuf and oobrbuf must be in
273 * consecutive order.
274 */
275struct nand_buffers {
276 uint8_t ecccalc[NAND_MAX_OOBSIZE];
277 uint8_t ecccode[NAND_MAX_OOBSIZE];
278 uint8_t oobwbuf[NAND_MAX_OOBSIZE];
279 uint8_t databuf[NAND_MAX_PAGESIZE];
280 uint8_t oobrbuf[NAND_MAX_OOBSIZE];
281};
282
283/**
267 * struct nand_chip - NAND Private Flash Chip Data 284 * struct nand_chip - NAND Private Flash Chip Data
268 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 285 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
269 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 286 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
270 * @read_byte: [REPLACEABLE] read one byte from the chip 287 * @read_byte: [REPLACEABLE] read one byte from the chip
271 * @write_byte: [REPLACEABLE] write one byte to the chip
272 * @read_word: [REPLACEABLE] read one word from the chip 288 * @read_word: [REPLACEABLE] read one word from the chip
273 * @write_word: [REPLACEABLE] write one word to the chip
274 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 289 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
275 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 290 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
276 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 291 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
277 * @select_chip: [REPLACEABLE] select chip nr 292 * @select_chip: [REPLACEABLE] select chip nr
278 * @block_bad: [REPLACEABLE] check, if the block is bad 293 * @block_bad: [REPLACEABLE] check, if the block is bad
279 * @block_markbad: [REPLACEABLE] mark the block bad 294 * @block_markbad: [REPLACEABLE] mark the block bad
280 * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines 295 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
296 * ALE/CLE/nCE. Also used to write command and address
281 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 297 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
282 * If set to NULL no access to ready/busy is available and the ready/busy information 298 * If set to NULL no access to ready/busy is available and the ready/busy information
283 * is read from the chip status register 299 * is read from the chip status register
284 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 300 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
285 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 301 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
286 * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware 302 * @ecc: [BOARDSPECIFIC] ecc control ctructure
287 * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
288 * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
289 * be provided if a hardware ECC is available
290 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 303 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
291 * @scan_bbt: [REPLACEABLE] function to scan bad block table 304 * @scan_bbt: [REPLACEABLE] function to scan bad block table
292 * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
293 * @eccsize: [INTERN] databytes used per ecc-calculation
294 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
295 * @eccsteps: [INTERN] number of ecc calculation steps per page
296 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 305 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
297 * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
298 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 306 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
299 * @state: [INTERN] the current state of the NAND device 307 * @state: [INTERN] the current state of the NAND device
300 * @page_shift: [INTERN] number of address bits in a page (column address bits) 308 * @page_shift: [INTERN] number of address bits in a page (column address bits)
301 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 309 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
302 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 310 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
303 * @chip_shift: [INTERN] number of address bits in one chip 311 * @chip_shift: [INTERN] number of address bits in one chip
304 * @data_buf: [INTERN] internal buffer for one page + oob 312 * @datbuf: [INTERN] internal buffer for one page + oob
305 * @oob_buf: [INTERN] oob buffer for one eraseblock 313 * @oobbuf: [INTERN] oob buffer for one eraseblock
306 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized 314 * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
307 * @data_poi: [INTERN] pointer to a data buffer 315 * @data_poi: [INTERN] pointer to a data buffer
308 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 316 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
@@ -312,12 +320,13 @@ struct nand_hw_control {
312 * @chipsize: [INTERN] the size of one chip for multichip arrays 320 * @chipsize: [INTERN] the size of one chip for multichip arrays
313 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 321 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
314 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 322 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
315 * @autooob: [REPLACEABLE] the default (auto)placement scheme 323 * @ecclayout: [REPLACEABLE] the default ecc placement scheme
316 * @bbt: [INTERN] bad block table pointer 324 * @bbt: [INTERN] bad block table pointer
317 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 325 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
318 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 326 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
319 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 327 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
320 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices 328 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
329 * which is shared among multiple independend devices
321 * @priv: [OPTIONAL] pointer to private chip date 330 * @priv: [OPTIONAL] pointer to private chip date
322 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 331 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
323 * (determine if errors are correctable) 332 * (determine if errors are correctable)
@@ -325,58 +334,57 @@ struct nand_hw_control {
325 334
326struct nand_chip { 335struct nand_chip {
327 void __iomem *IO_ADDR_R; 336 void __iomem *IO_ADDR_R;
328 void __iomem *IO_ADDR_W; 337 void __iomem *IO_ADDR_W;
329 338
330 u_char (*read_byte)(struct mtd_info *mtd); 339 uint8_t (*read_byte)(struct mtd_info *mtd);
331 void (*write_byte)(struct mtd_info *mtd, u_char byte);
332 u16 (*read_word)(struct mtd_info *mtd); 340 u16 (*read_word)(struct mtd_info *mtd);
333 void (*write_word)(struct mtd_info *mtd, u16 word); 341 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
334 342 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
335 void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); 343 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
336 void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
337 int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
338 void (*select_chip)(struct mtd_info *mtd, int chip); 344 void (*select_chip)(struct mtd_info *mtd, int chip);
339 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 345 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
340 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 346 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
341 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 347 void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
342 int (*dev_ready)(struct mtd_info *mtd); 348 unsigned int ctrl);
343 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 349 int (*dev_ready)(struct mtd_info *mtd);
344 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); 350 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
345 int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); 351 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
346 int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
347 void (*enable_hwecc)(struct mtd_info *mtd, int mode);
348 void (*erase_cmd)(struct mtd_info *mtd, int page); 352 void (*erase_cmd)(struct mtd_info *mtd, int page);
349 int (*scan_bbt)(struct mtd_info *mtd); 353 int (*scan_bbt)(struct mtd_info *mtd);
350 int eccmode; 354 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
351 int eccsize; 355
352 int eccbytes; 356 int chip_delay;
353 int eccsteps; 357 unsigned int options;
354 int chip_delay; 358
355 spinlock_t chip_lock; 359 int page_shift;
356 wait_queue_head_t wq;
357 nand_state_t state;
358 int page_shift;
359 int phys_erase_shift; 360 int phys_erase_shift;
360 int bbt_erase_shift; 361 int bbt_erase_shift;
361 int chip_shift; 362 int chip_shift;
362 u_char *data_buf;
363 u_char *oob_buf;
364 int oobdirty;
365 u_char *data_poi;
366 unsigned int options;
367 int badblockpos;
368 int numchips; 363 int numchips;
369 unsigned long chipsize; 364 unsigned long chipsize;
370 int pagemask; 365 int pagemask;
371 int pagebuf; 366 int pagebuf;
372 struct nand_oobinfo *autooob; 367 int badblockpos;
368
369 nand_state_t state;
370
371 uint8_t *oob_poi;
372 struct nand_hw_control *controller;
373 struct nand_ecclayout *ecclayout;
374
375 struct nand_ecc_ctrl ecc;
376 struct nand_buffers buffers;
377 struct nand_hw_control hwcontrol;
378
379 struct mtd_oob_ops ops;
380
373 uint8_t *bbt; 381 uint8_t *bbt;
374 struct nand_bbt_descr *bbt_td; 382 struct nand_bbt_descr *bbt_td;
375 struct nand_bbt_descr *bbt_md; 383 struct nand_bbt_descr *bbt_md;
384
376 struct nand_bbt_descr *badblock_pattern; 385 struct nand_bbt_descr *badblock_pattern;
377 struct nand_hw_control *controller; 386
378 void *priv; 387 void *priv;
379 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
380}; 388};
381 389
382/* 390/*
@@ -388,19 +396,19 @@ struct nand_chip {
388#define NAND_MFR_NATIONAL 0x8f 396#define NAND_MFR_NATIONAL 0x8f
389#define NAND_MFR_RENESAS 0x07 397#define NAND_MFR_RENESAS 0x07
390#define NAND_MFR_STMICRO 0x20 398#define NAND_MFR_STMICRO 0x20
391#define NAND_MFR_HYNIX 0xad 399#define NAND_MFR_HYNIX 0xad
392 400
393/** 401/**
394 * struct nand_flash_dev - NAND Flash Device ID Structure 402 * struct nand_flash_dev - NAND Flash Device ID Structure
395 * 403 *
396 * @name: Identify the device type 404 * @name: Identify the device type
397 * @id: device ID code 405 * @id: device ID code
398 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 406 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
399 * If the pagesize is 0, then the real pagesize 407 * If the pagesize is 0, then the real pagesize
400 * and the eraseize are determined from the 408 * and the eraseize are determined from the
401 * extended id bytes in the chip 409 * extended id bytes in the chip
402 * @erasesize: Size of an erase block in the flash device. 410 * @erasesize: Size of an erase block in the flash device.
403 * @chipsize: Total chipsize in Mega Bytes 411 * @chipsize: Total chipsize in Mega Bytes
404 * @options: Bitfield to store chip relevant options 412 * @options: Bitfield to store chip relevant options
405 */ 413 */
406struct nand_flash_dev { 414struct nand_flash_dev {
@@ -415,7 +423,7 @@ struct nand_flash_dev {
415/** 423/**
416 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 424 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
417 * @name: Manufacturer name 425 * @name: Manufacturer name
418 * @id: manufacturer ID code of device. 426 * @id: manufacturer ID code of device.
419*/ 427*/
420struct nand_manufacturers { 428struct nand_manufacturers {
421 int id; 429 int id;
@@ -455,7 +463,7 @@ struct nand_bbt_descr {
455 int veroffs; 463 int veroffs;
456 uint8_t version[NAND_MAX_CHIPS]; 464 uint8_t version[NAND_MAX_CHIPS];
457 int len; 465 int len;
458 int maxblocks; 466 int maxblocks;
459 int reserved_block_code; 467 int reserved_block_code;
460 uint8_t *pattern; 468 uint8_t *pattern;
461}; 469};
@@ -494,14 +502,14 @@ struct nand_bbt_descr {
494/* The maximum number of blocks to scan for a bbt */ 502/* The maximum number of blocks to scan for a bbt */
495#define NAND_BBT_SCAN_MAXBLOCKS 4 503#define NAND_BBT_SCAN_MAXBLOCKS 4
496 504
497extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); 505extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
498extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); 506extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
499extern int nand_default_bbt (struct mtd_info *mtd); 507extern int nand_default_bbt(struct mtd_info *mtd);
500extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); 508extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
501extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); 509extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
502extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, 510 int allowbbt);
503 size_t * retlen, u_char * buf, u_char * oob_buf, 511extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
504 struct nand_oobinfo *oobsel, int flags); 512 size_t * retlen, uint8_t * buf);
505 513
506/* 514/*
507* Constants for oob configuration 515* Constants for oob configuration
@@ -509,4 +517,53 @@ extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
509#define NAND_SMALL_BADBLOCK_POS 5 517#define NAND_SMALL_BADBLOCK_POS 5
510#define NAND_LARGE_BADBLOCK_POS 0 518#define NAND_LARGE_BADBLOCK_POS 0
511 519
520/**
521 * struct platform_nand_chip - chip level device structure
522 *
523 * @nr_chips: max. number of chips to scan for
524 * @chip_offs: chip number offset
525 * @nr_partitions: number of partitions pointed to by partitions (or zero)
526 * @partitions: mtd partition list
527 * @chip_delay: R/B delay value in us
528 * @options: Option flags, e.g. 16bit buswidth
529 * @ecclayout: ecc layout info structure
530 * @priv: hardware controller specific settings
531 */
532struct platform_nand_chip {
533 int nr_chips;
534 int chip_offset;
535 int nr_partitions;
536 struct mtd_partition *partitions;
537 struct nand_ecclayout *ecclayout;
538 int chip_delay;
539 unsigned int options;
540 void *priv;
541};
542
543/**
544 * struct platform_nand_ctrl - controller level device structure
545 *
546 * @hwcontrol: platform specific hardware control structure
547 * @dev_ready: platform specific function to read ready/busy pin
548 * @select_chip: platform specific chip select function
549 * @priv_data: private data to transport driver specific settings
550 *
551 * All fields are optional and depend on the hardware driver requirements
552 */
553struct platform_nand_ctrl {
554 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
555 int (*dev_ready)(struct mtd_info *mtd);
556 void (*select_chip)(struct mtd_info *mtd, int chip);
557 void *priv;
558};
559
560/* Some helpers to access the data structures */
561static inline
562struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
563{
564 struct nand_chip *chip = mtd->priv;
565
566 return chip->priv;
567}
568
512#endif /* __LINUX_MTD_NAND_H */ 569#endif /* __LINUX_MTD_NAND_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 00:50:09 -0500