1 files changed, 61 insertions, 60 deletions

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index ef52d9c91459..ab6363443ce8 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -86,7 +86,6 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_READOOB        0x50
 #define NAND_CMD_ERASE1         0x60
 #define NAND_CMD_STATUS         0x70
-#define NAND_CMD_STATUS_MULTI   0x71
 #define NAND_CMD_SEQIN          0x80
 #define NAND_CMD_RNDIN          0x85
 #define NAND_CMD_READID         0x90
@@ -105,25 +104,6 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_RNDOUTSTART    0xE0
 #define NAND_CMD_CACHEDPROG     0x15
 
-/* Extended commands for AG-AND device */
-/*
- * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
- *       there is no way to distinguish that from NAND_CMD_READ0
- *       until the remaining sequence of commands has been completed
- *       so add a high order bit and mask it off in the command.
- */
-#define NAND_CMD_DEPLETE1       0x100
-#define NAND_CMD_DEPLETE2       0x38
-#define NAND_CMD_STATUS_MULTI   0x71
-#define NAND_CMD_STATUS_ERROR   0x72
-/* multi-bank error status (banks 0-3) */
-#define NAND_CMD_STATUS_ERROR0  0x73
-#define NAND_CMD_STATUS_ERROR1  0x74
-#define NAND_CMD_STATUS_ERROR2  0x75
-#define NAND_CMD_STATUS_ERROR3  0x76
-#define NAND_CMD_STATUS_RESET   0x7f
-#define NAND_CMD_STATUS_CLEAR   0xff
-
 #define NAND_CMD_NONE           -1
 
 /* Status bits */
@@ -165,28 +145,8 @@ typedef enum {
  */
 /* Buswidth is 16 bit */
 #define NAND_BUSWIDTH_16        0x00000002
-/* Device supports partial programming without padding */
-#define NAND_NO_PADDING         0x00000004
 /* Chip has cache program function */
 #define NAND_CACHEPRG           0x00000008
-/* Chip has copy back function */
-#define NAND_COPYBACK           0x00000010
-/*
- * AND Chip which has 4 banks and a confusing page / block
- * assignment. See Renesas datasheet for further information.
- */
-#define NAND_IS_AND             0x00000020
-/*
- * Chip has a array of 4 pages which can be read without
- * additional ready /busy waits.
- */
-#define NAND_4PAGE_ARRAY        0x00000040
-/*
- * Chip requires that BBT is periodically rewritten to prevent
- * bits from adjacent blocks from 'leaking' in altering data.
- * This happens with the Renesas AG-AND chips, possibly others.
- */
-#define BBT_AUTO_REFRESH        0x00000080
 /*
  * Chip requires ready check on read (for auto-incremented sequential read).
  * True only for small page devices; large page devices do not support
@@ -207,13 +167,10 @@ typedef enum {
 #define NAND_SUBPAGE_READ       0x00001000
 
 /* Options valid for Samsung large page devices */
-#define NAND_SAMSUNG_LP_OPTIONS \
-        (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 
 /* Macros to identify the above */
-#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
-#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
 
 /* Non chip related options */
@@ -361,6 +318,7 @@ struct nand_hw_control {
  *              any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  * @read_subpage:       function to read parts of the page covered by ECC;
  *                      returns same as read_page()
+ * @write_subpage:      function to write parts of the page covered by ECC.
  * @write_page: function to write a page according to the ECC generator
  *              requirements.
  * @write_oob_raw:      function to write chip OOB data without ECC
@@ -392,6 +350,9 @@ struct nand_ecc_ctrl {
                         uint8_t *buf, int oob_required, int page);
         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
                         uint32_t offs, uint32_t len, uint8_t *buf);
+        int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+                        uint32_t offset, uint32_t data_len,
+                        const uint8_t *data_buf, int oob_required);
         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
                         const uint8_t *buf, int oob_required);
         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
@@ -527,8 +488,8 @@ struct nand_chip {
         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
                         int status, int page);
         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
-                        const uint8_t *buf, int oob_required, int page,
-                        int cached, int raw);
+                        uint32_t offset, int data_len, const uint8_t *buf,
+                        int oob_required, int page, int cached, int raw);
         int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
                         int feature_addr, uint8_t *subfeature_para);
         int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
@@ -589,25 +550,65 @@ struct nand_chip {
 #define NAND_MFR_MACRONIX       0xc2
 #define NAND_MFR_EON            0x92
 
+/* The maximum expected count of bytes in the NAND ID sequence */
+#define NAND_MAX_ID_LEN 8
+
+/*
+ * A helper for defining older NAND chips where the second ID byte fully
+ * defined the chip, including the geometry (chip size, eraseblock size, page
+ * size). All these chips have 512 bytes NAND page size.
+ */
+#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
+        { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
+          .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
+
+/*
+ * A helper for defining newer chips which report their page size and
+ * eraseblock size via the extended ID bytes.
+ *
+ * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
+ * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
+ * device ID now only represented a particular total chip size (and voltage,
+ * buswidth), and the page size, eraseblock size, and OOB size could vary while
+ * using the same device ID.
+ */
+#define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
+        { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
+          .options = (opts) }
+
 /**
  * struct nand_flash_dev - NAND Flash Device ID Structure
- * @name:       Identify the device type
- * @id:         device ID code
- * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
- *              If the pagesize is 0, then the real pagesize
- *              and the eraseize are determined from the
- *              extended id bytes in the chip
- * @erasesize:  Size of an erase block in the flash device.
- * @chipsize:   Total chipsize in Mega Bytes
- * @options:    Bitfield to store chip relevant options
+ * @name: a human-readable name of the NAND chip
+ * @dev_id: the device ID (the second byte of the full chip ID array)
+ * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
+ *          memory address as @id[0])
+ * @dev_id: device ID part of the full chip ID array (refers the same memory
+ *          address as @id[1])
+ * @id: full device ID array
+ * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
+ *            well as the eraseblock size) is determined from the extended NAND
+ *            chip ID array)
+ * @chipsize: total chip size in MiB
+ * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
+ * @options: stores various chip bit options
+ * @id_len: The valid length of the @id.
+ * @oobsize: OOB size
  */
 struct nand_flash_dev {
         char *name;
-        int id;
-        unsigned long pagesize;
-        unsigned long chipsize;
-        unsigned long erasesize;
-        unsigned long options;
+        union {
+                struct {
+                        uint8_t mfr_id;
+                        uint8_t dev_id;
+                };
+                uint8_t id[NAND_MAX_ID_LEN];
+        };
+        unsigned int pagesize;
+        unsigned int chipsize;
+        unsigned int erasesize;
+        unsigned int options;
+        uint16_t id_len;
+        uint16_t oobsize;
 };
 
 /**