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-rw-r--r--include/linux/mmc/Kbuild1
-rw-r--r--include/linux/mmc/boot.h7
-rw-r--r--include/linux/mmc/card.h212
-rw-r--r--include/linux/mmc/core.h8
-rw-r--r--include/linux/mmc/dw_mmc.h222
-rw-r--r--include/linux/mmc/host.h115
-rw-r--r--include/linux/mmc/ioctl.h54
-rw-r--r--include/linux/mmc/mmc.h33
-rw-r--r--include/linux/mmc/sd.h9
-rw-r--r--include/linux/mmc/sdhci-pltfm.h35
-rw-r--r--include/linux/mmc/sdhci.h165
-rw-r--r--include/linux/mmc/sdio_ids.h1
-rw-r--r--include/linux/mmc/sh_mmcif.h109
-rw-r--r--include/linux/mmc/sh_mobile_sdhi.h20
-rw-r--r--include/linux/mmc/tmio.h63
15 files changed, 1003 insertions, 51 deletions
diff --git a/include/linux/mmc/Kbuild b/include/linux/mmc/Kbuild
new file mode 100644
index 000000000000..1fb26448faa9
--- /dev/null
+++ b/include/linux/mmc/Kbuild
@@ -0,0 +1 @@
header-y += ioctl.h
diff --git a/include/linux/mmc/boot.h b/include/linux/mmc/boot.h
new file mode 100644
index 000000000000..39d787c229cb
--- /dev/null
+++ b/include/linux/mmc/boot.h
@@ -0,0 +1,7 @@
1#ifndef MMC_BOOT_H
2#define MMC_BOOT_H
3
4enum { MMC_PROGRESS_ENTER, MMC_PROGRESS_INIT,
5 MMC_PROGRESS_LOAD, MMC_PROGRESS_DONE };
6
7#endif
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 6b7525099e56..6ad43554ac05 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -11,6 +11,7 @@
11#define LINUX_MMC_CARD_H 11#define LINUX_MMC_CARD_H
12 12
13#include <linux/mmc/core.h> 13#include <linux/mmc/core.h>
14#include <linux/mod_devicetable.h>
14 15
15struct mmc_cid { 16struct mmc_cid {
16 unsigned int manfid; 17 unsigned int manfid;
@@ -29,6 +30,7 @@ struct mmc_csd {
29 unsigned short cmdclass; 30 unsigned short cmdclass;
30 unsigned short tacc_clks; 31 unsigned short tacc_clks;
31 unsigned int tacc_ns; 32 unsigned int tacc_ns;
33 unsigned int c_size;
32 unsigned int r2w_factor; 34 unsigned int r2w_factor;
33 unsigned int max_dtr; 35 unsigned int max_dtr;
34 unsigned int erase_size; /* In sectors */ 36 unsigned int erase_size; /* In sectors */
@@ -45,21 +47,47 @@ struct mmc_ext_csd {
45 u8 rev; 47 u8 rev;
46 u8 erase_group_def; 48 u8 erase_group_def;
47 u8 sec_feature_support; 49 u8 sec_feature_support;
50 u8 rel_sectors;
51 u8 rel_param;
52 u8 part_config;
53 unsigned int part_time; /* Units: ms */
48 unsigned int sa_timeout; /* Units: 100ns */ 54 unsigned int sa_timeout; /* Units: 100ns */
49 unsigned int hs_max_dtr; 55 unsigned int hs_max_dtr;
50 unsigned int sectors; 56 unsigned int sectors;
57 unsigned int card_type;
51 unsigned int hc_erase_size; /* In sectors */ 58 unsigned int hc_erase_size; /* In sectors */
52 unsigned int hc_erase_timeout; /* In milliseconds */ 59 unsigned int hc_erase_timeout; /* In milliseconds */
53 unsigned int sec_trim_mult; /* Secure trim multiplier */ 60 unsigned int sec_trim_mult; /* Secure trim multiplier */
54 unsigned int sec_erase_mult; /* Secure erase multiplier */ 61 unsigned int sec_erase_mult; /* Secure erase multiplier */
55 unsigned int trim_timeout; /* In milliseconds */ 62 unsigned int trim_timeout; /* In milliseconds */
63 bool enhanced_area_en; /* enable bit */
64 unsigned long long enhanced_area_offset; /* Units: Byte */
65 unsigned int enhanced_area_size; /* Units: KB */
66 unsigned int boot_size; /* in bytes */
67 u8 raw_partition_support; /* 160 */
68 u8 raw_erased_mem_count; /* 181 */
69 u8 raw_ext_csd_structure; /* 194 */
70 u8 raw_card_type; /* 196 */
71 u8 raw_s_a_timeout; /* 217 */
72 u8 raw_hc_erase_gap_size; /* 221 */
73 u8 raw_erase_timeout_mult; /* 223 */
74 u8 raw_hc_erase_grp_size; /* 224 */
75 u8 raw_sec_trim_mult; /* 229 */
76 u8 raw_sec_erase_mult; /* 230 */
77 u8 raw_sec_feature_support;/* 231 */
78 u8 raw_trim_mult; /* 232 */
79 u8 raw_sectors[4]; /* 212 - 4 bytes */
56}; 80};
57 81
58struct sd_scr { 82struct sd_scr {
59 unsigned char sda_vsn; 83 unsigned char sda_vsn;
84 unsigned char sda_spec3;
60 unsigned char bus_widths; 85 unsigned char bus_widths;
61#define SD_SCR_BUS_WIDTH_1 (1<<0) 86#define SD_SCR_BUS_WIDTH_1 (1<<0)
62#define SD_SCR_BUS_WIDTH_4 (1<<2) 87#define SD_SCR_BUS_WIDTH_4 (1<<2)
88 unsigned char cmds;
89#define SD_SCR_CMD20_SUPPORT (1<<0)
90#define SD_SCR_CMD23_SUPPORT (1<<1)
63}; 91};
64 92
65struct sd_ssr { 93struct sd_ssr {
@@ -70,6 +98,39 @@ struct sd_ssr {
70 98
71struct sd_switch_caps { 99struct sd_switch_caps {
72 unsigned int hs_max_dtr; 100 unsigned int hs_max_dtr;
101 unsigned int uhs_max_dtr;
102#define UHS_SDR104_MAX_DTR 208000000
103#define UHS_SDR50_MAX_DTR 100000000
104#define UHS_DDR50_MAX_DTR 50000000
105#define UHS_SDR25_MAX_DTR UHS_DDR50_MAX_DTR
106#define UHS_SDR12_MAX_DTR 25000000
107 unsigned int sd3_bus_mode;
108#define UHS_SDR12_BUS_SPEED 0
109#define UHS_SDR25_BUS_SPEED 1
110#define UHS_SDR50_BUS_SPEED 2
111#define UHS_SDR104_BUS_SPEED 3
112#define UHS_DDR50_BUS_SPEED 4
113
114#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
115#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
116#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
117#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
118#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
119 unsigned int sd3_drv_type;
120#define SD_DRIVER_TYPE_B 0x01
121#define SD_DRIVER_TYPE_A 0x02
122#define SD_DRIVER_TYPE_C 0x04
123#define SD_DRIVER_TYPE_D 0x08
124 unsigned int sd3_curr_limit;
125#define SD_SET_CURRENT_LIMIT_200 0
126#define SD_SET_CURRENT_LIMIT_400 1
127#define SD_SET_CURRENT_LIMIT_600 2
128#define SD_SET_CURRENT_LIMIT_800 3
129
130#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
131#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
132#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
133#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
73}; 134};
74 135
75struct sdio_cccr { 136struct sdio_cccr {
@@ -113,12 +174,20 @@ struct mmc_card {
113#define MMC_STATE_READONLY (1<<1) /* card is read-only */ 174#define MMC_STATE_READONLY (1<<1) /* card is read-only */
114#define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */ 175#define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */
115#define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */ 176#define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */
177#define MMC_STATE_HIGHSPEED_DDR (1<<4) /* card is in high speed mode */
178#define MMC_STATE_ULTRAHIGHSPEED (1<<5) /* card is in ultra high speed mode */
179#define MMC_CARD_SDXC (1<<6) /* card is SDXC */
116 unsigned int quirks; /* card quirks */ 180 unsigned int quirks; /* card quirks */
117#define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */ 181#define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */
118#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */ 182#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */
119 /* for byte mode */ 183 /* for byte mode */
120#define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */ 184#define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */
121 /* (missing CIA registers) */ 185 /* (missing CIA registers) */
186#define MMC_QUIRK_BROKEN_CLK_GATING (1<<3) /* clock gating the sdio bus will make card fail */
187#define MMC_QUIRK_NONSTD_FUNC_IF (1<<4) /* SDIO card has nonstd function interfaces */
188#define MMC_QUIRK_DISABLE_CD (1<<5) /* disconnect CD/DAT[3] resistor */
189#define MMC_QUIRK_INAND_CMD38 (1<<6) /* iNAND devices have broken CMD38 */
190#define MMC_QUIRK_BLK_NO_CMD23 (1<<7) /* Avoid CMD23 for regular multiblock */
122 191
123 unsigned int erase_size; /* erase size in sectors */ 192 unsigned int erase_size; /* erase size in sectors */
124 unsigned int erase_shift; /* if erase unit is power 2 */ 193 unsigned int erase_shift; /* if erase unit is power 2 */
@@ -139,13 +208,101 @@ struct mmc_card {
139 struct sdio_cccr cccr; /* common card info */ 208 struct sdio_cccr cccr; /* common card info */
140 struct sdio_cis cis; /* common tuple info */ 209 struct sdio_cis cis; /* common tuple info */
141 struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */ 210 struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
211 struct sdio_func *sdio_single_irq; /* SDIO function when only one IRQ active */
142 unsigned num_info; /* number of info strings */ 212 unsigned num_info; /* number of info strings */
143 const char **info; /* info strings */ 213 const char **info; /* info strings */
144 struct sdio_func_tuple *tuples; /* unknown common tuples */ 214 struct sdio_func_tuple *tuples; /* unknown common tuples */
145 215
216 unsigned int sd_bus_speed; /* Bus Speed Mode set for the card */
217
146 struct dentry *debugfs_root; 218 struct dentry *debugfs_root;
147}; 219};
148 220
221/*
222 * The world is not perfect and supplies us with broken mmc/sdio devices.
223 * For at least some of these bugs we need a work-around.
224 */
225
226struct mmc_fixup {
227 /* CID-specific fields. */
228 const char *name;
229
230 /* Valid revision range */
231 u64 rev_start, rev_end;
232
233 unsigned int manfid;
234 unsigned short oemid;
235
236 /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */
237 u16 cis_vendor, cis_device;
238
239 void (*vendor_fixup)(struct mmc_card *card, int data);
240 int data;
241};
242
243#define CID_MANFID_ANY (-1u)
244#define CID_OEMID_ANY ((unsigned short) -1)
245#define CID_NAME_ANY (NULL)
246
247#define END_FIXUP { 0 }
248
249#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \
250 _cis_vendor, _cis_device, \
251 _fixup, _data) \
252 { \
253 .name = (_name), \
254 .manfid = (_manfid), \
255 .oemid = (_oemid), \
256 .rev_start = (_rev_start), \
257 .rev_end = (_rev_end), \
258 .cis_vendor = (_cis_vendor), \
259 .cis_device = (_cis_device), \
260 .vendor_fixup = (_fixup), \
261 .data = (_data), \
262 }
263
264#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \
265 _fixup, _data) \
266 _FIXUP_EXT(_name, _manfid, \
267 _oemid, _rev_start, _rev_end, \
268 SDIO_ANY_ID, SDIO_ANY_ID, \
269 _fixup, _data) \
270
271#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \
272 MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data)
273
274#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \
275 _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \
276 CID_OEMID_ANY, 0, -1ull, \
277 _vendor, _device, \
278 _fixup, _data) \
279
280#define cid_rev(hwrev, fwrev, year, month) \
281 (((u64) hwrev) << 40 | \
282 ((u64) fwrev) << 32 | \
283 ((u64) year) << 16 | \
284 ((u64) month))
285
286#define cid_rev_card(card) \
287 cid_rev(card->cid.hwrev, \
288 card->cid.fwrev, \
289 card->cid.year, \
290 card->cid.month)
291
292/*
293 * Unconditionally quirk add/remove.
294 */
295
296static inline void __maybe_unused add_quirk(struct mmc_card *card, int data)
297{
298 card->quirks |= data;
299}
300
301static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
302{
303 card->quirks &= ~data;
304}
305
149#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC) 306#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC)
150#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD) 307#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD)
151#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO) 308#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO)
@@ -154,11 +311,51 @@ struct mmc_card {
154#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY) 311#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY)
155#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED) 312#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED)
156#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR) 313#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR)
314#define mmc_card_ddr_mode(c) ((c)->state & MMC_STATE_HIGHSPEED_DDR)
315#define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED)
316#define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
157 317
158#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT) 318#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
159#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY) 319#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
160#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED) 320#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED)
161#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR) 321#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
322#define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
323#define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
324#define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
325
326/*
327 * Quirk add/remove for MMC products.
328 */
329
330static inline void __maybe_unused add_quirk_mmc(struct mmc_card *card, int data)
331{
332 if (mmc_card_mmc(card))
333 card->quirks |= data;
334}
335
336static inline void __maybe_unused remove_quirk_mmc(struct mmc_card *card,
337 int data)
338{
339 if (mmc_card_mmc(card))
340 card->quirks &= ~data;
341}
342
343/*
344 * Quirk add/remove for SD products.
345 */
346
347static inline void __maybe_unused add_quirk_sd(struct mmc_card *card, int data)
348{
349 if (mmc_card_sd(card))
350 card->quirks |= data;
351}
352
353static inline void __maybe_unused remove_quirk_sd(struct mmc_card *card,
354 int data)
355{
356 if (mmc_card_sd(card))
357 card->quirks &= ~data;
358}
162 359
163static inline int mmc_card_lenient_fn0(const struct mmc_card *c) 360static inline int mmc_card_lenient_fn0(const struct mmc_card *c)
164{ 361{
@@ -170,9 +367,21 @@ static inline int mmc_blksz_for_byte_mode(const struct mmc_card *c)
170 return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE; 367 return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
171} 368}
172 369
370static inline int mmc_card_disable_cd(const struct mmc_card *c)
371{
372 return c->quirks & MMC_QUIRK_DISABLE_CD;
373}
374
375static inline int mmc_card_nonstd_func_interface(const struct mmc_card *c)
376{
377 return c->quirks & MMC_QUIRK_NONSTD_FUNC_IF;
378}
379
173#define mmc_card_name(c) ((c)->cid.prod_name) 380#define mmc_card_name(c) ((c)->cid.prod_name)
174#define mmc_card_id(c) (dev_name(&(c)->dev)) 381#define mmc_card_id(c) (dev_name(&(c)->dev))
175 382
383#define mmc_dev_to_card(d) container_of(d, struct mmc_card, dev)
384
176#define mmc_list_to_card(l) container_of(l, struct mmc_card, node) 385#define mmc_list_to_card(l) container_of(l, struct mmc_card, node)
177#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev) 386#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev)
178#define mmc_set_drvdata(c,d) dev_set_drvdata(&(c)->dev, d) 387#define mmc_set_drvdata(c,d) dev_set_drvdata(&(c)->dev, d)
@@ -191,4 +400,7 @@ struct mmc_driver {
191extern int mmc_register_driver(struct mmc_driver *); 400extern int mmc_register_driver(struct mmc_driver *);
192extern void mmc_unregister_driver(struct mmc_driver *); 401extern void mmc_unregister_driver(struct mmc_driver *);
193 402
403extern void mmc_fixup_device(struct mmc_card *card,
404 const struct mmc_fixup *table);
405
194#endif 406#endif
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 7429033acb66..b6718e549a51 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -92,7 +92,7 @@ struct mmc_command {
92 * actively failing requests 92 * actively failing requests
93 */ 93 */
94 94
95 unsigned int erase_timeout; /* in milliseconds */ 95 unsigned int cmd_timeout_ms; /* in milliseconds */
96 96
97 struct mmc_data *data; /* data segment associated with cmd */ 97 struct mmc_data *data; /* data segment associated with cmd */
98 struct mmc_request *mrq; /* associated request */ 98 struct mmc_request *mrq; /* associated request */
@@ -120,6 +120,7 @@ struct mmc_data {
120}; 120};
121 121
122struct mmc_request { 122struct mmc_request {
123 struct mmc_command *sbc; /* SET_BLOCK_COUNT for multiblock */
123 struct mmc_command *cmd; 124 struct mmc_command *cmd;
124 struct mmc_data *data; 125 struct mmc_data *data;
125 struct mmc_command *stop; 126 struct mmc_command *stop;
@@ -133,8 +134,10 @@ struct mmc_card;
133 134
134extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *); 135extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
135extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int); 136extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
137extern int mmc_app_cmd(struct mmc_host *, struct mmc_card *);
136extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *, 138extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
137 struct mmc_command *, int); 139 struct mmc_command *, int);
140extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
138 141
139#define MMC_ERASE_ARG 0x00000000 142#define MMC_ERASE_ARG 0x00000000
140#define MMC_SECURE_ERASE_ARG 0x80000000 143#define MMC_SECURE_ERASE_ARG 0x80000000
@@ -153,11 +156,14 @@ extern int mmc_can_secure_erase_trim(struct mmc_card *card);
153extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from, 156extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from,
154 unsigned int nr); 157 unsigned int nr);
155 158
159extern int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen);
160
156extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *); 161extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *);
157extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int); 162extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
158 163
159extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort); 164extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
160extern void mmc_release_host(struct mmc_host *host); 165extern void mmc_release_host(struct mmc_host *host);
166extern void mmc_do_release_host(struct mmc_host *host);
161extern int mmc_try_claim_host(struct mmc_host *host); 167extern int mmc_try_claim_host(struct mmc_host *host);
162 168
163/** 169/**
diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
new file mode 100644
index 000000000000..bdd7ceeb99e4
--- /dev/null
+++ b/include/linux/mmc/dw_mmc.h
@@ -0,0 +1,222 @@
1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef _LINUX_MMC_DW_MMC_H_
15#define _LINUX_MMC_DW_MMC_H_
16
17#define MAX_MCI_SLOTS 2
18
19enum dw_mci_state {
20 STATE_IDLE = 0,
21 STATE_SENDING_CMD,
22 STATE_SENDING_DATA,
23 STATE_DATA_BUSY,
24 STATE_SENDING_STOP,
25 STATE_DATA_ERROR,
26};
27
28enum {
29 EVENT_CMD_COMPLETE = 0,
30 EVENT_XFER_COMPLETE,
31 EVENT_DATA_COMPLETE,
32 EVENT_DATA_ERROR,
33 EVENT_XFER_ERROR
34};
35
36struct mmc_data;
37
38/**
39 * struct dw_mci - MMC controller state shared between all slots
40 * @lock: Spinlock protecting the queue and associated data.
41 * @regs: Pointer to MMIO registers.
42 * @sg: Scatterlist entry currently being processed by PIO code, if any.
43 * @pio_offset: Offset into the current scatterlist entry.
44 * @cur_slot: The slot which is currently using the controller.
45 * @mrq: The request currently being processed on @cur_slot,
46 * or NULL if the controller is idle.
47 * @cmd: The command currently being sent to the card, or NULL.
48 * @data: The data currently being transferred, or NULL if no data
49 * transfer is in progress.
50 * @use_dma: Whether DMA channel is initialized or not.
51 * @sg_dma: Bus address of DMA buffer.
52 * @sg_cpu: Virtual address of DMA buffer.
53 * @dma_ops: Pointer to platform-specific DMA callbacks.
54 * @cmd_status: Snapshot of SR taken upon completion of the current
55 * command. Only valid when EVENT_CMD_COMPLETE is pending.
56 * @data_status: Snapshot of SR taken upon completion of the current
57 * data transfer. Only valid when EVENT_DATA_COMPLETE or
58 * EVENT_DATA_ERROR is pending.
59 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
60 * to be sent.
61 * @dir_status: Direction of current transfer.
62 * @tasklet: Tasklet running the request state machine.
63 * @card_tasklet: Tasklet handling card detect.
64 * @pending_events: Bitmask of events flagged by the interrupt handler
65 * to be processed by the tasklet.
66 * @completed_events: Bitmask of events which the state machine has
67 * processed.
68 * @state: Tasklet state.
69 * @queue: List of slots waiting for access to the controller.
70 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
71 * rate and timeout calculations.
72 * @current_speed: Configured rate of the controller.
73 * @num_slots: Number of slots available.
74 * @pdev: Platform device associated with the MMC controller.
75 * @pdata: Platform data associated with the MMC controller.
76 * @slot: Slots sharing this MMC controller.
77 * @data_shift: log2 of FIFO item size.
78 * @push_data: Pointer to FIFO push function.
79 * @pull_data: Pointer to FIFO pull function.
80 * @quirks: Set of quirks that apply to specific versions of the IP.
81 *
82 * Locking
83 * =======
84 *
85 * @lock is a softirq-safe spinlock protecting @queue as well as
86 * @cur_slot, @mrq and @state. These must always be updated
87 * at the same time while holding @lock.
88 *
89 * The @mrq field of struct dw_mci_slot is also protected by @lock,
90 * and must always be written at the same time as the slot is added to
91 * @queue.
92 *
93 * @pending_events and @completed_events are accessed using atomic bit
94 * operations, so they don't need any locking.
95 *
96 * None of the fields touched by the interrupt handler need any
97 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
98 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
99 * interrupts must be disabled and @data_status updated with a
100 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
101 * CMDRDY interrupt must be disabled and @cmd_status updated with a
102 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
103 * bytes_xfered field of @data must be written. This is ensured by
104 * using barriers.
105 */
106struct dw_mci {
107 spinlock_t lock;
108 void __iomem *regs;
109
110 struct scatterlist *sg;
111 unsigned int pio_offset;
112
113 struct dw_mci_slot *cur_slot;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_data *data;
117
118 /* DMA interface members*/
119 int use_dma;
120
121 dma_addr_t sg_dma;
122 void *sg_cpu;
123 struct dw_mci_dma_ops *dma_ops;
124#ifdef CONFIG_MMC_DW_IDMAC
125 unsigned int ring_size;
126#else
127 struct dw_mci_dma_data *dma_data;
128#endif
129 u32 cmd_status;
130 u32 data_status;
131 u32 stop_cmdr;
132 u32 dir_status;
133 struct tasklet_struct tasklet;
134 struct tasklet_struct card_tasklet;
135 unsigned long pending_events;
136 unsigned long completed_events;
137 enum dw_mci_state state;
138 struct list_head queue;
139
140 u32 bus_hz;
141 u32 current_speed;
142 u32 num_slots;
143 u32 fifoth_val;
144 struct platform_device *pdev;
145 struct dw_mci_board *pdata;
146 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
147
148 /* FIFO push and pull */
149 int data_shift;
150 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
151 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
152
153 /* Workaround flags */
154 u32 quirks;
155
156 struct regulator *vmmc; /* Power regulator */
157};
158
159/* DMA ops for Internal/External DMAC interface */
160struct dw_mci_dma_ops {
161 /* DMA Ops */
162 int (*init)(struct dw_mci *host);
163 void (*start)(struct dw_mci *host, unsigned int sg_len);
164 void (*complete)(struct dw_mci *host);
165 void (*stop)(struct dw_mci *host);
166 void (*cleanup)(struct dw_mci *host);
167 void (*exit)(struct dw_mci *host);
168};
169
170/* IP Quirks/flags. */
171/* DTO fix for command transmission with IDMAC configured */
172#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
173/* delay needed between retries on some 2.11a implementations */
174#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
175/* High Speed Capable - Supports HS cards (up to 50MHz) */
176#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
177/* Unreliable card detection */
178#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
179
180
181struct dma_pdata;
182
183struct block_settings {
184 unsigned short max_segs; /* see blk_queue_max_segments */
185 unsigned int max_blk_size; /* maximum size of one mmc block */
186 unsigned int max_blk_count; /* maximum number of blocks in one req*/
187 unsigned int max_req_size; /* maximum number of bytes in one req*/
188 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
189};
190
191/* Board platform data */
192struct dw_mci_board {
193 u32 num_slots;
194
195 u32 quirks; /* Workaround / Quirk flags */
196 unsigned int bus_hz; /* Bus speed */
197
198 unsigned int caps; /* Capabilities */
199
200 /* delay in mS before detecting cards after interrupt */
201 u32 detect_delay_ms;
202
203 int (*init)(u32 slot_id, irq_handler_t , void *);
204 int (*get_ro)(u32 slot_id);
205 int (*get_cd)(u32 slot_id);
206 int (*get_ocr)(u32 slot_id);
207 int (*get_bus_wd)(u32 slot_id);
208 /*
209 * Enable power to selected slot and set voltage to desired level.
210 * Voltage levels are specified using MMC_VDD_xxx defines defined
211 * in linux/mmc/host.h file.
212 */
213 void (*setpower)(u32 slot_id, u32 volt);
214 void (*exit)(u32 slot_id);
215 void (*select_slot)(u32 slot_id);
216
217 struct dw_mci_dma_ops *dma_ops;
218 struct dma_pdata *data;
219 struct block_settings *blk_settings;
220};
221
222#endif /* _LINUX_MMC_DW_MMC_H_ */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 1575b52c3bfa..1ee4424462eb 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -50,6 +50,30 @@ struct mmc_ios {
50#define MMC_TIMING_LEGACY 0 50#define MMC_TIMING_LEGACY 0
51#define MMC_TIMING_MMC_HS 1 51#define MMC_TIMING_MMC_HS 1
52#define MMC_TIMING_SD_HS 2 52#define MMC_TIMING_SD_HS 2
53#define MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY
54#define MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS
55#define MMC_TIMING_UHS_SDR50 3
56#define MMC_TIMING_UHS_SDR104 4
57#define MMC_TIMING_UHS_DDR50 5
58
59 unsigned char ddr; /* dual data rate used */
60
61#define MMC_SDR_MODE 0
62#define MMC_1_2V_DDR_MODE 1
63#define MMC_1_8V_DDR_MODE 2
64
65 unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
66
67#define MMC_SIGNAL_VOLTAGE_330 0
68#define MMC_SIGNAL_VOLTAGE_180 1
69#define MMC_SIGNAL_VOLTAGE_120 2
70
71 unsigned char drv_type; /* driver type (A, B, C, D) */
72
73#define MMC_SET_DRIVER_TYPE_B 0
74#define MMC_SET_DRIVER_TYPE_A 1
75#define MMC_SET_DRIVER_TYPE_C 2
76#define MMC_SET_DRIVER_TYPE_D 3
53}; 77};
54 78
55struct mmc_host_ops { 79struct mmc_host_ops {
@@ -111,6 +135,10 @@ struct mmc_host_ops {
111 135
112 /* optional callback for HC quirks */ 136 /* optional callback for HC quirks */
113 void (*init_card)(struct mmc_host *host, struct mmc_card *card); 137 void (*init_card)(struct mmc_host *host, struct mmc_card *card);
138
139 int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
140 int (*execute_tuning)(struct mmc_host *host);
141 void (*enable_preset_value)(struct mmc_host *host, bool enable);
114}; 142};
115 143
116struct mmc_card; 144struct mmc_card;
@@ -123,7 +151,11 @@ struct mmc_host {
123 const struct mmc_host_ops *ops; 151 const struct mmc_host_ops *ops;
124 unsigned int f_min; 152 unsigned int f_min;
125 unsigned int f_max; 153 unsigned int f_max;
154 unsigned int f_init;
126 u32 ocr_avail; 155 u32 ocr_avail;
156 u32 ocr_avail_sdio; /* SDIO-specific OCR */
157 u32 ocr_avail_sd; /* SD-specific OCR */
158 u32 ocr_avail_mmc; /* MMC-specific OCR */
127 struct notifier_block pm_notify; 159 struct notifier_block pm_notify;
128 160
129#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ 161#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
@@ -157,13 +189,44 @@ struct mmc_host {
157#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */ 189#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
158#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */ 190#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
159#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */ 191#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
192#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
193 /* DDR mode at 1.8V */
194#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
195 /* DDR mode at 1.2V */
196#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
197#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
198#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
199#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
200#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
201#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
202#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
203#define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
204#define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
205#define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
206#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
207#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
208#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
209#define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */
210#define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */
211#define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */
212#define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */
213#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
160 214
161 mmc_pm_flag_t pm_caps; /* supported pm features */ 215 mmc_pm_flag_t pm_caps; /* supported pm features */
162 216
217#ifdef CONFIG_MMC_CLKGATE
218 int clk_requests; /* internal reference counter */
219 unsigned int clk_delay; /* number of MCI clk hold cycles */
220 bool clk_gated; /* clock gated */
221 struct work_struct clk_gate_work; /* delayed clock gate */
222 unsigned int clk_old; /* old clock value cache */
223 spinlock_t clk_lock; /* lock for clk fields */
224 struct mutex clk_gate_mutex; /* mutex for clock gating */
225#endif
226
163 /* host specific block data */ 227 /* host specific block data */
164 unsigned int max_seg_size; /* see blk_queue_max_segment_size */ 228 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
165 unsigned short max_hw_segs; /* see blk_queue_max_hw_segments */ 229 unsigned short max_segs; /* see blk_queue_max_segments */
166 unsigned short max_phys_segs; /* see blk_queue_max_phys_segments */
167 unsigned short unused; 230 unsigned short unused;
168 unsigned int max_req_size; /* maximum number of bytes in one req */ 231 unsigned int max_req_size; /* maximum number of bytes in one req */
169 unsigned int max_blk_size; /* maximum size of one mmc block */ 232 unsigned int max_blk_size; /* maximum size of one mmc block */
@@ -212,6 +275,10 @@ struct mmc_host {
212 struct led_trigger *led; /* activity led */ 275 struct led_trigger *led; /* activity led */
213#endif 276#endif
214 277
278#ifdef CONFIG_REGULATOR
279 bool regulator_enabled; /* regulator state */
280#endif
281
215 struct dentry *debugfs_root; 282 struct dentry *debugfs_root;
216 283
217 unsigned long private[0] ____cacheline_aligned; 284 unsigned long private[0] ____cacheline_aligned;
@@ -236,8 +303,8 @@ static inline void *mmc_priv(struct mmc_host *host)
236extern int mmc_suspend_host(struct mmc_host *); 303extern int mmc_suspend_host(struct mmc_host *);
237extern int mmc_resume_host(struct mmc_host *); 304extern int mmc_resume_host(struct mmc_host *);
238 305
239extern void mmc_power_save_host(struct mmc_host *host); 306extern int mmc_power_save_host(struct mmc_host *host);
240extern void mmc_power_restore_host(struct mmc_host *host); 307extern int mmc_power_restore_host(struct mmc_host *host);
241 308
242extern void mmc_detect_change(struct mmc_host *, unsigned long delay); 309extern void mmc_detect_change(struct mmc_host *, unsigned long delay);
243extern void mmc_request_done(struct mmc_host *, struct mmc_request *); 310extern void mmc_request_done(struct mmc_host *, struct mmc_request *);
@@ -250,8 +317,24 @@ static inline void mmc_signal_sdio_irq(struct mmc_host *host)
250 317
251struct regulator; 318struct regulator;
252 319
320#ifdef CONFIG_REGULATOR
253int mmc_regulator_get_ocrmask(struct regulator *supply); 321int mmc_regulator_get_ocrmask(struct regulator *supply);
254int mmc_regulator_set_ocr(struct regulator *supply, unsigned short vdd_bit); 322int mmc_regulator_set_ocr(struct mmc_host *mmc,
323 struct regulator *supply,
324 unsigned short vdd_bit);
325#else
326static inline int mmc_regulator_get_ocrmask(struct regulator *supply)
327{
328 return 0;
329}
330
331static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
332 struct regulator *supply,
333 unsigned short vdd_bit)
334{
335 return 0;
336}
337#endif
255 338
256int mmc_card_awake(struct mmc_host *host); 339int mmc_card_awake(struct mmc_host *host);
257int mmc_card_sleep(struct mmc_host *host); 340int mmc_card_sleep(struct mmc_host *host);
@@ -268,5 +351,27 @@ static inline void mmc_set_disable_delay(struct mmc_host *host,
268 host->disable_delay = disable_delay; 351 host->disable_delay = disable_delay;
269} 352}
270 353
354/* Module parameter */
355extern int mmc_assume_removable;
356
357static inline int mmc_card_is_removable(struct mmc_host *host)
358{
359 return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable;
360}
361
362static inline int mmc_card_keep_power(struct mmc_host *host)
363{
364 return host->pm_flags & MMC_PM_KEEP_POWER;
365}
366
367static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
368{
369 return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
370}
371
372static inline int mmc_host_cmd23(struct mmc_host *host)
373{
374 return host->caps & MMC_CAP_CMD23;
375}
271#endif 376#endif
272 377
diff --git a/include/linux/mmc/ioctl.h b/include/linux/mmc/ioctl.h
new file mode 100644
index 000000000000..5baf2983a12f
--- /dev/null
+++ b/include/linux/mmc/ioctl.h
@@ -0,0 +1,54 @@
1#ifndef LINUX_MMC_IOCTL_H
2#define LINUX_MMC_IOCTL_H
3struct mmc_ioc_cmd {
4 /* Implies direction of data. true = write, false = read */
5 int write_flag;
6
7 /* Application-specific command. true = precede with CMD55 */
8 int is_acmd;
9
10 __u32 opcode;
11 __u32 arg;
12 __u32 response[4]; /* CMD response */
13 unsigned int flags;
14 unsigned int blksz;
15 unsigned int blocks;
16
17 /*
18 * Sleep at least postsleep_min_us useconds, and at most
19 * postsleep_max_us useconds *after* issuing command. Needed for
20 * some read commands for which cards have no other way of indicating
21 * they're ready for the next command (i.e. there is no equivalent of
22 * a "busy" indicator for read operations).
23 */
24 unsigned int postsleep_min_us;
25 unsigned int postsleep_max_us;
26
27 /*
28 * Override driver-computed timeouts. Note the difference in units!
29 */
30 unsigned int data_timeout_ns;
31 unsigned int cmd_timeout_ms;
32
33 /*
34 * For 64-bit machines, the next member, ``__u64 data_ptr``, wants to
35 * be 8-byte aligned. Make sure this struct is the same size when
36 * built for 32-bit.
37 */
38 __u32 __pad;
39
40 /* DAT buffer */
41 __u64 data_ptr;
42};
43#define mmc_ioc_cmd_set_data(ic, ptr) ic.data_ptr = (__u64)(unsigned long) ptr
44
45#define MMC_IOC_CMD _IOWR(MMC_BLOCK_MAJOR, 0, struct mmc_ioc_cmd)
46
47/*
48 * Since this ioctl is only meant to enhance (and not replace) normal access
49 * to the mmc bus device, an upper data transfer limit of MMC_IOC_MAX_BYTES
50 * is enforced per ioctl call. For larger data transfers, use the normal
51 * block device operations.
52 */
53#define MMC_IOC_MAX_BYTES (512L * 256)
54#endif /* LINUX_MMC_IOCTL_H */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index dd11ae51fb68..ac26a685cca8 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -40,7 +40,9 @@
40#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ 40#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
41#define MMC_STOP_TRANSMISSION 12 /* ac R1b */ 41#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
42#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ 42#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
43#define MMC_BUS_TEST_R 14 /* adtc R1 */
43#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ 44#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
45#define MMC_BUS_TEST_W 19 /* adtc R1 */
44#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ 46#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
45#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ 47#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
46 48
@@ -48,6 +50,7 @@
48#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ 50#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
49#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ 51#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
50#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ 52#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
53#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
51 54
52 /* class 3 */ 55 /* class 3 */
53#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ 56#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
@@ -80,6 +83,12 @@
80#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ 83#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
81#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ 84#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
82 85
86static inline bool mmc_op_multi(u32 opcode)
87{
88 return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
89 opcode == MMC_READ_MULTIPLE_BLOCK;
90}
91
83/* 92/*
84 * MMC_SWITCH argument format: 93 * MMC_SWITCH argument format:
85 * 94 *
@@ -251,17 +260,25 @@ struct _mmc_csd {
251 * EXT_CSD fields 260 * EXT_CSD fields
252 */ 261 */
253 262
263#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
264#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
265#define EXT_CSD_WR_REL_PARAM 166 /* RO */
254#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 266#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
267#define EXT_CSD_PART_CONFIG 179 /* R/W */
255#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ 268#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
256#define EXT_CSD_BUS_WIDTH 183 /* R/W */ 269#define EXT_CSD_BUS_WIDTH 183 /* R/W */
257#define EXT_CSD_HS_TIMING 185 /* R/W */ 270#define EXT_CSD_HS_TIMING 185 /* R/W */
258#define EXT_CSD_REV 192 /* RO */ 271#define EXT_CSD_REV 192 /* RO */
259#define EXT_CSD_STRUCTURE 194 /* RO */ 272#define EXT_CSD_STRUCTURE 194 /* RO */
260#define EXT_CSD_CARD_TYPE 196 /* RO */ 273#define EXT_CSD_CARD_TYPE 196 /* RO */
274#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
261#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 275#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
262#define EXT_CSD_S_A_TIMEOUT 217 /* RO */ 276#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
277#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
278#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
263#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ 279#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
264#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 280#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
281#define EXT_CSD_BOOT_MULT 226 /* RO */
265#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ 282#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
266#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ 283#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
267#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ 284#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
@@ -271,17 +288,31 @@ struct _mmc_csd {
271 * EXT_CSD field definitions 288 * EXT_CSD field definitions
272 */ 289 */
273 290
291#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
292
293#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
294#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
295#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2)
296
274#define EXT_CSD_CMD_SET_NORMAL (1<<0) 297#define EXT_CSD_CMD_SET_NORMAL (1<<0)
275#define EXT_CSD_CMD_SET_SECURE (1<<1) 298#define EXT_CSD_CMD_SET_SECURE (1<<1)
276#define EXT_CSD_CMD_SET_CPSECURE (1<<2) 299#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
277 300
278#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ 301#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
279#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ 302#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
280#define EXT_CSD_CARD_TYPE_MASK 0x3 /* Mask out reserved and DDR bits */ 303#define EXT_CSD_CARD_TYPE_MASK 0xF /* Mask out reserved bits */
304#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
305 /* DDR mode @1.8V or 3V I/O */
306#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
307 /* DDR mode @1.2V I/O */
308#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
309 | EXT_CSD_CARD_TYPE_DDR_1_2V)
281 310
282#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 311#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
283#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 312#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
284#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 313#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
314#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
315#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
285 316
286#define EXT_CSD_SEC_ER_EN BIT(0) 317#define EXT_CSD_SEC_ER_EN BIT(0)
287#define EXT_CSD_SEC_BD_BLK_EN BIT(2) 318#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h
index 3fd85e088cc3..7d35d52c3df3 100644
--- a/include/linux/mmc/sd.h
+++ b/include/linux/mmc/sd.h
@@ -17,6 +17,7 @@
17/* This is basically the same command as for MMC with some quirks. */ 17/* This is basically the same command as for MMC with some quirks. */
18#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ 18#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
19#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ 19#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
20#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
20 21
21 /* class 10 */ 22 /* class 10 */
22#define SD_SWITCH 6 /* adtc [31:0] See below R1 */ 23#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
@@ -32,6 +33,12 @@
32#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ 33#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
33#define SD_APP_SEND_SCR 51 /* adtc R1 */ 34#define SD_APP_SEND_SCR 51 /* adtc R1 */
34 35
36/* OCR bit definitions */
37#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
38#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
39#define SD_OCR_XPC (1 << 28) /* SDXC power control */
40#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
41
35/* 42/*
36 * SD_SWITCH argument format: 43 * SD_SWITCH argument format:
37 * 44 *
@@ -59,7 +66,7 @@
59 66
60#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ 67#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
61#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ 68#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
62#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */ 69#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
63 70
64/* 71/*
65 * SD bus widths 72 * SD bus widths
diff --git a/include/linux/mmc/sdhci-pltfm.h b/include/linux/mmc/sdhci-pltfm.h
new file mode 100644
index 000000000000..548d59d404cb
--- /dev/null
+++ b/include/linux/mmc/sdhci-pltfm.h
@@ -0,0 +1,35 @@
1/*
2 * Platform data declarations for the sdhci-pltfm driver.
3 *
4 * Copyright (c) 2010 MontaVista Software, LLC.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
12 */
13
14#ifndef _SDHCI_PLTFM_H
15#define _SDHCI_PLTFM_H
16
17struct sdhci_ops;
18struct sdhci_host;
19
20/**
21 * struct sdhci_pltfm_data - SDHCI platform-specific information & hooks
22 * @ops: optional pointer to the platform-provided SDHCI ops
23 * @quirks: optional SDHCI quirks
24 * @init: optional hook that is called during device probe, before the
25 * driver tries to access any SDHCI registers
26 * @exit: optional hook that is called during device removal
27 */
28struct sdhci_pltfm_data {
29 struct sdhci_ops *ops;
30 unsigned int quirks;
31 int (*init)(struct sdhci_host *host, struct sdhci_pltfm_data *pdata);
32 void (*exit)(struct sdhci_host *host);
33};
34
35#endif /* _SDHCI_PLTFM_H */
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
new file mode 100644
index 000000000000..6a68c4eb4e44
--- /dev/null
+++ b/include/linux/mmc/sdhci.h
@@ -0,0 +1,165 @@
1/*
2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11#ifndef __SDHCI_H
12#define __SDHCI_H
13
14#include <linux/scatterlist.h>
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19
20struct sdhci_host {
21 /* Data set by hardware interface driver */
22 const char *hw_name; /* Hardware bus name */
23
24 unsigned int quirks; /* Deviations from spec. */
25
26/* Controller doesn't honor resets unless we touch the clock register */
27#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
28/* Controller has bad caps bits, but really supports DMA */
29#define SDHCI_QUIRK_FORCE_DMA (1<<1)
30/* Controller doesn't like to be reset when there is no card inserted. */
31#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
32/* Controller doesn't like clearing the power reg before a change */
33#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
34/* Controller has flaky internal state so reset it on each ios change */
35#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
36/* Controller has an unusable DMA engine */
37#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
38/* Controller has an unusable ADMA engine */
39#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
40/* Controller can only DMA from 32-bit aligned addresses */
41#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
42/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
43#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
44/* Controller can only ADMA chunks that are a multiple of 32 bits */
45#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
46/* Controller needs to be reset after each request to stay stable */
47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
48/* Controller needs voltage and power writes to happen separately */
49#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
50/* Controller provides an incorrect timeout value for transfers */
51#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
52/* Controller has an issue with buffer bits for small transfers */
53#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
54/* Controller does not provide transfer-complete interrupt when not busy */
55#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
56/* Controller has unreliable card detection */
57#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
58/* Controller reports inverted write-protect state */
59#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
60/* Controller has nonstandard clock management */
61#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
62/* Controller does not like fast PIO transfers */
63#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
64/* Controller losing signal/interrupt enable states after reset */
65#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
66/* Controller has to be forced to use block size of 2048 bytes */
67#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
68/* Controller cannot do multi-block transfers */
69#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
70/* Controller can only handle 1-bit data transfers */
71#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
72/* Controller needs 10ms delay between applying power and clock */
73#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
74/* Controller uses SDCLK instead of TMCLK for data timeouts */
75#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
76/* Controller reports wrong base clock capability */
77#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
78/* Controller cannot support End Attribute in NOP ADMA descriptor */
79#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
80/* Controller is missing device caps. Use caps provided by host */
81#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
82/* Controller uses Auto CMD12 command to stop the transfer */
83#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
84/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
85#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
86/* Controller treats ADMA descriptors with length 0000h incorrectly */
87#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
88/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
89#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
90
91 int irq; /* Device IRQ */
92 void __iomem *ioaddr; /* Mapped address */
93
94 const struct sdhci_ops *ops; /* Low level hw interface */
95
96 struct regulator *vmmc; /* Power regulator */
97
98 /* Internal data */
99 struct mmc_host *mmc; /* MMC structure */
100 u64 dma_mask; /* custom DMA mask */
101
102#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
103 struct led_classdev led; /* LED control */
104 char led_name[32];
105#endif
106
107 spinlock_t lock; /* Mutex */
108
109 int flags; /* Host attributes */
110#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
111#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
112#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
113#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
114#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
115#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
116#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
117#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
118
119 unsigned int version; /* SDHCI spec. version */
120
121 unsigned int max_clk; /* Max possible freq (MHz) */
122 unsigned int timeout_clk; /* Timeout freq (KHz) */
123 unsigned int clk_mul; /* Clock Muliplier value */
124
125 unsigned int clock; /* Current clock (MHz) */
126 u8 pwr; /* Current voltage */
127
128 struct mmc_request *mrq; /* Current request */
129 struct mmc_command *cmd; /* Current command */
130 struct mmc_data *data; /* Current data request */
131 unsigned int data_early:1; /* Data finished before cmd */
132
133 struct sg_mapping_iter sg_miter; /* SG state for PIO */
134 unsigned int blocks; /* remaining PIO blocks */
135
136 int sg_count; /* Mapped sg entries */
137
138 u8 *adma_desc; /* ADMA descriptor table */
139 u8 *align_buffer; /* Bounce buffer */
140
141 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
142 dma_addr_t align_addr; /* Mapped bounce buffer */
143
144 struct tasklet_struct card_tasklet; /* Tasklet structures */
145 struct tasklet_struct finish_tasklet;
146
147 struct timer_list timer; /* Timer for timeouts */
148
149 unsigned int caps; /* Alternative capabilities */
150
151 unsigned int ocr_avail_sdio; /* OCR bit masks */
152 unsigned int ocr_avail_sd;
153 unsigned int ocr_avail_mmc;
154
155 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
156 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
157
158 unsigned int tuning_count; /* Timer count for re-tuning */
159 unsigned int tuning_mode; /* Re-tuning mode supported by host */
160#define SDHCI_TUNING_MODE_1 0
161 struct timer_list tuning_timer; /* Timer for tuning */
162
163 unsigned long private[0] ____cacheline_aligned;
164};
165#endif /* __SDHCI_H */
diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h
index 33b2ea09a4ad..a36ab3bc7b03 100644
--- a/include/linux/mmc/sdio_ids.h
+++ b/include/linux/mmc/sdio_ids.h
@@ -18,6 +18,7 @@
18#define SDIO_CLASS_PHS 0x06 /* PHS standard interface */ 18#define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
19#define SDIO_CLASS_WLAN 0x07 /* WLAN interface */ 19#define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
20#define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */ 20#define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
21#define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
21 22
22/* 23/*
23 * Vendors and devices. Sort key: vendor first, device next. 24 * Vendors and devices. Sort key: vendor first, device next.
diff --git a/include/linux/mmc/sh_mmcif.h b/include/linux/mmc/sh_mmcif.h
index d4a2ebbdab4b..9eb9b4b96f55 100644
--- a/include/linux/mmc/sh_mmcif.h
+++ b/include/linux/mmc/sh_mmcif.h
@@ -14,8 +14,9 @@
14#ifndef __SH_MMCIF_H__ 14#ifndef __SH_MMCIF_H__
15#define __SH_MMCIF_H__ 15#define __SH_MMCIF_H__
16 16
17#include <linux/platform_device.h>
18#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/platform_device.h>
19#include <linux/sh_dma.h>
19 20
20/* 21/*
21 * MMCIF : CE_CLK_CTRL [19:16] 22 * MMCIF : CE_CLK_CTRL [19:16]
@@ -31,12 +32,19 @@
31 * 1111 : Peripheral clock (sup_pclk set '1') 32 * 1111 : Peripheral clock (sup_pclk set '1')
32 */ 33 */
33 34
35struct sh_mmcif_dma {
36 struct sh_dmae_slave chan_priv_tx;
37 struct sh_dmae_slave chan_priv_rx;
38};
39
34struct sh_mmcif_plat_data { 40struct sh_mmcif_plat_data {
35 void (*set_pwr)(struct platform_device *pdev, int state); 41 void (*set_pwr)(struct platform_device *pdev, int state);
36 void (*down_pwr)(struct platform_device *pdev); 42 void (*down_pwr)(struct platform_device *pdev);
37 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */ 43 int (*get_cd)(struct platform_device *pdef);
38 unsigned long caps; 44 struct sh_mmcif_dma *dma;
39 u32 ocr; 45 u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
46 unsigned long caps;
47 u32 ocr;
40}; 48};
41 49
42#define MMCIF_CE_CMD_SET 0x00000000 50#define MMCIF_CE_CMD_SET 0x00000000
@@ -58,19 +66,45 @@ struct sh_mmcif_plat_data {
58#define MMCIF_CE_HOST_STS2 0x0000004C 66#define MMCIF_CE_HOST_STS2 0x0000004C
59#define MMCIF_CE_VERSION 0x0000007C 67#define MMCIF_CE_VERSION 0x0000007C
60 68
61extern inline u32 sh_mmcif_readl(void __iomem *addr, int reg) 69/* CE_BUF_ACC */
70#define BUF_ACC_DMAWEN (1 << 25)
71#define BUF_ACC_DMAREN (1 << 24)
72#define BUF_ACC_BUSW_32 (0 << 17)
73#define BUF_ACC_BUSW_16 (1 << 17)
74#define BUF_ACC_ATYP (1 << 16)
75
76/* CE_CLK_CTRL */
77#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
78#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
79#define CLK_SUP_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
80#define CLKDIV_4 (1<<16) /* mmc clock frequency.
81 * n: bus clock/(2^(n+1)) */
82#define CLKDIV_256 (7<<16) /* mmc clock frequency. (see above) */
83#define SRSPTO_256 ((1 << 13) | (0 << 12)) /* resp timeout */
84#define SRBSYTO_29 ((1 << 11) | (1 << 10) | \
85 (1 << 9) | (1 << 8)) /* resp busy timeout */
86#define SRWDTO_29 ((1 << 7) | (1 << 6) | \
87 (1 << 5) | (1 << 4)) /* read/write timeout */
88#define SCCSTO_29 ((1 << 3) | (1 << 2) | \
89 (1 << 1) | (1 << 0)) /* ccs timeout */
90
91/* CE_VERSION */
92#define SOFT_RST_ON (1 << 31)
93#define SOFT_RST_OFF 0
94
95static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
62{ 96{
63 return readl(addr + reg); 97 return __raw_readl(addr + reg);
64} 98}
65 99
66extern inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val) 100static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
67{ 101{
68 writel(val, addr + reg); 102 __raw_writel(val, addr + reg);
69} 103}
70 104
71#define SH_MMCIF_BBS 512 /* boot block size */ 105#define SH_MMCIF_BBS 512 /* boot block size */
72 106
73extern inline void sh_mmcif_boot_cmd_send(void __iomem *base, 107static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
74 unsigned long cmd, unsigned long arg) 108 unsigned long cmd, unsigned long arg)
75{ 109{
76 sh_mmcif_writel(base, MMCIF_CE_INT, 0); 110 sh_mmcif_writel(base, MMCIF_CE_INT, 0);
@@ -78,7 +112,7 @@ extern inline void sh_mmcif_boot_cmd_send(void __iomem *base,
78 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); 112 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
79} 113}
80 114
81extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask) 115static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
82{ 116{
83 unsigned long tmp; 117 unsigned long tmp;
84 int cnt; 118 int cnt;
@@ -94,14 +128,14 @@ extern inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
94 return -1; 128 return -1;
95} 129}
96 130
97extern inline int sh_mmcif_boot_cmd(void __iomem *base, 131static inline int sh_mmcif_boot_cmd(void __iomem *base,
98 unsigned long cmd, unsigned long arg) 132 unsigned long cmd, unsigned long arg)
99{ 133{
100 sh_mmcif_boot_cmd_send(base, cmd, arg); 134 sh_mmcif_boot_cmd_send(base, cmd, arg);
101 return sh_mmcif_boot_cmd_poll(base, 0x00010000); 135 return sh_mmcif_boot_cmd_poll(base, 0x00010000);
102} 136}
103 137
104extern inline int sh_mmcif_boot_do_read_single(void __iomem *base, 138static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
105 unsigned int block_nr, 139 unsigned int block_nr,
106 unsigned long *buf) 140 unsigned long *buf)
107{ 141{
@@ -124,7 +158,7 @@ extern inline int sh_mmcif_boot_do_read_single(void __iomem *base,
124 return 0; 158 return 0;
125} 159}
126 160
127extern inline int sh_mmcif_boot_do_read(void __iomem *base, 161static inline int sh_mmcif_boot_do_read(void __iomem *base,
128 unsigned long first_block, 162 unsigned long first_block,
129 unsigned long nr_blocks, 163 unsigned long nr_blocks,
130 void *buf) 164 void *buf)
@@ -132,6 +166,17 @@ extern inline int sh_mmcif_boot_do_read(void __iomem *base,
132 unsigned long k; 166 unsigned long k;
133 int ret = 0; 167 int ret = 0;
134 168
169 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
170 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
171 CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
172 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
173
174 /* CMD9 - Get CSD */
175 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
176
177 /* CMD7 - Select the card */
178 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
179
135 /* CMD16 - Set the block size */ 180 /* CMD16 - Set the block size */
136 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS); 181 sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
137 182
@@ -142,23 +187,22 @@ extern inline int sh_mmcif_boot_do_read(void __iomem *base,
142 return ret; 187 return ret;
143} 188}
144 189
145extern inline void sh_mmcif_boot_init(void __iomem *base) 190static inline void sh_mmcif_boot_init(void __iomem *base)
146{ 191{
147 unsigned long tmp;
148
149 /* reset */ 192 /* reset */
150 tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION); 193 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
151 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000); 194 sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
152 sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);
153 195
154 /* byte swap */ 196 /* byte swap */
155 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000); 197 sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
156 198
157 /* Set block size in MMCIF hardware */ 199 /* Set block size in MMCIF hardware */
158 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS); 200 sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
159 201
160 /* Enable the clock, set it to Bus clock/256 (about 325Khz)*/ 202 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
161 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff); 203 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
204 CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
205 SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
162 206
163 /* CMD0 */ 207 /* CMD0 */
164 sh_mmcif_boot_cmd(base, 0x00000040, 0); 208 sh_mmcif_boot_cmd(base, 0x00000040, 0);
@@ -176,25 +220,4 @@ extern inline void sh_mmcif_boot_init(void __iomem *base)
176 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000); 220 sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
177} 221}
178 222
179extern inline void sh_mmcif_boot_slurp(void __iomem *base,
180 unsigned char *buf,
181 unsigned long no_bytes)
182{
183 unsigned long tmp;
184
185 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
186 sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01012fff);
187
188 /* CMD9 - Get CSD */
189 sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
190
191 /* CMD7 - Select the card */
192 sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
193
194 tmp = no_bytes / SH_MMCIF_BBS;
195 tmp += (no_bytes % SH_MMCIF_BBS) ? 1 : 0;
196
197 sh_mmcif_boot_do_read(base, 512, tmp, buf);
198}
199
200#endif /* __SH_MMCIF_H__ */ 223#endif /* __SH_MMCIF_H__ */
diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
new file mode 100644
index 000000000000..faf32b6ec185
--- /dev/null
+++ b/include/linux/mmc/sh_mobile_sdhi.h
@@ -0,0 +1,20 @@
1#ifndef __SH_MOBILE_SDHI_H__
2#define __SH_MOBILE_SDHI_H__
3
4#include <linux/types.h>
5
6struct platform_device;
7struct tmio_mmc_data;
8
9struct sh_mobile_sdhi_info {
10 int dma_slave_tx;
11 int dma_slave_rx;
12 unsigned long tmio_flags;
13 unsigned long tmio_caps;
14 u32 tmio_ocr_mask; /* available MMC voltages */
15 struct tmio_mmc_data *pdata;
16 void (*set_pwr)(struct platform_device *pdev, int state);
17 int (*get_cd)(struct platform_device *pdev);
18};
19
20#endif /* __SH_MOBILE_SDHI_H__ */
diff --git a/include/linux/mmc/tmio.h b/include/linux/mmc/tmio.h
new file mode 100644
index 000000000000..19490b942db0
--- /dev/null
+++ b/include/linux/mmc/tmio.h
@@ -0,0 +1,63 @@
1/*
2 * include/linux/mmc/tmio.h
3 *
4 * Copyright (C) 2007 Ian Molton
5 * Copyright (C) 2004 Ian Molton
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Driver for the MMC / SD / SDIO cell found in:
12 *
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
14 */
15#ifndef _LINUX_MMC_TMIO_H_
16#define _LINUX_MMC_TMIO_H_
17
18#define CTL_SD_CMD 0x00
19#define CTL_ARG_REG 0x04
20#define CTL_STOP_INTERNAL_ACTION 0x08
21#define CTL_XFER_BLK_COUNT 0xa
22#define CTL_RESPONSE 0x0c
23#define CTL_STATUS 0x1c
24#define CTL_IRQ_MASK 0x20
25#define CTL_SD_CARD_CLK_CTL 0x24
26#define CTL_SD_XFER_LEN 0x26
27#define CTL_SD_MEM_CARD_OPT 0x28
28#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
29#define CTL_SD_DATA_PORT 0x30
30#define CTL_TRANSACTION_CTL 0x34
31#define CTL_SDIO_STATUS 0x36
32#define CTL_SDIO_IRQ_MASK 0x38
33#define CTL_RESET_SD 0xe0
34#define CTL_SDIO_REGS 0x100
35#define CTL_CLK_AND_WAIT_CTL 0x138
36#define CTL_RESET_SDIO 0x1e0
37
38/* Definitions for values the CTRL_STATUS register can take. */
39#define TMIO_STAT_CMDRESPEND 0x00000001
40#define TMIO_STAT_DATAEND 0x00000004
41#define TMIO_STAT_CARD_REMOVE 0x00000008
42#define TMIO_STAT_CARD_INSERT 0x00000010
43#define TMIO_STAT_SIGSTATE 0x00000020
44#define TMIO_STAT_WRPROTECT 0x00000080
45#define TMIO_STAT_CARD_REMOVE_A 0x00000100
46#define TMIO_STAT_CARD_INSERT_A 0x00000200
47#define TMIO_STAT_SIGSTATE_A 0x00000400
48#define TMIO_STAT_CMD_IDX_ERR 0x00010000
49#define TMIO_STAT_CRCFAIL 0x00020000
50#define TMIO_STAT_STOPBIT_ERR 0x00040000
51#define TMIO_STAT_DATATIMEOUT 0x00080000
52#define TMIO_STAT_RXOVERFLOW 0x00100000
53#define TMIO_STAT_TXUNDERRUN 0x00200000
54#define TMIO_STAT_CMDTIMEOUT 0x00400000
55#define TMIO_STAT_RXRDY 0x01000000
56#define TMIO_STAT_TXRQ 0x02000000
57#define TMIO_STAT_ILL_FUNC 0x20000000
58#define TMIO_STAT_CMD_BUSY 0x40000000
59#define TMIO_STAT_ILL_ACCESS 0x80000000
60
61#define TMIO_BBS 512 /* Boot block size */
62
63#endif /* _LINUX_MMC_TMIO_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 07:47:38 -0500