4 files changed, 244 insertions, 0 deletions

diff --git a/include/linux/mmc/dw_mmc.h b/include/linux/mmc/dw_mmc.h
new file mode 100644
index 000000000000..16b0261763ed
--- /dev/null
+++ b/include/linux/mmc/dw_mmc.h
@@ -0,0 +1,217 @@
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ *  (Based on NXP driver for lpc 31xx)
+ *
+ * Copyright (C) 2009 NXP Semiconductors
+ * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MMC_DW_MMC_H_
+#define _LINUX_MMC_DW_MMC_H_
+
+#define MAX_MCI_SLOTS   2
+
+enum dw_mci_state {
+        STATE_IDLE = 0,
+        STATE_SENDING_CMD,
+        STATE_SENDING_DATA,
+        STATE_DATA_BUSY,
+        STATE_SENDING_STOP,
+        STATE_DATA_ERROR,
+};
+
+enum {
+        EVENT_CMD_COMPLETE = 0,
+        EVENT_XFER_COMPLETE,
+        EVENT_DATA_COMPLETE,
+        EVENT_DATA_ERROR,
+        EVENT_XFER_ERROR
+};
+
+struct mmc_data;
+
+/**
+ * struct dw_mci - MMC controller state shared between all slots
+ * @lock: Spinlock protecting the queue and associated data.
+ * @regs: Pointer to MMIO registers.
+ * @sg: Scatterlist entry currently being processed by PIO code, if any.
+ * @pio_offset: Offset into the current scatterlist entry.
+ * @cur_slot: The slot which is currently using the controller.
+ * @mrq: The request currently being processed on @cur_slot,
+ *      or NULL if the controller is idle.
+ * @cmd: The command currently being sent to the card, or NULL.
+ * @data: The data currently being transferred, or NULL if no data
+ *      transfer is in progress.
+ * @use_dma: Whether DMA channel is initialized or not.
+ * @sg_dma: Bus address of DMA buffer.
+ * @sg_cpu: Virtual address of DMA buffer.
+ * @dma_ops: Pointer to platform-specific DMA callbacks.
+ * @cmd_status: Snapshot of SR taken upon completion of the current
+ *      command. Only valid when EVENT_CMD_COMPLETE is pending.
+ * @data_status: Snapshot of SR taken upon completion of the current
+ *      data transfer. Only valid when EVENT_DATA_COMPLETE or
+ *      EVENT_DATA_ERROR is pending.
+ * @stop_cmdr: Value to be loaded into CMDR when the stop command is
+ *      to be sent.
+ * @dir_status: Direction of current transfer.
+ * @tasklet: Tasklet running the request state machine.
+ * @card_tasklet: Tasklet handling card detect.
+ * @pending_events: Bitmask of events flagged by the interrupt handler
+ *      to be processed by the tasklet.
+ * @completed_events: Bitmask of events which the state machine has
+ *      processed.
+ * @state: Tasklet state.
+ * @queue: List of slots waiting for access to the controller.
+ * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
+ *      rate and timeout calculations.
+ * @current_speed: Configured rate of the controller.
+ * @num_slots: Number of slots available.
+ * @pdev: Platform device associated with the MMC controller.
+ * @pdata: Platform data associated with the MMC controller.
+ * @slot: Slots sharing this MMC controller.
+ * @data_shift: log2 of FIFO item size.
+ * @push_data: Pointer to FIFO push function.
+ * @pull_data: Pointer to FIFO pull function.
+ * @quirks: Set of quirks that apply to specific versions of the IP.
+ *
+ * Locking
+ * =======
+ *
+ * @lock is a softirq-safe spinlock protecting @queue as well as
+ * @cur_slot, @mrq and @state. These must always be updated
+ * at the same time while holding @lock.
+ *
+ * The @mrq field of struct dw_mci_slot is also protected by @lock,
+ * and must always be written at the same time as the slot is added to
+ * @queue.
+ *
+ * @pending_events and @completed_events are accessed using atomic bit
+ * operations, so they don't need any locking.
+ *
+ * None of the fields touched by the interrupt handler need any
+ * locking. However, ordering is important: Before EVENT_DATA_ERROR or
+ * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
+ * interrupts must be disabled and @data_status updated with a
+ * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
+ * CMDRDY interupt must be disabled and @cmd_status updated with a
+ * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
+ * bytes_xfered field of @data must be written. This is ensured by
+ * using barriers.
+ */
+struct dw_mci {
+        spinlock_t              lock;
+        void __iomem            *regs;
+
+        struct scatterlist      *sg;
+        unsigned int            pio_offset;
+
+        struct dw_mci_slot      *cur_slot;
+        struct mmc_request      *mrq;
+        struct mmc_command      *cmd;
+        struct mmc_data         *data;
+
+        /* DMA interface members*/
+        int                     use_dma;
+
+        dma_addr_t              sg_dma;
+        void                    *sg_cpu;
+        struct dw_mci_dma_ops   *dma_ops;
+#ifdef CONFIG_MMC_DW_IDMAC
+        unsigned int            ring_size;
+#else
+        struct dw_mci_dma_data  *dma_data;
+#endif
+        u32                     cmd_status;
+        u32                     data_status;
+        u32                     stop_cmdr;
+        u32                     dir_status;
+        struct tasklet_struct   tasklet;
+        struct tasklet_struct   card_tasklet;
+        unsigned long           pending_events;
+        unsigned long           completed_events;
+        enum dw_mci_state       state;
+        struct list_head        queue;
+
+        u32                     bus_hz;
+        u32                     current_speed;
+        u32                     num_slots;
+        struct platform_device  *pdev;
+        struct dw_mci_board     *pdata;
+        struct dw_mci_slot      *slot[MAX_MCI_SLOTS];
+
+        /* FIFO push and pull */
+        int                     data_shift;
+        void (*push_data)(struct dw_mci *host, void *buf, int cnt);
+        void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
+
+        /* Workaround flags */
+        u32                     quirks;
+};
+
+/* DMA ops for Internal/External DMAC interface */
+struct dw_mci_dma_ops {
+        /* DMA Ops */
+        int (*init)(struct dw_mci *host);
+        void (*start)(struct dw_mci *host, unsigned int sg_len);
+        void (*complete)(struct dw_mci *host);
+        void (*stop)(struct dw_mci *host);
+        void (*cleanup)(struct dw_mci *host);
+        void (*exit)(struct dw_mci *host);
+};
+
+/* IP Quirks/flags. */
+/* No special quirks or flags to cater for */
+#define DW_MCI_QUIRK_NONE               0
+/* DTO fix for command transmission with IDMAC configured */
+#define DW_MCI_QUIRK_IDMAC_DTO          1
+/* delay needed between retries on some 2.11a implementations */
+#define DW_MCI_QUIRK_RETRY_DELAY        2
+/* High Speed Capable - Supports HS cards (upto 50MHz) */
+#define DW_MCI_QUIRK_HIGHSPEED          4
+
+
+struct dma_pdata;
+
+struct block_settings {
+        unsigned short  max_segs;       /* see blk_queue_max_segments */
+        unsigned int    max_blk_size;   /* maximum size of one mmc block */
+        unsigned int    max_blk_count;  /* maximum number of blocks in one req*/
+        unsigned int    max_req_size;   /* maximum number of bytes in one req*/
+        unsigned int    max_seg_size;   /* see blk_queue_max_segment_size */
+};
+
+/* Board platform data */
+struct dw_mci_board {
+        u32 num_slots;
+
+        u32 quirks; /* Workaround / Quirk flags */
+        unsigned int bus_hz; /* Bus speed */
+
+        /* delay in mS before detecting cards after interrupt */
+        u32 detect_delay_ms;
+
+        int (*init)(u32 slot_id, irq_handler_t , void *);
+        int (*get_ro)(u32 slot_id);
+        int (*get_cd)(u32 slot_id);
+        int (*get_ocr)(u32 slot_id);
+        int (*get_bus_wd)(u32 slot_id);
+        /*
+         * Enable power to selected slot and set voltage to desired level.
+         * Voltage levels are specified using MMC_VDD_xxx defines defined
+         * in linux/mmc/host.h file.
+         */
+        void (*setpower)(u32 slot_id, u32 volt);
+        void (*exit)(u32 slot_id);
+        void (*select_slot)(u32 slot_id);
+
+        struct dw_mci_dma_ops *dma_ops;
+        struct dma_pdata *data;
+        struct block_settings *blk_settings;
+};
+
+#endif /* _LINUX_MMC_DW_MMC_H_ */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 30f6fad99a58..bcb793ec7374 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -131,6 +131,9 @@ struct mmc_host {
         unsigned int            f_max;
         unsigned int            f_init;
         u32                     ocr_avail;
+        u32                     ocr_avail_sdio; /* SDIO-specific OCR */
+        u32                     ocr_avail_sd;   /* SD-specific OCR */
+        u32                     ocr_avail_mmc;  /* MMC-specific OCR */
         struct notifier_block   pm_notify;
 
 #define MMC_VDD_165_195         0x00000080      /* VDD voltage 1.65 - 1.95 */
@@ -169,9 +172,20 @@ struct mmc_host {
 #define MMC_CAP_1_2V_DDR        (1 << 12)       /* can support */
                                                 /* DDR mode at 1.2V */
 #define MMC_CAP_POWER_OFF_CARD  (1 << 13)       /* Can power off after boot */
+#define MMC_CAP_BUS_WIDTH_TEST  (1 << 14)       /* CMD14/CMD19 bus width ok */
 
         mmc_pm_flag_t           pm_caps;        /* supported pm features */
 
+#ifdef CONFIG_MMC_CLKGATE
+        int                     clk_requests;   /* internal reference counter */
+        unsigned int            clk_delay;      /* number of MCI clk hold cycles */
+        bool                    clk_gated;      /* clock gated */
+        struct work_struct      clk_gate_work; /* delayed clock gate */
+        unsigned int            clk_old;        /* old clock value cache */
+        spinlock_t              clk_lock;       /* lock for clk fields */
+        struct mutex            clk_gate_mutex; /* mutex for clock gating */
+#endif
+
         /* host specific block data */
         unsigned int            max_seg_size;   /* see blk_queue_max_segment_size */
         unsigned short          max_segs;       /* see blk_queue_max_segments */
@@ -307,5 +321,10 @@ static inline int mmc_card_is_removable(struct mmc_host *host)
         return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable;
 }
 
+static inline int mmc_card_is_powered_resumed(struct mmc_host *host)
+{
+        return host->pm_flags & MMC_PM_KEEP_POWER;
+}
+
 #endif
 
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 956fbd877692..612301f85d14 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -40,7 +40,9 @@
 #define MMC_READ_DAT_UNTIL_STOP  11   /* adtc [31:0] dadr        R1  */
 #define MMC_STOP_TRANSMISSION    12   /* ac                      R1b */
 #define MMC_SEND_STATUS          13   /* ac   [31:16] RCA        R1  */
+#define MMC_BUS_TEST_R           14   /* adtc                    R1  */
 #define MMC_GO_INACTIVE_STATE    15   /* ac   [31:16] RCA            */
+#define MMC_BUS_TEST_W           19   /* adtc                    R1  */
 #define MMC_SPI_READ_OCR         58   /* spi                  spi_R3 */
 #define MMC_SPI_CRC_ON_OFF       59   /* spi  [0:0] flag      spi_R1 */
 
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 1fdc673f2396..83bd9f76709a 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -83,6 +83,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1<<28)
 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
 #define SDHCI_QUIRK_NO_HISPD_BIT                        (1<<29)
+/* Controller treats ADMA descriptors with length 0000h incorrectly */
+#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC            (1<<30)
 
         int irq;                /* Device IRQ */
         void __iomem *ioaddr;   /* Mapped address */
@@ -139,6 +141,10 @@ struct sdhci_host {
 
         unsigned int caps;      /* Alternative capabilities */
 
+        unsigned int            ocr_avail_sdio; /* OCR bit masks */
+        unsigned int            ocr_avail_sd;
+        unsigned int            ocr_avail_mmc;
+
         unsigned long private[0] ____cacheline_aligned;
 };
 #endif /* __SDHCI_H */