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Diffstat (limited to 'include/linux/mmc/sdhci.h')
-rw-r--r--include/linux/mmc/sdhci.h18
1 files changed, 16 insertions, 2 deletions
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dba793e3a331..375af80bde7d 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,12 @@ struct sdhci_host {
100#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7) 100#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
101/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */ 101/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
102#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8) 102#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
103/* Controller does not support 64-bit DMA */
104#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
105/* need clear transfer mode register before send cmd */
106#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
107/* Capability register bit-63 indicates HS400 support */
108#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
103 109
104 int irq; /* Device IRQ */ 110 int irq; /* Device IRQ */
105 void __iomem *ioaddr; /* Mapped address */ 111 void __iomem *ioaddr; /* Mapped address */
@@ -130,6 +136,7 @@ struct sdhci_host {
130#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ 136#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
131#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ 137#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
132#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */ 138#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
139#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
133 140
134 unsigned int version; /* SDHCI spec. version */ 141 unsigned int version; /* SDHCI spec. version */
135 142
@@ -155,12 +162,19 @@ struct sdhci_host {
155 162
156 int sg_count; /* Mapped sg entries */ 163 int sg_count; /* Mapped sg entries */
157 164
158 u8 *adma_desc; /* ADMA descriptor table */ 165 void *adma_table; /* ADMA descriptor table */
159 u8 *align_buffer; /* Bounce buffer */ 166 void *align_buffer; /* Bounce buffer */
167
168 size_t adma_table_sz; /* ADMA descriptor table size */
169 size_t align_buffer_sz; /* Bounce buffer size */
160 170
161 dma_addr_t adma_addr; /* Mapped ADMA descr. table */ 171 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
162 dma_addr_t align_addr; /* Mapped bounce buffer */ 172 dma_addr_t align_addr; /* Mapped bounce buffer */
163 173
174 unsigned int desc_sz; /* ADMA descriptor size */
175 unsigned int align_sz; /* ADMA alignment */
176 unsigned int align_mask; /* ADMA alignment mask */
177
164 struct tasklet_struct finish_tasklet; /* Tasklet structures */ 178 struct tasklet_struct finish_tasklet; /* Tasklet structures */
165 179
166 struct timer_list timer; /* Timer for timeouts */ 180 struct timer_list timer; /* Timer for timeouts */