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-rw-r--r--include/linux/mmc/sdhci.h165
1 files changed, 165 insertions, 0 deletions
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
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+++ b/include/linux/mmc/sdhci.h
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1/*
2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11#ifndef __SDHCI_H
12#define __SDHCI_H
13
14#include <linux/scatterlist.h>
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19
20struct sdhci_host {
21 /* Data set by hardware interface driver */
22 const char *hw_name; /* Hardware bus name */
23
24 unsigned int quirks; /* Deviations from spec. */
25
26/* Controller doesn't honor resets unless we touch the clock register */
27#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
28/* Controller has bad caps bits, but really supports DMA */
29#define SDHCI_QUIRK_FORCE_DMA (1<<1)
30/* Controller doesn't like to be reset when there is no card inserted. */
31#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
32/* Controller doesn't like clearing the power reg before a change */
33#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
34/* Controller has flaky internal state so reset it on each ios change */
35#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
36/* Controller has an unusable DMA engine */
37#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
38/* Controller has an unusable ADMA engine */
39#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
40/* Controller can only DMA from 32-bit aligned addresses */
41#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
42/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
43#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
44/* Controller can only ADMA chunks that are a multiple of 32 bits */
45#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
46/* Controller needs to be reset after each request to stay stable */
47#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
48/* Controller needs voltage and power writes to happen separately */
49#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
50/* Controller provides an incorrect timeout value for transfers */
51#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
52/* Controller has an issue with buffer bits for small transfers */
53#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
54/* Controller does not provide transfer-complete interrupt when not busy */
55#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
56/* Controller has unreliable card detection */
57#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
58/* Controller reports inverted write-protect state */
59#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
60/* Controller has nonstandard clock management */
61#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
62/* Controller does not like fast PIO transfers */
63#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
64/* Controller losing signal/interrupt enable states after reset */
65#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
66/* Controller has to be forced to use block size of 2048 bytes */
67#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
68/* Controller cannot do multi-block transfers */
69#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
70/* Controller can only handle 1-bit data transfers */
71#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
72/* Controller needs 10ms delay between applying power and clock */
73#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
74/* Controller uses SDCLK instead of TMCLK for data timeouts */
75#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
76/* Controller reports wrong base clock capability */
77#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
78/* Controller cannot support End Attribute in NOP ADMA descriptor */
79#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
80/* Controller is missing device caps. Use caps provided by host */
81#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
82/* Controller uses Auto CMD12 command to stop the transfer */
83#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
84/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
85#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
86/* Controller treats ADMA descriptors with length 0000h incorrectly */
87#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
88/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
89#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
90
91 int irq; /* Device IRQ */
92 void __iomem *ioaddr; /* Mapped address */
93
94 const struct sdhci_ops *ops; /* Low level hw interface */
95
96 struct regulator *vmmc; /* Power regulator */
97
98 /* Internal data */
99 struct mmc_host *mmc; /* MMC structure */
100 u64 dma_mask; /* custom DMA mask */
101
102#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
103 struct led_classdev led; /* LED control */
104 char led_name[32];
105#endif
106
107 spinlock_t lock; /* Mutex */
108
109 int flags; /* Host attributes */
110#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
111#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
112#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
113#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
114#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
115#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
116#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
117#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
118
119 unsigned int version; /* SDHCI spec. version */
120
121 unsigned int max_clk; /* Max possible freq (MHz) */
122 unsigned int timeout_clk; /* Timeout freq (KHz) */
123 unsigned int clk_mul; /* Clock Muliplier value */
124
125 unsigned int clock; /* Current clock (MHz) */
126 u8 pwr; /* Current voltage */
127
128 struct mmc_request *mrq; /* Current request */
129 struct mmc_command *cmd; /* Current command */
130 struct mmc_data *data; /* Current data request */
131 unsigned int data_early:1; /* Data finished before cmd */
132
133 struct sg_mapping_iter sg_miter; /* SG state for PIO */
134 unsigned int blocks; /* remaining PIO blocks */
135
136 int sg_count; /* Mapped sg entries */
137
138 u8 *adma_desc; /* ADMA descriptor table */
139 u8 *align_buffer; /* Bounce buffer */
140
141 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
142 dma_addr_t align_addr; /* Mapped bounce buffer */
143
144 struct tasklet_struct card_tasklet; /* Tasklet structures */
145 struct tasklet_struct finish_tasklet;
146
147 struct timer_list timer; /* Timer for timeouts */
148
149 unsigned int caps; /* Alternative capabilities */
150
151 unsigned int ocr_avail_sdio; /* OCR bit masks */
152 unsigned int ocr_avail_sd;
153 unsigned int ocr_avail_mmc;
154
155 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
156 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
157
158 unsigned int tuning_count; /* Timer count for re-tuning */
159 unsigned int tuning_mode; /* Re-tuning mode supported by host */
160#define SDHCI_TUNING_MODE_1 0
161 struct timer_list tuning_timer; /* Timer for tuning */
162
163 unsigned long private[0] ____cacheline_aligned;
164};
165#endif /* __SDHCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 04:55:22 -0500