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-rw-r--r--include/linux/mlx4/cmd.h1
-rw-r--r--include/linux/mlx4/cq.h5
-rw-r--r--include/linux/mlx4/device.h39
-rw-r--r--include/linux/mlx4/qp.h6
4 files changed, 50 insertions, 1 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index 8df61bc5da00..b0ec0fe035c0 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -180,6 +180,7 @@ enum {
180 MLX4_SET_PORT_GID_TABLE = 0x5, 180 MLX4_SET_PORT_GID_TABLE = 0x5,
181 MLX4_SET_PORT_PRIO2TC = 0x8, 181 MLX4_SET_PORT_PRIO2TC = 0x8,
182 MLX4_SET_PORT_SCHEDULER = 0x9, 182 MLX4_SET_PORT_SCHEDULER = 0x9,
183 MLX4_SET_PORT_VXLAN = 0xB
183}; 184};
184 185
185enum { 186enum {
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 98fa492cf406..5dd0d70a0689 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -81,7 +81,12 @@ struct mlx4_ts_cqe {
81} __packed; 81} __packed;
82 82
83enum { 83enum {
84 MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31,
84 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, 85 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
86 MLX4_CQE_L2_TUNNEL = 1 << 27,
87 MLX4_CQE_L2_TUNNEL_CSUM = 1 << 26,
88 MLX4_CQE_L2_TUNNEL_IPV4 = 1 << 25,
89
85 MLX4_CQE_QPN_MASK = 0xffffff, 90 MLX4_CQE_QPN_MASK = 0xffffff,
86}; 91};
87 92
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 7d3a523160ba..c99ecf6d2c67 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -119,6 +119,11 @@ static inline const char *mlx4_steering_mode_str(int steering_mode)
119} 119}
120 120
121enum { 121enum {
122 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
123 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
124};
125
126enum {
122 MLX4_DEV_CAP_FLAG_RC = 1LL << 0, 127 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
123 MLX4_DEV_CAP_FLAG_UC = 1LL << 1, 128 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
124 MLX4_DEV_CAP_FLAG_UD = 1LL << 2, 129 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
@@ -160,7 +165,8 @@ enum {
160 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, 165 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
161 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, 166 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
162 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, 167 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
163 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8 168 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
169 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 9
164}; 170};
165 171
166enum { 172enum {
@@ -454,6 +460,8 @@ struct mlx4_caps {
454 u32 userspace_caps; /* userspace must be aware of these */ 460 u32 userspace_caps; /* userspace must be aware of these */
455 u32 function_caps; /* VFs must be aware of these */ 461 u32 function_caps; /* VFs must be aware of these */
456 u16 hca_core_clock; 462 u16 hca_core_clock;
463 u64 phys_port_id[MLX4_MAX_PORTS + 1];
464 int tunnel_offload_mode;
457}; 465};
458 466
459struct mlx4_buf_list { 467struct mlx4_buf_list {
@@ -908,6 +916,7 @@ enum mlx4_net_trans_rule_id {
908 MLX4_NET_TRANS_RULE_ID_IPV4, 916 MLX4_NET_TRANS_RULE_ID_IPV4,
909 MLX4_NET_TRANS_RULE_ID_TCP, 917 MLX4_NET_TRANS_RULE_ID_TCP,
910 MLX4_NET_TRANS_RULE_ID_UDP, 918 MLX4_NET_TRANS_RULE_ID_UDP,
919 MLX4_NET_TRANS_RULE_ID_VXLAN,
911 MLX4_NET_TRANS_RULE_NUM, /* should be last */ 920 MLX4_NET_TRANS_RULE_NUM, /* should be last */
912}; 921};
913 922
@@ -965,6 +974,12 @@ struct mlx4_spec_ib {
965 u8 dst_gid_msk[16]; 974 u8 dst_gid_msk[16];
966}; 975};
967 976
977struct mlx4_spec_vxlan {
978 __be32 vni;
979 __be32 vni_mask;
980
981};
982
968struct mlx4_spec_list { 983struct mlx4_spec_list {
969 struct list_head list; 984 struct list_head list;
970 enum mlx4_net_trans_rule_id id; 985 enum mlx4_net_trans_rule_id id;
@@ -973,6 +988,7 @@ struct mlx4_spec_list {
973 struct mlx4_spec_ib ib; 988 struct mlx4_spec_ib ib;
974 struct mlx4_spec_ipv4 ipv4; 989 struct mlx4_spec_ipv4 ipv4;
975 struct mlx4_spec_tcp_udp tcp_udp; 990 struct mlx4_spec_tcp_udp tcp_udp;
991 struct mlx4_spec_vxlan vxlan;
976 }; 992 };
977}; 993};
978 994
@@ -1059,6 +1075,15 @@ struct mlx4_net_trans_rule_hw_ipv4 {
1059 __be32 src_ip_msk; 1075 __be32 src_ip_msk;
1060} __packed; 1076} __packed;
1061 1077
1078struct mlx4_net_trans_rule_hw_vxlan {
1079 u8 size;
1080 u8 rsvd;
1081 __be16 id;
1082 __be32 rsvd1;
1083 __be32 vni;
1084 __be32 vni_mask;
1085} __packed;
1086
1062struct _rule_hw { 1087struct _rule_hw {
1063 union { 1088 union {
1064 struct { 1089 struct {
@@ -1070,9 +1095,19 @@ struct _rule_hw {
1070 struct mlx4_net_trans_rule_hw_ib ib; 1095 struct mlx4_net_trans_rule_hw_ib ib;
1071 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 1096 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1072 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 1097 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1098 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1073 }; 1099 };
1074}; 1100};
1075 1101
1102enum {
1103 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1104 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1105 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1106 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1107 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1108};
1109
1110
1076int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, 1111int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1077 enum mlx4_net_trans_promisc_mode mode); 1112 enum mlx4_net_trans_promisc_mode mode);
1078int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1113int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
@@ -1095,6 +1130,7 @@ int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1095int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); 1130int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1096int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, 1131int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1097 u8 *pg, u16 *ratelimit); 1132 u8 *pg, u16 *ratelimit);
1133int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering);
1098int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 1134int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1099int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1135int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1100void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1136void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
@@ -1113,6 +1149,7 @@ int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1113 int *vector); 1149 int *vector);
1114void mlx4_release_eq(struct mlx4_dev *dev, int vec); 1150void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1115 1151
1152int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1116int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 1153int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1117int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 1154int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1118 1155
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 6d351473c292..59f8ba84568b 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -109,6 +109,10 @@ enum {
109 MLX4_RSS_TCP_IPV4 = 1 << 4, 109 MLX4_RSS_TCP_IPV4 = 1 << 4,
110 MLX4_RSS_IPV4 = 1 << 5, 110 MLX4_RSS_IPV4 = 1 << 5,
111 111
112 MLX4_RSS_BY_OUTER_HEADERS = 0 << 6,
113 MLX4_RSS_BY_INNER_HEADERS = 2 << 6,
114 MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6,
115
112 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */ 116 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
113 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24, 117 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
114 /* offset of being RSS indirection QP within mlx4_qp_context.flags */ 118 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
@@ -252,6 +256,8 @@ enum { /* param3 */
252 256
253enum { 257enum {
254 MLX4_WQE_CTRL_NEC = 1 << 29, 258 MLX4_WQE_CTRL_NEC = 1 << 29,
259 MLX4_WQE_CTRL_IIP = 1 << 28,
260 MLX4_WQE_CTRL_ILP = 1 << 27,
255 MLX4_WQE_CTRL_FENCE = 1 << 6, 261 MLX4_WQE_CTRL_FENCE = 1 << 6,
256 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 262 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
257 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 263 MLX4_WQE_CTRL_SOLICITED = 1 << 1,