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-rw-r--r--include/linux/mlx4/cmd.h178
-rw-r--r--include/linux/mlx4/cq.h123
-rw-r--r--include/linux/mlx4/device.h331
-rw-r--r--include/linux/mlx4/doorbell.h97
-rw-r--r--include/linux/mlx4/driver.h59
-rw-r--r--include/linux/mlx4/qp.h288
-rw-r--r--include/linux/mlx4/srq.h42
7 files changed, 1118 insertions, 0 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
new file mode 100644
index 000000000000..4fb552d12f7a
--- /dev/null
+++ b/include/linux/mlx4/cmd.h
@@ -0,0 +1,178 @@
1/*
2 * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_CMD_H
34#define MLX4_CMD_H
35
36#include <linux/dma-mapping.h>
37
38enum {
39 /* initialization and general commands */
40 MLX4_CMD_SYS_EN = 0x1,
41 MLX4_CMD_SYS_DIS = 0x2,
42 MLX4_CMD_MAP_FA = 0xfff,
43 MLX4_CMD_UNMAP_FA = 0xffe,
44 MLX4_CMD_RUN_FW = 0xff6,
45 MLX4_CMD_MOD_STAT_CFG = 0x34,
46 MLX4_CMD_QUERY_DEV_CAP = 0x3,
47 MLX4_CMD_QUERY_FW = 0x4,
48 MLX4_CMD_ENABLE_LAM = 0xff8,
49 MLX4_CMD_DISABLE_LAM = 0xff7,
50 MLX4_CMD_QUERY_DDR = 0x5,
51 MLX4_CMD_QUERY_ADAPTER = 0x6,
52 MLX4_CMD_INIT_HCA = 0x7,
53 MLX4_CMD_CLOSE_HCA = 0x8,
54 MLX4_CMD_INIT_PORT = 0x9,
55 MLX4_CMD_CLOSE_PORT = 0xa,
56 MLX4_CMD_QUERY_HCA = 0xb,
57 MLX4_CMD_SET_PORT = 0xc,
58 MLX4_CMD_ACCESS_DDR = 0x2e,
59 MLX4_CMD_MAP_ICM = 0xffa,
60 MLX4_CMD_UNMAP_ICM = 0xff9,
61 MLX4_CMD_MAP_ICM_AUX = 0xffc,
62 MLX4_CMD_UNMAP_ICM_AUX = 0xffb,
63 MLX4_CMD_SET_ICM_SIZE = 0xffd,
64
65 /* TPT commands */
66 MLX4_CMD_SW2HW_MPT = 0xd,
67 MLX4_CMD_QUERY_MPT = 0xe,
68 MLX4_CMD_HW2SW_MPT = 0xf,
69 MLX4_CMD_READ_MTT = 0x10,
70 MLX4_CMD_WRITE_MTT = 0x11,
71 MLX4_CMD_SYNC_TPT = 0x2f,
72
73 /* EQ commands */
74 MLX4_CMD_MAP_EQ = 0x12,
75 MLX4_CMD_SW2HW_EQ = 0x13,
76 MLX4_CMD_HW2SW_EQ = 0x14,
77 MLX4_CMD_QUERY_EQ = 0x15,
78
79 /* CQ commands */
80 MLX4_CMD_SW2HW_CQ = 0x16,
81 MLX4_CMD_HW2SW_CQ = 0x17,
82 MLX4_CMD_QUERY_CQ = 0x18,
83 MLX4_CMD_RESIZE_CQ = 0x2c,
84
85 /* SRQ commands */
86 MLX4_CMD_SW2HW_SRQ = 0x35,
87 MLX4_CMD_HW2SW_SRQ = 0x36,
88 MLX4_CMD_QUERY_SRQ = 0x37,
89 MLX4_CMD_ARM_SRQ = 0x40,
90
91 /* QP/EE commands */
92 MLX4_CMD_RST2INIT_QP = 0x19,
93 MLX4_CMD_INIT2RTR_QP = 0x1a,
94 MLX4_CMD_RTR2RTS_QP = 0x1b,
95 MLX4_CMD_RTS2RTS_QP = 0x1c,
96 MLX4_CMD_SQERR2RTS_QP = 0x1d,
97 MLX4_CMD_2ERR_QP = 0x1e,
98 MLX4_CMD_RTS2SQD_QP = 0x1f,
99 MLX4_CMD_SQD2SQD_QP = 0x38,
100 MLX4_CMD_SQD2RTS_QP = 0x20,
101 MLX4_CMD_2RST_QP = 0x21,
102 MLX4_CMD_QUERY_QP = 0x22,
103 MLX4_CMD_INIT2INIT_QP = 0x2d,
104 MLX4_CMD_SUSPEND_QP = 0x32,
105 MLX4_CMD_UNSUSPEND_QP = 0x33,
106 /* special QP and management commands */
107 MLX4_CMD_CONF_SPECIAL_QP = 0x23,
108 MLX4_CMD_MAD_IFC = 0x24,
109
110 /* multicast commands */
111 MLX4_CMD_READ_MCG = 0x25,
112 MLX4_CMD_WRITE_MCG = 0x26,
113 MLX4_CMD_MGID_HASH = 0x27,
114
115 /* miscellaneous commands */
116 MLX4_CMD_DIAG_RPRT = 0x30,
117 MLX4_CMD_NOP = 0x31,
118
119 /* debug commands */
120 MLX4_CMD_QUERY_DEBUG_MSG = 0x2a,
121 MLX4_CMD_SET_DEBUG_MSG = 0x2b,
122};
123
124enum {
125 MLX4_CMD_TIME_CLASS_A = 10000,
126 MLX4_CMD_TIME_CLASS_B = 10000,
127 MLX4_CMD_TIME_CLASS_C = 10000,
128};
129
130enum {
131 MLX4_MAILBOX_SIZE = 4096
132};
133
134struct mlx4_dev;
135
136struct mlx4_cmd_mailbox {
137 void *buf;
138 dma_addr_t dma;
139};
140
141int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
142 int out_is_imm, u32 in_modifier, u8 op_modifier,
143 u16 op, unsigned long timeout);
144
145/* Invoke a command with no output parameter */
146static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier,
147 u8 op_modifier, u16 op, unsigned long timeout)
148{
149 return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier,
150 op_modifier, op, timeout);
151}
152
153/* Invoke a command with an output mailbox */
154static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param,
155 u32 in_modifier, u8 op_modifier, u16 op,
156 unsigned long timeout)
157{
158 return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier,
159 op_modifier, op, timeout);
160}
161
162/*
163 * Invoke a command with an immediate output parameter (and copy the
164 * output into the caller's out_param pointer after the command
165 * executes).
166 */
167static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
168 u32 in_modifier, u8 op_modifier, u16 op,
169 unsigned long timeout)
170{
171 return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier,
172 op_modifier, op, timeout);
173}
174
175struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
176void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);
177
178#endif /* MLX4_CMD_H */
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
new file mode 100644
index 000000000000..0181e0a57cbf
--- /dev/null
+++ b/include/linux/mlx4/cq.h
@@ -0,0 +1,123 @@
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_CQ_H
34#define MLX4_CQ_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39#include <linux/mlx4/doorbell.h>
40
41struct mlx4_cqe {
42 __be32 my_qpn;
43 __be32 immed_rss_invalid;
44 __be32 g_mlpath_rqpn;
45 u8 sl;
46 u8 reserved1;
47 __be16 rlid;
48 u32 reserved2;
49 __be32 byte_cnt;
50 __be16 wqe_index;
51 __be16 checksum;
52 u8 reserved3[3];
53 u8 owner_sr_opcode;
54};
55
56struct mlx4_err_cqe {
57 __be32 my_qpn;
58 u32 reserved1[5];
59 __be16 wqe_index;
60 u8 vendor_err_syndrome;
61 u8 syndrome;
62 u8 reserved2[3];
63 u8 owner_sr_opcode;
64};
65
66enum {
67 MLX4_CQE_OWNER_MASK = 0x80,
68 MLX4_CQE_IS_SEND_MASK = 0x40,
69 MLX4_CQE_OPCODE_MASK = 0x1f
70};
71
72enum {
73 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
74 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
75 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
76 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
77 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
78 MLX4_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
79 MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
80 MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
81 MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
82 MLX4_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
83 MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
84 MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
86};
87
88static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
89 void __iomem *uar_page,
90 spinlock_t *doorbell_lock)
91{
92 __be32 doorbell[2];
93 u32 sn;
94 u32 ci;
95
96 sn = cq->arm_sn & 3;
97 ci = cq->cons_index & 0xffffff;
98
99 *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
100
101 /*
102 * Make sure that the doorbell record in host memory is
103 * written before ringing the doorbell via PCI MMIO.
104 */
105 wmb();
106
107 doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
108 doorbell[1] = cpu_to_be32(ci);
109
110 mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
111}
112
113static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
114{
115 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
116}
117
118enum {
119 MLX4_CQ_DB_REQ_NOT_SOL = 1 << 24,
120 MLX4_CQ_DB_REQ_NOT = 2 << 24
121};
122
123#endif /* MLX4_CQ_H */
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
new file mode 100644
index 000000000000..8c5f8fd86841
--- /dev/null
+++ b/include/linux/mlx4/device.h
@@ -0,0 +1,331 @@
1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
40#include <asm/atomic.h>
41
42enum {
43 MLX4_FLAG_MSI_X = 1 << 0,
44};
45
46enum {
47 MLX4_MAX_PORTS = 2
48};
49
50enum {
51 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
52 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
53 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
54 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
55 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
56 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
57 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
58 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
59 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
60 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
61 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
62 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
63 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
64};
65
66enum mlx4_event {
67 MLX4_EVENT_TYPE_COMP = 0x00,
68 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
69 MLX4_EVENT_TYPE_COMM_EST = 0x02,
70 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
71 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
72 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
73 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
74 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
75 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
76 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
77 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
78 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
79 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
80 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
81 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
82 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
83 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
84 MLX4_EVENT_TYPE_CMD = 0x0a
85};
86
87enum {
88 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
89 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
90};
91
92enum {
93 MLX4_PERM_LOCAL_READ = 1 << 10,
94 MLX4_PERM_LOCAL_WRITE = 1 << 11,
95 MLX4_PERM_REMOTE_READ = 1 << 12,
96 MLX4_PERM_REMOTE_WRITE = 1 << 13,
97 MLX4_PERM_ATOMIC = 1 << 14
98};
99
100enum {
101 MLX4_OPCODE_NOP = 0x00,
102 MLX4_OPCODE_SEND_INVAL = 0x01,
103 MLX4_OPCODE_RDMA_WRITE = 0x08,
104 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
105 MLX4_OPCODE_SEND = 0x0a,
106 MLX4_OPCODE_SEND_IMM = 0x0b,
107 MLX4_OPCODE_LSO = 0x0e,
108 MLX4_OPCODE_RDMA_READ = 0x10,
109 MLX4_OPCODE_ATOMIC_CS = 0x11,
110 MLX4_OPCODE_ATOMIC_FA = 0x12,
111 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
112 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
113 MLX4_OPCODE_BIND_MW = 0x18,
114 MLX4_OPCODE_FMR = 0x19,
115 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
116 MLX4_OPCODE_CONFIG_CMD = 0x1f,
117
118 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
119 MLX4_RECV_OPCODE_SEND = 0x01,
120 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
121 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
122
123 MLX4_CQE_OPCODE_ERROR = 0x1e,
124 MLX4_CQE_OPCODE_RESIZE = 0x16,
125};
126
127enum {
128 MLX4_STAT_RATE_OFFSET = 5
129};
130
131struct mlx4_caps {
132 u64 fw_ver;
133 int num_ports;
134 int vl_cap;
135 int mtu_cap;
136 int gid_table_len;
137 int pkey_table_len;
138 int local_ca_ack_delay;
139 int num_uars;
140 int bf_reg_size;
141 int bf_regs_per_page;
142 int max_sq_sg;
143 int max_rq_sg;
144 int num_qps;
145 int max_wqes;
146 int max_sq_desc_sz;
147 int max_rq_desc_sz;
148 int max_qp_init_rdma;
149 int max_qp_dest_rdma;
150 int reserved_qps;
151 int sqp_start;
152 int num_srqs;
153 int max_srq_wqes;
154 int max_srq_sge;
155 int reserved_srqs;
156 int num_cqs;
157 int max_cqes;
158 int reserved_cqs;
159 int num_eqs;
160 int reserved_eqs;
161 int num_mpts;
162 int num_mtt_segs;
163 int fmr_reserved_mtts;
164 int reserved_mtts;
165 int reserved_mrws;
166 int reserved_uars;
167 int num_mgms;
168 int num_amgms;
169 int reserved_mcgs;
170 int num_qp_per_mgm;
171 int num_pds;
172 int reserved_pds;
173 int mtt_entry_sz;
174 u32 page_size_cap;
175 u32 flags;
176 u16 stat_rate_support;
177 u8 port_width_cap;
178};
179
180struct mlx4_buf_list {
181 void *buf;
182 dma_addr_t map;
183};
184
185struct mlx4_buf {
186 union {
187 struct mlx4_buf_list direct;
188 struct mlx4_buf_list *page_list;
189 } u;
190 int nbufs;
191 int npages;
192 int page_shift;
193};
194
195struct mlx4_mtt {
196 u32 first_seg;
197 int order;
198 int page_shift;
199};
200
201struct mlx4_mr {
202 struct mlx4_mtt mtt;
203 u64 iova;
204 u64 size;
205 u32 key;
206 u32 pd;
207 u32 access;
208 int enabled;
209};
210
211struct mlx4_uar {
212 unsigned long pfn;
213 int index;
214};
215
216struct mlx4_cq {
217 void (*comp) (struct mlx4_cq *);
218 void (*event) (struct mlx4_cq *, enum mlx4_event);
219
220 struct mlx4_uar *uar;
221
222 u32 cons_index;
223
224 __be32 *set_ci_db;
225 __be32 *arm_db;
226 int arm_sn;
227
228 int cqn;
229
230 atomic_t refcount;
231 struct completion free;
232};
233
234struct mlx4_qp {
235 void (*event) (struct mlx4_qp *, enum mlx4_event);
236
237 int qpn;
238
239 atomic_t refcount;
240 struct completion free;
241};
242
243struct mlx4_srq {
244 void (*event) (struct mlx4_srq *, enum mlx4_event);
245
246 int srqn;
247 int max;
248 int max_gs;
249 int wqe_shift;
250
251 atomic_t refcount;
252 struct completion free;
253};
254
255struct mlx4_av {
256 __be32 port_pd;
257 u8 reserved1;
258 u8 g_slid;
259 __be16 dlid;
260 u8 reserved2;
261 u8 gid_index;
262 u8 stat_rate;
263 u8 hop_limit;
264 __be32 sl_tclass_flowlabel;
265 u8 dgid[16];
266};
267
268struct mlx4_dev {
269 struct pci_dev *pdev;
270 unsigned long flags;
271 struct mlx4_caps caps;
272 struct radix_tree_root qp_table_tree;
273};
274
275struct mlx4_init_port_param {
276 int set_guid0;
277 int set_node_guid;
278 int set_si_guid;
279 u16 mtu;
280 int port_width_cap;
281 u16 vl_cap;
282 u16 max_gid;
283 u16 max_pkey;
284 u64 guid0;
285 u64 node_guid;
286 u64 si_guid;
287};
288
289int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
290 struct mlx4_buf *buf);
291void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
292
293int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
294void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
295
296int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
297void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
298
299int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
300 struct mlx4_mtt *mtt);
301void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
302u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
303
304int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
305 int npages, int page_shift, struct mlx4_mr *mr);
306void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
307int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
308int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
309 int start_index, int npages, u64 *page_list);
310int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
311 struct mlx4_buf *buf);
312
313int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
314 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq);
315void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
316
317int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
318void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
319
320int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
321 u64 db_rec, struct mlx4_srq *srq);
322void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
323int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
324
325int mlx4_INIT_PORT(struct mlx4_dev *dev, struct mlx4_init_port_param *param, int port);
326int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
327
328int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
329int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
330
331#endif /* MLX4_DEVICE_H */
diff --git a/include/linux/mlx4/doorbell.h b/include/linux/mlx4/doorbell.h
new file mode 100644
index 000000000000..3f2da442d7cb
--- /dev/null
+++ b/include/linux/mlx4/doorbell.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#ifndef MLX4_DOORBELL_H
36#define MLX4_DOORBELL_H
37
38#include <linux/types.h>
39#include <linux/io.h>
40
41#define MLX4_SEND_DOORBELL 0x14
42#define MLX4_CQ_DOORBELL 0x20
43
44#if BITS_PER_LONG == 64
45/*
46 * Assume that we can just write a 64-bit doorbell atomically. s390
47 * actually doesn't have writeq() but S/390 systems don't even have
48 * PCI so we won't worry about it.
49 */
50
51#define MLX4_DECLARE_DOORBELL_LOCK(name)
52#define MLX4_INIT_DOORBELL_LOCK(ptr) do { } while (0)
53#define MLX4_GET_DOORBELL_LOCK(ptr) (NULL)
54
55static inline void mlx4_write64_raw(__be64 val, void __iomem *dest)
56{
57 __raw_writeq((__force u64) val, dest);
58}
59
60static inline void mlx4_write64(__be32 val[2], void __iomem *dest,
61 spinlock_t *doorbell_lock)
62{
63 __raw_writeq(*(u64 *) val, dest);
64}
65
66#else
67
68/*
69 * Just fall back to a spinlock to protect the doorbell if
70 * BITS_PER_LONG is 32 -- there's no portable way to do atomic 64-bit
71 * MMIO writes.
72 */
73
74#define MLX4_DECLARE_DOORBELL_LOCK(name) spinlock_t name;
75#define MLX4_INIT_DOORBELL_LOCK(ptr) spin_lock_init(ptr)
76#define MLX4_GET_DOORBELL_LOCK(ptr) (ptr)
77
78static inline void mlx4_write64_raw(__be64 val, void __iomem *dest)
79{
80 __raw_writel(((__force u32 *) &val)[0], dest);
81 __raw_writel(((__force u32 *) &val)[1], dest + 4);
82}
83
84static inline void mlx4_write64(__be32 val[2], void __iomem *dest,
85 spinlock_t *doorbell_lock)
86{
87 unsigned long flags;
88
89 spin_lock_irqsave(doorbell_lock, flags);
90 __raw_writel((__force u32) val[0], dest);
91 __raw_writel((__force u32) val[1], dest + 4);
92 spin_unlock_irqrestore(doorbell_lock, flags);
93}
94
95#endif
96
97#endif /* MLX4_DOORBELL_H */
diff --git a/include/linux/mlx4/driver.h b/include/linux/mlx4/driver.h
new file mode 100644
index 000000000000..1b835ca49df1
--- /dev/null
+++ b/include/linux/mlx4/driver.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DRIVER_H
34#define MLX4_DRIVER_H
35
36#include <linux/device.h>
37
38struct mlx4_dev;
39
40enum mlx4_dev_event {
41 MLX4_DEV_EVENT_CATASTROPHIC_ERROR,
42 MLX4_DEV_EVENT_PORT_UP,
43 MLX4_DEV_EVENT_PORT_DOWN,
44 MLX4_DEV_EVENT_PORT_REINIT,
45};
46
47struct mlx4_interface {
48 void * (*add) (struct mlx4_dev *dev);
49 void (*remove)(struct mlx4_dev *dev, void *context);
50 void (*event) (struct mlx4_dev *dev, void *context,
51 enum mlx4_dev_event event, int subtype,
52 int port);
53 struct list_head list;
54};
55
56int mlx4_register_interface(struct mlx4_interface *intf);
57void mlx4_unregister_interface(struct mlx4_interface *intf);
58
59#endif /* MLX4_DRIVER_H */
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
new file mode 100644
index 000000000000..9eeb61adf6a3
--- /dev/null
+++ b/include/linux/mlx4/qp.h
@@ -0,0 +1,288 @@
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_QP_H
34#define MLX4_QP_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39
40#define MLX4_INVALID_LKEY 0x100
41
42enum mlx4_qp_optpar {
43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
44 MLX4_QP_OPTPAR_RRE = 1 << 1,
45 MLX4_QP_OPTPAR_RAE = 1 << 2,
46 MLX4_QP_OPTPAR_RWE = 1 << 3,
47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16
58};
59
60enum mlx4_qp_state {
61 MLX4_QP_STATE_RST = 0,
62 MLX4_QP_STATE_INIT = 1,
63 MLX4_QP_STATE_RTR = 2,
64 MLX4_QP_STATE_RTS = 3,
65 MLX4_QP_STATE_SQER = 4,
66 MLX4_QP_STATE_SQD = 5,
67 MLX4_QP_STATE_ERR = 6,
68 MLX4_QP_STATE_SQ_DRAINING = 7,
69 MLX4_QP_NUM_STATE
70};
71
72enum {
73 MLX4_QP_ST_RC = 0x0,
74 MLX4_QP_ST_UC = 0x1,
75 MLX4_QP_ST_RD = 0x2,
76 MLX4_QP_ST_UD = 0x3,
77 MLX4_QP_ST_MLX = 0x7
78};
79
80enum {
81 MLX4_QP_PM_MIGRATED = 0x3,
82 MLX4_QP_PM_ARMED = 0x0,
83 MLX4_QP_PM_REARM = 0x1
84};
85
86enum {
87 /* params1 */
88 MLX4_QP_BIT_SRE = 1 << 15,
89 MLX4_QP_BIT_SWE = 1 << 14,
90 MLX4_QP_BIT_SAE = 1 << 13,
91 /* params2 */
92 MLX4_QP_BIT_RRE = 1 << 15,
93 MLX4_QP_BIT_RWE = 1 << 14,
94 MLX4_QP_BIT_RAE = 1 << 13,
95 MLX4_QP_BIT_RIC = 1 << 4,
96};
97
98struct mlx4_qp_path {
99 u8 fl;
100 u8 reserved1[2];
101 u8 pkey_index;
102 u8 reserved2;
103 u8 grh_mylmc;
104 __be16 rlid;
105 u8 ackto;
106 u8 mgid_index;
107 u8 static_rate;
108 u8 hop_limit;
109 __be32 tclass_flowlabel;
110 u8 rgid[16];
111 u8 sched_queue;
112 u8 snooper_flags;
113 u8 reserved3[2];
114 u8 counter_index;
115 u8 reserved4[7];
116};
117
118struct mlx4_qp_context {
119 __be32 flags;
120 __be32 pd;
121 u8 mtu_msgmax;
122 u8 rq_size_stride;
123 u8 sq_size_stride;
124 u8 rlkey;
125 __be32 usr_page;
126 __be32 local_qpn;
127 __be32 remote_qpn;
128 struct mlx4_qp_path pri_path;
129 struct mlx4_qp_path alt_path;
130 __be32 params1;
131 u32 reserved1;
132 __be32 next_send_psn;
133 __be32 cqn_send;
134 u32 reserved2[2];
135 __be32 last_acked_psn;
136 __be32 ssn;
137 __be32 params2;
138 __be32 rnr_nextrecvpsn;
139 __be32 srcd;
140 __be32 cqn_recv;
141 __be64 db_rec_addr;
142 __be32 qkey;
143 __be32 srqn;
144 __be32 msn;
145 __be16 rq_wqe_counter;
146 __be16 sq_wqe_counter;
147 u32 reserved3[2];
148 __be32 param3;
149 __be32 nummmcpeers_basemkey;
150 u8 log_page_size;
151 u8 reserved4[2];
152 u8 mtt_base_addr_h;
153 __be32 mtt_base_addr_l;
154 u32 reserved5[10];
155};
156
157enum {
158 MLX4_WQE_CTRL_FENCE = 1 << 6,
159 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
160 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
161};
162
163struct mlx4_wqe_ctrl_seg {
164 __be32 owner_opcode;
165 u8 reserved2[3];
166 u8 fence_size;
167 /*
168 * High 24 bits are SRC remote buffer; low 8 bits are flags:
169 * [7] SO (strong ordering)
170 * [5] TCP/UDP checksum
171 * [4] IP checksum
172 * [3:2] C (generate completion queue entry)
173 * [1] SE (solicited event)
174 */
175 __be32 srcrb_flags;
176 /*
177 * imm is immediate data for send/RDMA write w/ immediate;
178 * also invalidation key for send with invalidate; input
179 * modifier for WQEs on CCQs.
180 */
181 __be32 imm;
182};
183
184enum {
185 MLX4_WQE_MLX_VL15 = 1 << 17,
186 MLX4_WQE_MLX_SLR = 1 << 16
187};
188
189struct mlx4_wqe_mlx_seg {
190 u8 owner;
191 u8 reserved1[2];
192 u8 opcode;
193 u8 reserved2[3];
194 u8 size;
195 /*
196 * [17] VL15
197 * [16] SLR
198 * [15:12] static rate
199 * [11:8] SL
200 * [4] ICRC
201 * [3:2] C
202 * [0] FL (force loopback)
203 */
204 __be32 flags;
205 __be16 rlid;
206 u16 reserved3;
207};
208
209struct mlx4_wqe_datagram_seg {
210 __be32 av[8];
211 __be32 dqpn;
212 __be32 qkey;
213 __be32 reservd[2];
214};
215
216struct mlx4_wqe_bind_seg {
217 __be32 flags1;
218 __be32 flags2;
219 __be32 new_rkey;
220 __be32 lkey;
221 __be64 addr;
222 __be64 length;
223};
224
225struct mlx4_wqe_fmr_seg {
226 __be32 flags;
227 __be32 mem_key;
228 __be64 buf_list;
229 __be64 start_addr;
230 __be64 reg_len;
231 __be32 offset;
232 __be32 page_size;
233 u32 reserved[2];
234};
235
236struct mlx4_wqe_fmr_ext_seg {
237 u8 flags;
238 u8 reserved;
239 __be16 app_mask;
240 __be16 wire_app_tag;
241 __be16 mem_app_tag;
242 __be32 wire_ref_tag_base;
243 __be32 mem_ref_tag_base;
244};
245
246struct mlx4_wqe_local_inval_seg {
247 u8 flags;
248 u8 reserved1[3];
249 __be32 mem_key;
250 u8 reserved2[3];
251 u8 guest_id;
252 __be64 pa;
253};
254
255struct mlx4_wqe_raddr_seg {
256 __be64 raddr;
257 __be32 rkey;
258 u32 reserved;
259};
260
261struct mlx4_wqe_atomic_seg {
262 __be64 swap_add;
263 __be64 compare;
264};
265
266struct mlx4_wqe_data_seg {
267 __be32 byte_count;
268 __be32 lkey;
269 __be64 addr;
270};
271
272struct mlx4_wqe_inline_seg {
273 __be32 byte_count;
274};
275
276int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
277 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
278 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
279 int sqd_event, struct mlx4_qp *qp);
280
281static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
282{
283 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
284}
285
286void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
287
288#endif /* MLX4_QP_H */
diff --git a/include/linux/mlx4/srq.h b/include/linux/mlx4/srq.h
new file mode 100644
index 000000000000..799a0697a383
--- /dev/null
+++ b/include/linux/mlx4/srq.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_SRQ_H
34#define MLX4_SRQ_H
35
36struct mlx4_wqe_srq_next_seg {
37 u16 reserved1;
38 __be16 next_wqe_index;
39 u32 reserved2[3];
40};
41
42#endif /* MLX4_SRQ_H */
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