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-rw-r--r--include/linux/mlx4/device.h61
1 files changed, 56 insertions, 5 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 5f3a9aa7225d..e4ebff7e9d02 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -42,7 +42,7 @@
42 42
43#include <linux/atomic.h> 43#include <linux/atomic.h>
44 44
45#include <linux/clocksource.h> 45#include <linux/timecounter.h>
46 46
47#define MAX_MSIX_P_PORT 17 47#define MAX_MSIX_P_PORT 17
48#define MAX_MSIX 64 48#define MAX_MSIX 64
@@ -70,6 +70,7 @@ enum {
70 MLX4_FLAG_SLAVE = 1 << 3, 70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4, 71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6, 72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 MLX4_FLAG_BONDED = 1 << 7
73}; 74};
74 75
75enum { 76enum {
@@ -200,7 +201,9 @@ enum {
200 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16, 201 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
201 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17, 202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
202 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, 203 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
203 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19 204 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
205 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
206 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
204}; 207};
205 208
206enum { 209enum {
@@ -208,6 +211,10 @@ enum {
208 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1 211 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
209}; 212};
210 213
214enum {
215 MLX4_VF_CAP_FLAG_RESET = 1 << 0
216};
217
211/* bit enums for an 8-bit flags field indicating special use 218/* bit enums for an 8-bit flags field indicating special use
212 * QPs which require special handling in qp_reserve_range. 219 * QPs which require special handling in qp_reserve_range.
213 * Currently, this only includes QPs used by the ETH interface, 220 * Currently, this only includes QPs used by the ETH interface,
@@ -248,9 +255,14 @@ enum {
248 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 255 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
249 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 256 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
250 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 257 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
258 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
251 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, 259 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
252}; 260};
253 261
262enum {
263 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
264};
265
254enum mlx4_event { 266enum mlx4_event {
255 MLX4_EVENT_TYPE_COMP = 0x00, 267 MLX4_EVENT_TYPE_COMP = 0x00,
256 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 268 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
@@ -276,6 +288,7 @@ enum mlx4_event {
276 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, 288 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
277 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, 289 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
278 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, 290 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
291 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
279 MLX4_EVENT_TYPE_NONE = 0xff, 292 MLX4_EVENT_TYPE_NONE = 0xff,
280}; 293};
281 294
@@ -285,6 +298,11 @@ enum {
285}; 298};
286 299
287enum { 300enum {
301 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
302 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
303};
304
305enum {
288 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, 306 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
289}; 307};
290 308
@@ -411,6 +429,16 @@ enum {
411 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, 429 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
412}; 430};
413 431
432enum {
433 MLX4_DEVICE_STATE_UP = 1 << 0,
434 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
435};
436
437enum {
438 MLX4_INTERFACE_STATE_UP = 1 << 0,
439 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
440};
441
414#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ 442#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
415 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) 443 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
416 444
@@ -535,6 +563,7 @@ struct mlx4_caps {
535 u8 alloc_res_qp_mask; 563 u8 alloc_res_qp_mask;
536 u32 dmfs_high_rate_qpn_base; 564 u32 dmfs_high_rate_qpn_base;
537 u32 dmfs_high_rate_qpn_range; 565 u32 dmfs_high_rate_qpn_range;
566 u32 vf_caps;
538}; 567};
539 568
540struct mlx4_buf_list { 569struct mlx4_buf_list {
@@ -660,6 +689,8 @@ struct mlx4_cq {
660 void (*comp)(struct mlx4_cq *); 689 void (*comp)(struct mlx4_cq *);
661 void *priv; 690 void *priv;
662 } tasklet_ctx; 691 } tasklet_ctx;
692 int reset_notify_added;
693 struct list_head reset_notify;
663}; 694};
664 695
665struct mlx4_qp { 696struct mlx4_qp {
@@ -744,8 +775,23 @@ struct mlx4_vf_dev {
744 u8 n_ports; 775 u8 n_ports;
745}; 776};
746 777
747struct mlx4_dev { 778struct mlx4_dev_persistent {
748 struct pci_dev *pdev; 779 struct pci_dev *pdev;
780 struct mlx4_dev *dev;
781 int nvfs[MLX4_MAX_PORTS + 1];
782 int num_vfs;
783 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
784 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
785 struct work_struct catas_work;
786 struct workqueue_struct *catas_wq;
787 struct mutex device_state_mutex; /* protect HW state */
788 u8 state;
789 struct mutex interface_state_mutex; /* protect SW state */
790 u8 interface_state;
791};
792
793struct mlx4_dev {
794 struct mlx4_dev_persistent *persist;
749 unsigned long flags; 795 unsigned long flags;
750 unsigned long num_slaves; 796 unsigned long num_slaves;
751 struct mlx4_caps caps; 797 struct mlx4_caps caps;
@@ -754,13 +800,11 @@ struct mlx4_dev {
754 struct radix_tree_root qp_table_tree; 800 struct radix_tree_root qp_table_tree;
755 u8 rev_id; 801 u8 rev_id;
756 char board_id[MLX4_BOARD_ID_LEN]; 802 char board_id[MLX4_BOARD_ID_LEN];
757 int num_vfs;
758 int numa_node; 803 int numa_node;
759 int oper_log_mgm_entry_size; 804 int oper_log_mgm_entry_size;
760 u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; 805 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
761 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; 806 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
762 struct mlx4_vf_dev *dev_vfs; 807 struct mlx4_vf_dev *dev_vfs;
763 int nvfs[MLX4_MAX_PORTS + 1];
764}; 808};
765 809
766struct mlx4_eqe { 810struct mlx4_eqe {
@@ -832,6 +876,11 @@ struct mlx4_eqe {
832 } __packed tbl_change_info; 876 } __packed tbl_change_info;
833 } params; 877 } params;
834 } __packed port_mgmt_change; 878 } __packed port_mgmt_change;
879 struct {
880 u8 reserved[3];
881 u8 port;
882 u32 reserved1[5];
883 } __packed bad_cable;
835 } event; 884 } event;
836 u8 slave_id; 885 u8 slave_id;
837 u8 reserved3[2]; 886 u8 reserved3[2];
@@ -1338,6 +1387,8 @@ int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1338int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); 1387int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1339 1388
1340int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); 1389int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1390int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1391int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1341int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); 1392int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1342int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); 1393int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1343int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, 1394int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,