17 files changed, 1569 insertions, 245 deletions

diff --git a/include/linux/mfd/88pm8607.h b/include/linux/mfd/88pm8607.h
new file mode 100644
index 000000000000..f41b428d2cec
--- /dev/null
+++ b/include/linux/mfd/88pm8607.h
@@ -0,0 +1,217 @@
+/*
+ * Marvell 88PM8607 Interface
+ *
+ * Copyright (C) 2009 Marvell International Ltd.
+ *      Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MFD_88PM8607_H
+#define __LINUX_MFD_88PM8607_H
+
+enum {
+        PM8607_ID_BUCK1 = 0,
+        PM8607_ID_BUCK2,
+        PM8607_ID_BUCK3,
+
+        PM8607_ID_LDO1,
+        PM8607_ID_LDO2,
+        PM8607_ID_LDO3,
+        PM8607_ID_LDO4,
+        PM8607_ID_LDO5,
+        PM8607_ID_LDO6,
+        PM8607_ID_LDO7,
+        PM8607_ID_LDO8,
+        PM8607_ID_LDO9,
+        PM8607_ID_LDO10,
+        PM8607_ID_LDO12,
+        PM8607_ID_LDO14,
+
+        PM8607_ID_RG_MAX,
+};
+
+#define CHIP_ID                         (0x40)
+#define CHIP_ID_MASK                    (0xF8)
+
+/* Interrupt Registers */
+#define PM8607_STATUS_1                 (0x01)
+#define PM8607_STATUS_2                 (0x02)
+#define PM8607_INT_STATUS1              (0x03)
+#define PM8607_INT_STATUS2              (0x04)
+#define PM8607_INT_STATUS3              (0x05)
+#define PM8607_INT_MASK_1               (0x06)
+#define PM8607_INT_MASK_2               (0x07)
+#define PM8607_INT_MASK_3               (0x08)
+
+/* Regulator Control Registers */
+#define PM8607_LDO1                     (0x10)
+#define PM8607_LDO2                     (0x11)
+#define PM8607_LDO3                     (0x12)
+#define PM8607_LDO4                     (0x13)
+#define PM8607_LDO5                     (0x14)
+#define PM8607_LDO6                     (0x15)
+#define PM8607_LDO7                     (0x16)
+#define PM8607_LDO8                     (0x17)
+#define PM8607_LDO9                     (0x18)
+#define PM8607_LDO10                    (0x19)
+#define PM8607_LDO12                    (0x1A)
+#define PM8607_LDO14                    (0x1B)
+#define PM8607_SLEEP_MODE1              (0x1C)
+#define PM8607_SLEEP_MODE2              (0x1D)
+#define PM8607_SLEEP_MODE3              (0x1E)
+#define PM8607_SLEEP_MODE4              (0x1F)
+#define PM8607_GO                       (0x20)
+#define PM8607_SLEEP_BUCK1              (0x21)
+#define PM8607_SLEEP_BUCK2              (0x22)
+#define PM8607_SLEEP_BUCK3              (0x23)
+#define PM8607_BUCK1                    (0x24)
+#define PM8607_BUCK2                    (0x25)
+#define PM8607_BUCK3                    (0x26)
+#define PM8607_BUCK_CONTROLS            (0x27)
+#define PM8607_SUPPLIES_EN11            (0x2B)
+#define PM8607_SUPPLIES_EN12            (0x2C)
+#define PM8607_GROUP1                   (0x2D)
+#define PM8607_GROUP2                   (0x2E)
+#define PM8607_GROUP3                   (0x2F)
+#define PM8607_GROUP4                   (0x30)
+#define PM8607_GROUP5                   (0x31)
+#define PM8607_GROUP6                   (0x32)
+#define PM8607_SUPPLIES_EN21            (0x33)
+#define PM8607_SUPPLIES_EN22            (0x34)
+
+/* RTC Control Registers */
+#define PM8607_RTC1                     (0xA0)
+#define PM8607_RTC_COUNTER1             (0xA1)
+#define PM8607_RTC_COUNTER2             (0xA2)
+#define PM8607_RTC_COUNTER3             (0xA3)
+#define PM8607_RTC_COUNTER4             (0xA4)
+#define PM8607_RTC_EXPIRE1              (0xA5)
+#define PM8607_RTC_EXPIRE2              (0xA6)
+#define PM8607_RTC_EXPIRE3              (0xA7)
+#define PM8607_RTC_EXPIRE4              (0xA8)
+#define PM8607_RTC_TRIM1                (0xA9)
+#define PM8607_RTC_TRIM2                (0xAA)
+#define PM8607_RTC_TRIM3                (0xAB)
+#define PM8607_RTC_TRIM4                (0xAC)
+#define PM8607_RTC_MISC1                (0xAD)
+#define PM8607_RTC_MISC2                (0xAE)
+#define PM8607_RTC_MISC3                (0xAF)
+
+/* Misc Registers */
+#define PM8607_CHIP_ID                  (0x00)
+#define PM8607_LDO1                     (0x10)
+#define PM8607_DVC3                     (0x26)
+#define PM8607_MISC1                    (0x40)
+
+/* bit definitions for PM8607 events */
+#define PM8607_EVENT_ONKEY              (1 << 0)
+#define PM8607_EVENT_EXTON              (1 << 1)
+#define PM8607_EVENT_CHG                (1 << 2)
+#define PM8607_EVENT_BAT                (1 << 3)
+#define PM8607_EVENT_RTC                (1 << 4)
+#define PM8607_EVENT_CC                 (1 << 5)
+#define PM8607_EVENT_VBAT               (1 << 8)
+#define PM8607_EVENT_VCHG               (1 << 9)
+#define PM8607_EVENT_VSYS               (1 << 10)
+#define PM8607_EVENT_TINT               (1 << 11)
+#define PM8607_EVENT_GPADC0             (1 << 12)
+#define PM8607_EVENT_GPADC1             (1 << 13)
+#define PM8607_EVENT_GPADC2             (1 << 14)
+#define PM8607_EVENT_GPADC3             (1 << 15)
+#define PM8607_EVENT_AUDIO_SHORT        (1 << 16)
+#define PM8607_EVENT_PEN                (1 << 17)
+#define PM8607_EVENT_HEADSET            (1 << 18)
+#define PM8607_EVENT_HOOK               (1 << 19)
+#define PM8607_EVENT_MICIN              (1 << 20)
+#define PM8607_EVENT_CHG_TIMEOUT        (1 << 21)
+#define PM8607_EVENT_CHG_DONE           (1 << 22)
+#define PM8607_EVENT_CHG_FAULT          (1 << 23)
+
+/* bit definitions of Status Query Interface */
+#define PM8607_STATUS_CC                (1 << 3)
+#define PM8607_STATUS_PEN               (1 << 4)
+#define PM8607_STATUS_HEADSET           (1 << 5)
+#define PM8607_STATUS_HOOK              (1 << 6)
+#define PM8607_STATUS_MICIN             (1 << 7)
+#define PM8607_STATUS_ONKEY             (1 << 8)
+#define PM8607_STATUS_EXTON             (1 << 9)
+#define PM8607_STATUS_CHG               (1 << 10)
+#define PM8607_STATUS_BAT               (1 << 11)
+#define PM8607_STATUS_VBUS              (1 << 12)
+#define PM8607_STATUS_OV                (1 << 13)
+
+/* bit definitions of BUCK3 */
+#define PM8607_BUCK3_DOUBLE             (1 << 6)
+
+/* bit definitions of Misc1 */
+#define PM8607_MISC1_PI2C               (1 << 0)
+
+/* Interrupt Number in 88PM8607 */
+enum {
+        PM8607_IRQ_ONKEY = 0,
+        PM8607_IRQ_EXTON,
+        PM8607_IRQ_CHG,
+        PM8607_IRQ_BAT,
+        PM8607_IRQ_RTC,
+        PM8607_IRQ_VBAT = 8,
+        PM8607_IRQ_VCHG,
+        PM8607_IRQ_VSYS,
+        PM8607_IRQ_TINT,
+        PM8607_IRQ_GPADC0,
+        PM8607_IRQ_GPADC1,
+        PM8607_IRQ_GPADC2,
+        PM8607_IRQ_GPADC3,
+        PM8607_IRQ_AUDIO_SHORT = 16,
+        PM8607_IRQ_PEN,
+        PM8607_IRQ_HEADSET,
+        PM8607_IRQ_HOOK,
+        PM8607_IRQ_MICIN,
+        PM8607_IRQ_CHG_FAIL,
+        PM8607_IRQ_CHG_DONE,
+        PM8607_IRQ_CHG_FAULT,
+};
+
+enum {
+        PM8607_CHIP_A0 = 0x40,
+        PM8607_CHIP_A1 = 0x41,
+        PM8607_CHIP_B0 = 0x48,
+};
+
+
+struct pm8607_chip {
+        struct device           *dev;
+        struct mutex            io_lock;
+        struct i2c_client       *client;
+
+        int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest);
+        int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src);
+
+        int                     buck3_double;   /* DVC ramp slope double */
+        unsigned char           chip_id;
+
+};
+
+#define PM8607_MAX_REGULATOR    15      /* 3 Bucks, 12 LDOs */
+
+enum {
+        GI2C_PORT = 0,
+        PI2C_PORT,
+};
+
+struct pm8607_platform_data {
+        int     i2c_port;       /* Controlled by GI2C or PI2C */
+        struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
+};
+
+extern int pm8607_reg_read(struct pm8607_chip *, int);
+extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char);
+extern int pm8607_bulk_read(struct pm8607_chip *, int, int,
+                            unsigned char *);
+extern int pm8607_bulk_write(struct pm8607_chip *, int, int,
+                             unsigned char *);
+extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char,
+                           unsigned char);
+#endif /* __LINUX_MFD_88PM8607_H */
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
new file mode 100644
index 000000000000..a42a7033ae53
--- /dev/null
+++ b/include/linux/mfd/ab4500.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ * AB4500 device core funtions, for client access
+ */
+#ifndef MFD_AB4500_H
+#define MFD_AB4500_H
+
+#include <linux/device.h>
+
+/*
+ * AB4500 bank addresses
+ */
+#define AB4500_SYS_CTRL1_BLOCK  0x1
+#define AB4500_SYS_CTRL2_BLOCK  0x2
+#define AB4500_REGU_CTRL1       0x3
+#define AB4500_REGU_CTRL2       0x4
+#define AB4500_USB              0x5
+#define AB4500_TVOUT            0x6
+#define AB4500_DBI              0x7
+#define AB4500_ECI_AV_ACC       0x8
+#define AB4500_RESERVED         0x9
+#define AB4500_GPADC            0xA
+#define AB4500_CHARGER          0xB
+#define AB4500_GAS_GAUGE        0xC
+#define AB4500_AUDIO            0xD
+#define AB4500_INTERRUPT        0xE
+#define AB4500_RTC              0xF
+#define AB4500_MISC             0x10
+#define AB4500_DEBUG            0x12
+#define AB4500_PROD_TEST        0x13
+#define AB4500_OTP_EMUL         0x15
+
+/*
+ * System control 1 register offsets.
+ * Bank = 0x01
+ */
+#define AB4500_TURNON_STAT_REG          0x0100
+#define AB4500_RESET_STAT_REG           0x0101
+#define AB4500_PONKEY1_PRESS_STAT_REG   0x0102
+
+#define AB4500_FSM_STAT1_REG            0x0140
+#define AB4500_FSM_STAT2_REG            0x0141
+#define AB4500_SYSCLK_REQ_STAT_REG      0x0142
+#define AB4500_USB_STAT1_REG            0x0143
+#define AB4500_USB_STAT2_REG            0x0144
+#define AB4500_STATUS_SPARE1_REG        0x0145
+#define AB4500_STATUS_SPARE2_REG        0x0146
+
+#define AB4500_CTRL1_REG                0x0180
+#define AB4500_CTRL2_REG                0x0181
+
+/*
+ * System control 2 register offsets.
+ * bank = 0x02
+ */
+#define AB4500_CTRL3_REG                0x0200
+#define AB4500_MAIN_WDOG_CTRL_REG       0x0201
+#define AB4500_MAIN_WDOG_TIMER_REG      0x0202
+#define AB4500_LOW_BAT_REG              0x0203
+#define AB4500_BATT_OK_REG              0x0204
+#define AB4500_SYSCLK_TIMER_REG         0x0205
+#define AB4500_SMPSCLK_CTRL_REG         0x0206
+#define AB4500_SMPSCLK_SEL1_REG         0x0207
+#define AB4500_SMPSCLK_SEL2_REG         0x0208
+#define AB4500_SMPSCLK_SEL3_REG         0x0209
+#define AB4500_SYSULPCLK_CONF_REG       0x020A
+#define AB4500_SYSULPCLK_CTRL1_REG      0x020B
+#define AB4500_SYSCLK_CTRL_REG          0x020C
+#define AB4500_SYSCLK_REQ1_VALID_REG    0x020D
+#define AB4500_SYSCLK_REQ_VALID_REG     0x020E
+#define AB4500_SYSCTRL_SPARE_REG        0x020F
+#define AB4500_PAD_CONF_REG             0x0210
+
+/*
+ * Regu control1 register offsets
+ * Bank = 0x03
+ */
+#define AB4500_REGU_SERIAL_CTRL1_REG    0x0300
+#define AB4500_REGU_SERIAL_CTRL2_REG    0x0301
+#define AB4500_REGU_SERIAL_CTRL3_REG    0x0302
+#define AB4500_REGU_REQ_CTRL1_REG       0x0303
+#define AB4500_REGU_REQ_CTRL2_REG       0x0304
+#define AB4500_REGU_REQ_CTRL3_REG       0x0305
+#define AB4500_REGU_REQ_CTRL4_REG       0x0306
+#define AB4500_REGU_MISC1_REG           0x0380
+#define AB4500_REGU_OTGSUPPLY_CTRL_REG  0x0381
+#define AB4500_REGU_VUSB_CTRL_REG       0x0382
+#define AB4500_REGU_VAUDIO_SUPPLY_REG   0x0383
+#define AB4500_REGU_CTRL1_SPARE_REG     0x0384
+
+/*
+ * Regu control2 Vmod register offsets
+ */
+#define AB4500_REGU_VMOD_REGU_REG       0x0440
+#define AB4500_REGU_VMOD_SEL1_REG       0x0441
+#define AB4500_REGU_VMOD_SEL2_REG       0x0442
+#define AB4500_REGU_CTRL_DISCH_REG      0x0443
+#define AB4500_REGU_CTRL_DISCH2_REG     0x0444
+
+/*
+ * USB/ULPI register offsets
+ * Bank : 0x5
+ */
+#define AB4500_USB_LINE_STAT_REG        0x0580
+#define AB4500_USB_LINE_CTRL1_REG       0x0581
+#define AB4500_USB_LINE_CTRL2_REG       0x0582
+#define AB4500_USB_LINE_CTRL3_REG       0x0583
+#define AB4500_USB_LINE_CTRL4_REG       0x0584
+#define AB4500_USB_LINE_CTRL5_REG       0x0585
+#define AB4500_USB_OTG_CTRL_REG         0x0587
+#define AB4500_USB_OTG_STAT_REG         0x0588
+#define AB4500_USB_OTG_STAT_REG         0x0588
+#define AB4500_USB_CTRL_SPARE_REG       0x0589
+#define AB4500_USB_PHY_CTRL_REG         0x058A
+
+/*
+ * TVOUT / CTRL register offsets
+ * Bank : 0x06
+ */
+#define AB4500_TVOUT_CTRL_REG           0x0680
+
+/*
+ * DBI register offsets
+ * Bank : 0x07
+ */
+#define AB4500_DBI_REG1_REG             0x0700
+#define AB4500_DBI_REG2_REG             0x0701
+
+/*
+ * ECI regsiter offsets
+ * Bank : 0x08
+ */
+#define AB4500_ECI_CTRL_REG             0x0800
+#define AB4500_ECI_HOOKLEVEL_REG        0x0801
+#define AB4500_ECI_DATAOUT_REG          0x0802
+#define AB4500_ECI_DATAIN_REG           0x0803
+
+/*
+ * AV Connector register offsets
+ * Bank : 0x08
+ */
+#define AB4500_AV_CONN_REG              0x0840
+
+/*
+ * Accessory detection register offsets
+ * Bank : 0x08
+ */
+#define AB4500_ACC_DET_DB1_REG          0x0880
+#define AB4500_ACC_DET_DB2_REG          0x0881
+
+/*
+ * GPADC register offsets
+ * Bank : 0x0A
+ */
+#define AB4500_GPADC_CTRL1_REG          0x0A00
+#define AB4500_GPADC_CTRL2_REG          0x0A01
+#define AB4500_GPADC_CTRL3_REG          0x0A02
+#define AB4500_GPADC_AUTO_TIMER_REG     0x0A03
+#define AB4500_GPADC_STAT_REG           0x0A04
+#define AB4500_GPADC_MANDATAL_REG       0x0A05
+#define AB4500_GPADC_MANDATAH_REG       0x0A06
+#define AB4500_GPADC_AUTODATAL_REG      0x0A07
+#define AB4500_GPADC_AUTODATAH_REG      0x0A08
+#define AB4500_GPADC_MUX_CTRL_REG       0x0A09
+
+/*
+ * Charger / status register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_CH_STATUS1_REG           0x0B00
+#define AB4500_CH_STATUS2_REG           0x0B01
+#define AB4500_CH_USBCH_STAT1_REG       0x0B02
+#define AB4500_CH_USBCH_STAT2_REG       0x0B03
+#define AB4500_CH_FSM_STAT_REG          0x0B04
+#define AB4500_CH_STAT_REG              0x0B05
+
+/*
+ * Charger / control register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_CH_VOLT_LVL_REG          0x0B40
+
+/*
+ * Charger / main control register offfsets
+ * Bank : 0x0B
+ */
+#define AB4500_MCH_CTRL1                0x0B80
+#define AB4500_MCH_CTRL2                0x0B81
+#define AB4500_MCH_IPT_CURLVL_REG       0x0B82
+#define AB4500_CH_WD_REG                0x0B83
+
+/*
+ * Charger / USB control register offsets
+ * Bank : 0x0B
+ */
+#define AB4500_USBCH_CTRL1_REG          0x0BC0
+#define AB4500_USBCH_CTRL2_REG          0x0BC1
+#define AB4500_USBCH_IPT_CRNTLVL_REG    0x0BC2
+
+/*
+ * RTC bank register offsets
+ * Bank : 0xF
+ */
+#define AB4500_RTC_SOFF_STAT_REG        0x0F00
+#define AB4500_RTC_CC_CONF_REG          0x0F01
+#define AB4500_RTC_READ_REQ_REG         0x0F02
+#define AB4500_RTC_WATCH_TSECMID_REG    0x0F03
+#define AB4500_RTC_WATCH_TSECHI_REG     0x0F04
+#define AB4500_RTC_WATCH_TMIN_LOW_REG   0x0F05
+#define AB4500_RTC_WATCH_TMIN_MID_REG   0x0F06
+#define AB4500_RTC_WATCH_TMIN_HI_REG    0x0F07
+#define AB4500_RTC_ALRM_MIN_LOW_REG     0x0F08
+#define AB4500_RTC_ALRM_MIN_MID_REG     0x0F09
+#define AB4500_RTC_ALRM_MIN_HI_REG      0x0F0A
+#define AB4500_RTC_STAT_REG             0x0F0B
+#define AB4500_RTC_BKUP_CHG_REG         0x0F0C
+#define AB4500_RTC_FORCE_BKUP_REG       0x0F0D
+#define AB4500_RTC_CALIB_REG            0x0F0E
+#define AB4500_RTC_SWITCH_STAT_REG      0x0F0F
+
+/*
+ * PWM Out generators
+ * Bank: 0x10
+ */
+#define AB4500_PWM_OUT_CTRL1_REG        0x1060
+#define AB4500_PWM_OUT_CTRL2_REG        0x1061
+#define AB4500_PWM_OUT_CTRL3_REG        0x1062
+#define AB4500_PWM_OUT_CTRL4_REG        0x1063
+#define AB4500_PWM_OUT_CTRL5_REG        0x1064
+#define AB4500_PWM_OUT_CTRL6_REG        0x1065
+#define AB4500_PWM_OUT_CTRL7_REG        0x1066
+
+#define AB4500_I2C_PAD_CTRL_REG         0x1067
+#define AB4500_REV_REG                  0x1080
+
+/**
+ * struct ab4500
+ * @spi: spi device structure
+ * @tx_buf: transmit buffer
+ * @rx_buf: receive buffer
+ * @lock: sync primitive
+ */
+struct ab4500 {
+        struct spi_device       *spi;
+        unsigned long           tx_buf[4];
+        unsigned long           rx_buf[4];
+        struct mutex            lock;
+};
+
+int ab4500_write(struct ab4500 *ab4500, unsigned char block,
+                unsigned long addr, unsigned char data);
+int ab4500_read(struct ab4500 *ab4500, unsigned char block,
+                unsigned long addr);
+
+#endif /* MFD_AB4500_H */
diff --git a/include/linux/mfd/adp5520.h b/include/linux/mfd/adp5520.h
new file mode 100644
index 000000000000..ac37558a4673
--- /dev/null
+++ b/include/linux/mfd/adp5520.h
@@ -0,0 +1,299 @@
+/*
+ * Definitions and platform data for Analog Devices
+ * ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
+ *
+ * Copyright 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef __LINUX_MFD_ADP5520_H
+#define __LINUX_MFD_ADP5520_H
+
+#define ID_ADP5520              5520
+#define ID_ADP5501              5501
+
+/*
+ * ADP5520/ADP5501 Register Map
+ */
+
+#define ADP5520_MODE_STATUS             0x00
+#define ADP5520_INTERRUPT_ENABLE        0x01
+#define ADP5520_BL_CONTROL              0x02
+#define ADP5520_BL_TIME                 0x03
+#define ADP5520_BL_FADE                 0x04
+#define ADP5520_DAYLIGHT_MAX            0x05
+#define ADP5520_DAYLIGHT_DIM            0x06
+#define ADP5520_OFFICE_MAX              0x07
+#define ADP5520_OFFICE_DIM              0x08
+#define ADP5520_DARK_MAX                0x09
+#define ADP5520_DARK_DIM                0x0A
+#define ADP5520_BL_VALUE                0x0B
+#define ADP5520_ALS_CMPR_CFG            0x0C
+#define ADP5520_L2_TRIP                 0x0D
+#define ADP5520_L2_HYS                  0x0E
+#define ADP5520_L3_TRIP                 0x0F
+#define ADP5520_L3_HYS                  0x10
+#define ADP5520_LED_CONTROL             0x11
+#define ADP5520_LED_TIME                0x12
+#define ADP5520_LED_FADE                0x13
+#define ADP5520_LED1_CURRENT            0x14
+#define ADP5520_LED2_CURRENT            0x15
+#define ADP5520_LED3_CURRENT            0x16
+
+/*
+ * ADP5520 Register Map
+ */
+
+#define ADP5520_GPIO_CFG_1              0x17
+#define ADP5520_GPIO_CFG_2              0x18
+#define ADP5520_GPIO_IN                 0x19
+#define ADP5520_GPIO_OUT                0x1A
+#define ADP5520_GPIO_INT_EN             0x1B
+#define ADP5520_GPIO_INT_STAT           0x1C
+#define ADP5520_GPIO_INT_LVL            0x1D
+#define ADP5520_GPIO_DEBOUNCE           0x1E
+#define ADP5520_GPIO_PULLUP             0x1F
+#define ADP5520_KP_INT_STAT_1           0x20
+#define ADP5520_KP_INT_STAT_2           0x21
+#define ADP5520_KR_INT_STAT_1           0x22
+#define ADP5520_KR_INT_STAT_2           0x23
+#define ADP5520_KEY_STAT_1              0x24
+#define ADP5520_KEY_STAT_2              0x25
+
+/*
+ * MODE_STATUS bits
+ */
+
+#define ADP5520_nSTNBY          (1 << 7)
+#define ADP5520_BL_EN           (1 << 6)
+#define ADP5520_DIM_EN          (1 << 5)
+#define ADP5520_OVP_INT         (1 << 4)
+#define ADP5520_CMPR_INT        (1 << 3)
+#define ADP5520_GPI_INT         (1 << 2)
+#define ADP5520_KR_INT          (1 << 1)
+#define ADP5520_KP_INT          (1 << 0)
+
+/*
+ * INTERRUPT_ENABLE bits
+ */
+
+#define ADP5520_AUTO_LD_EN      (1 << 4)
+#define ADP5520_CMPR_IEN        (1 << 3)
+#define ADP5520_OVP_IEN         (1 << 2)
+#define ADP5520_KR_IEN          (1 << 1)
+#define ADP5520_KP_IEN          (1 << 0)
+
+/*
+ * BL_CONTROL bits
+ */
+
+#define ADP5520_BL_LVL          ((x) << 5)
+#define ADP5520_BL_LAW          ((x) << 4)
+#define ADP5520_BL_AUTO_ADJ     (1 << 3)
+#define ADP5520_OVP_EN          (1 << 2)
+#define ADP5520_FOVR            (1 << 1)
+#define ADP5520_KP_BL_EN        (1 << 0)
+
+/*
+ * ALS_CMPR_CFG bits
+ */
+
+#define ADP5520_L3_OUT          (1 << 3)
+#define ADP5520_L2_OUT          (1 << 2)
+#define ADP5520_L3_EN           (1 << 1)
+
+#define ADP5020_MAX_BRIGHTNESS  0x7F
+
+#define FADE_VAL(in, out)       ((0xF & (in)) | ((0xF & (out)) << 4))
+#define BL_CTRL_VAL(law, auto)  (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
+#define ALS_CMPR_CFG_VAL(filt, l3_en)   (((0x7 & filt) << 5) | l3_en)
+
+/*
+ * LEDs subdevice bits and masks
+ */
+
+#define ADP5520_01_MAXLEDS 3
+
+#define ADP5520_FLAG_LED_MASK           0x3
+#define ADP5520_FLAG_OFFT_SHIFT         8
+#define ADP5520_FLAG_OFFT_MASK          0x3
+
+#define ADP5520_R3_MODE         (1 << 5)
+#define ADP5520_C3_MODE         (1 << 4)
+#define ADP5520_LED_LAW         (1 << 3)
+#define ADP5520_LED3_EN         (1 << 2)
+#define ADP5520_LED2_EN         (1 << 1)
+#define ADP5520_LED1_EN         (1 << 0)
+
+/*
+ * GPIO subdevice bits and masks
+ */
+
+#define ADP5520_MAXGPIOS        8
+
+#define ADP5520_GPIO_C3         (1 << 7)        /* LED2 or GPIO7 aka C3 */
+#define ADP5520_GPIO_C2         (1 << 6)
+#define ADP5520_GPIO_C1         (1 << 5)
+#define ADP5520_GPIO_C0         (1 << 4)
+#define ADP5520_GPIO_R3         (1 << 3)        /* LED3 or GPIO3 aka R3 */
+#define ADP5520_GPIO_R2         (1 << 2)
+#define ADP5520_GPIO_R1         (1 << 1)
+#define ADP5520_GPIO_R0         (1 << 0)
+
+struct adp5520_gpio_platform_data {
+        unsigned gpio_start;
+        u8 gpio_en_mask;
+        u8 gpio_pullup_mask;
+};
+
+/*
+ * Keypad subdevice bits and masks
+ */
+
+#define ADP5520_MAXKEYS 16
+
+#define ADP5520_COL_C3          (1 << 7)        /* LED2 or GPIO7 aka C3 */
+#define ADP5520_COL_C2          (1 << 6)
+#define ADP5520_COL_C1          (1 << 5)
+#define ADP5520_COL_C0          (1 << 4)
+#define ADP5520_ROW_R3          (1 << 3)        /* LED3 or GPIO3 aka R3 */
+#define ADP5520_ROW_R2          (1 << 2)
+#define ADP5520_ROW_R1          (1 << 1)
+#define ADP5520_ROW_R0          (1 << 0)
+
+#define ADP5520_KEY(row, col) (col + row * 4)
+#define ADP5520_KEYMAPSIZE      ADP5520_MAXKEYS
+
+struct adp5520_keys_platform_data {
+        int rows_en_mask;               /* Number of rows */
+        int cols_en_mask;               /* Number of columns */
+        const unsigned short *keymap;   /* Pointer to keymap */
+        unsigned short keymapsize;      /* Keymap size */
+        unsigned repeat:1;              /* Enable key repeat */
+};
+
+
+/*
+ * LEDs subdevice platform data
+ */
+
+#define FLAG_ID_ADP5520_LED1_ADP5501_LED0       1       /* ADP5520 PIN ILED */
+#define FLAG_ID_ADP5520_LED2_ADP5501_LED1       2       /* ADP5520 PIN C3 */
+#define FLAG_ID_ADP5520_LED3_ADP5501_LED2       3       /* ADP5520 PIN R3 */
+
+#define ADP5520_LED_DIS_BLINK   (0 << ADP5520_FLAG_OFFT_SHIFT)
+#define ADP5520_LED_OFFT_600ms  (1 << ADP5520_FLAG_OFFT_SHIFT)
+#define ADP5520_LED_OFFT_800ms  (2 << ADP5520_FLAG_OFFT_SHIFT)
+#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
+
+#define ADP5520_LED_ONT_200ms   0
+#define ADP5520_LED_ONT_600ms   1
+#define ADP5520_LED_ONT_800ms   2
+#define ADP5520_LED_ONT_1200ms  3
+
+struct adp5520_leds_platform_data {
+        int num_leds;
+        struct led_info *leds;
+        u8 fade_in;             /* Backlight Fade-In Timer */
+        u8 fade_out;            /* Backlight Fade-Out Timer */
+        u8 led_on_time;
+};
+
+/*
+ * Backlight subdevice platform data
+ */
+
+#define ADP5520_FADE_T_DIS      0       /* Fade Timer Disabled */
+#define ADP5520_FADE_T_300ms    1       /* 0.3 Sec */
+#define ADP5520_FADE_T_600ms    2
+#define ADP5520_FADE_T_900ms    3
+#define ADP5520_FADE_T_1200ms   4
+#define ADP5520_FADE_T_1500ms   5
+#define ADP5520_FADE_T_1800ms   6
+#define ADP5520_FADE_T_2100ms   7
+#define ADP5520_FADE_T_2400ms   8
+#define ADP5520_FADE_T_2700ms   9
+#define ADP5520_FADE_T_3000ms   10
+#define ADP5520_FADE_T_3500ms   11
+#define ADP5520_FADE_T_4000ms   12
+#define ADP5520_FADE_T_4500ms   13
+#define ADP5520_FADE_T_5000ms   14
+#define ADP5520_FADE_T_5500ms   15      /* 5.5 Sec */
+
+#define ADP5520_BL_LAW_LINEAR   0
+#define ADP5520_BL_LAW_SQUARE   1
+#define ADP5520_BL_LAW_CUBIC1   2
+#define ADP5520_BL_LAW_CUBIC2   3
+
+#define ADP5520_BL_AMBL_FILT_80ms       0       /* Light sensor filter time */
+#define ADP5520_BL_AMBL_FILT_160ms      1
+#define ADP5520_BL_AMBL_FILT_320ms      2
+#define ADP5520_BL_AMBL_FILT_640ms      3
+#define ADP5520_BL_AMBL_FILT_1280ms     4
+#define ADP5520_BL_AMBL_FILT_2560ms     5
+#define ADP5520_BL_AMBL_FILT_5120ms     6
+#define ADP5520_BL_AMBL_FILT_10240ms    7       /* 10.24 sec */
+
+        /*
+         * Blacklight current 0..30mA
+         */
+#define ADP5520_BL_CUR_mA(I)            ((I * 127) / 30)
+
+        /*
+         * L2 comparator current 0..1000uA
+         */
+#define ADP5520_L2_COMP_CURR_uA(I)      ((I * 255) / 1000)
+
+        /*
+         * L3 comparator current 0..127uA
+         */
+#define ADP5520_L3_COMP_CURR_uA(I)      ((I * 255) / 127)
+
+struct adp5520_backlight_platform_data {
+        u8 fade_in;             /* Backlight Fade-In Timer */
+        u8 fade_out;            /* Backlight Fade-Out Timer */
+        u8 fade_led_law;        /* fade-on/fade-off transfer characteristic */
+
+        u8 en_ambl_sens;        /* 1 = enable ambient light sensor */
+        u8 abml_filt;           /* Light sensor filter time */
+        u8 l1_daylight_max;     /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l1_daylight_dim;     /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l2_office_max;       /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l2_office_dim;       /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l3_dark_max;         /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l3_dark_dim;         /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
+        u8 l2_trip;             /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
+        u8 l2_hyst;             /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
+        u8 l3_trip;             /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
+        u8 l3_hyst;             /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
+};
+
+/*
+ * MFD chip platform data
+ */
+
+struct adp5520_platform_data {
+        struct adp5520_keys_platform_data *keys;
+        struct adp5520_gpio_platform_data *gpio;
+        struct adp5520_leds_platform_data *leds;
+        struct adp5520_backlight_platform_data *backlight;
+};
+
+/*
+ * MFD chip functions
+ */
+
+extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
+extern int adp5520_write(struct device *dev, int reg, u8 val);
+extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
+extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
+
+extern int adp5520_register_notifier(struct device *dev,
+                 struct notifier_block *nb, unsigned int events);
+
+extern int adp5520_unregister_notifier(struct device *dev,
+                struct notifier_block *nb, unsigned int events);
+
+#endif /* __LINUX_MFD_ADP5520_H */
diff --git a/include/linux/mfd/da903x.h b/include/linux/mfd/da903x.h
index c63b65c94429..0aa3a1a49ee3 100644
--- a/include/linux/mfd/da903x.h
+++ b/include/linux/mfd/da903x.h
@@ -96,6 +96,10 @@ struct da9034_touch_pdata {
         int     y_inverted;
 };
 
+struct da9034_backlight_pdata {
+        int     output_current; /* output current of WLED, from 0-31 (in mA) */
+};
+
 /* DA9030 battery charger data */
 struct power_supply_info;
 
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index e5124ceea769..40c372165f3e 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -45,7 +45,7 @@ void pcap_set_ts_bits(struct pcap_chip *, u32);
 #define PCAP_CLEAR_INTERRUPT_REGISTER   0x01ffffff
 #define PCAP_MASK_ALL_INTERRUPT         0x01ffffff
 
-/* registers acessible by both pcap ports */
+/* registers accessible by both pcap ports */
 #define PCAP_REG_ISR            0x0     /* Interrupt Status */
 #define PCAP_REG_MSR            0x1     /* Interrupt Mask */
 #define PCAP_REG_PSTAT          0x2     /* Processor Status */
@@ -67,7 +67,7 @@ void pcap_set_ts_bits(struct pcap_chip *, u32);
 #define PCAP_REG_VENDOR_TEST1   0x1e
 #define PCAP_REG_VENDOR_TEST2   0x1f
 
-/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
+/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
 #define PCAP_REG_INT_SEL        0x3     /* Interrupt Select */
 #define PCAP_REG_SWCTRL         0x4     /* Switching Regulator Control */
 #define PCAP_REG_VREG1          0x5     /* Regulator Bank 1 Control */
@@ -231,9 +231,6 @@ void pcap_set_ts_bits(struct pcap_chip *, u32);
 #define PCAP_LED_4MA            1
 #define PCAP_LED_5MA            2
 #define PCAP_LED_9MA            3
-#define PCAP_LED_GPIO_VAL_MASK  0x00ffffff
-#define PCAP_LED_GPIO_EN        0x01000000
-#define PCAP_LED_GPIO_INVERT    0x02000000
 #define PCAP_LED_T_MASK         0xf
 #define PCAP_LED_C_MASK         0x3
 #define PCAP_BL_MASK            0x1f
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
index 47e698cb0f16..95cf9360553f 100644
--- a/include/linux/mfd/mc13783-private.h
+++ b/include/linux/mfd/mc13783-private.h
@@ -24,52 +24,23 @@
 
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
-#include <linux/workqueue.h>
 #include <linux/mutex.h>
-
-struct mc13783_irq {
-        void (*handler)(int, void *);
-        void *data;
-};
-
-#define MC13783_NUM_IRQ         2
-#define MC13783_IRQ_TS          0
-#define MC13783_IRQ_REGULATOR   1
-
-#define MC13783_ADC_MODE_TS             1
-#define MC13783_ADC_MODE_SINGLE_CHAN    2
-#define MC13783_ADC_MODE_MULT_CHAN      3
+#include <linux/interrupt.h>
 
 struct mc13783 {
-        int revision;
-        struct device *dev;
-        struct spi_device *spi_device;
-
-        int (*read_dev)(void *data, char reg, int count, u32 *dst);
-        int (*write_dev)(void *data, char reg, int count, const u32 *src);
-
-        struct mutex io_lock;
-        void *io_data;
+        struct spi_device *spidev;
+        struct mutex lock;
         int irq;
-        unsigned int flags;
+        int flags;
 
-        struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
-        struct work_struct work;
-        struct completion adc_done;
-        unsigned int ts_active;
-        struct mutex adc_conv_lock;
+        irq_handler_t irqhandler[MC13783_NUM_IRQ];
+        void *irqdata[MC13783_NUM_IRQ];
 
+        /* XXX these should go as platformdata to the regulator subdevice */
         struct mc13783_regulator_init_data *regulators;
         int num_regulators;
 };
 
-int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
-int mc13783_reg_write(struct mc13783 *, int, u32);
-int mc13783_set_bits(struct mc13783 *, int, u32, u32);
-int mc13783_free_irq(struct mc13783 *mc13783, int irq);
-int mc13783_register_irq(struct mc13783 *mc13783, int irq,
-                void (*handler) (int, void *), void *data);
-
 #define MC13783_REG_INTERRUPT_STATUS_0           0
 #define MC13783_REG_INTERRUPT_MASK_0             1
 #define MC13783_REG_INTERRUPT_SENSE_0            2
@@ -136,55 +107,6 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
 #define MC13783_REG_TEST_3                      63
 #define MC13783_REG_NB                          64
 
-
-/*
- * Interrupt Status
- */
-#define MC13783_INT_STAT_ADCDONEI       (1 << 0)
-#define MC13783_INT_STAT_ADCBISDONEI    (1 << 1)
-#define MC13783_INT_STAT_TSI            (1 << 2)
-#define MC13783_INT_STAT_WHIGHI         (1 << 3)
-#define MC13783_INT_STAT_WLOWI          (1 << 4)
-#define MC13783_INT_STAT_CHGDETI        (1 << 6)
-#define MC13783_INT_STAT_CHGOVI         (1 << 7)
-#define MC13783_INT_STAT_CHGREVI        (1 << 8)
-#define MC13783_INT_STAT_CHGSHORTI      (1 << 9)
-#define MC13783_INT_STAT_CCCVI          (1 << 10)
-#define MC13783_INT_STAT_CHGCURRI       (1 << 11)
-#define MC13783_INT_STAT_BPONI          (1 << 12)
-#define MC13783_INT_STAT_LOBATLI        (1 << 13)
-#define MC13783_INT_STAT_LOBATHI        (1 << 14)
-#define MC13783_INT_STAT_UDPI           (1 << 15)
-#define MC13783_INT_STAT_USBI           (1 << 16)
-#define MC13783_INT_STAT_IDI            (1 << 19)
-#define MC13783_INT_STAT_Unused         (1 << 20)
-#define MC13783_INT_STAT_SE1I           (1 << 21)
-#define MC13783_INT_STAT_CKDETI         (1 << 22)
-#define MC13783_INT_STAT_UDMI           (1 << 23)
-
-/*
- * Interrupt Mask
- */
-#define MC13783_INT_MASK_ADCDONEM       (1 << 0)
-#define MC13783_INT_MASK_ADCBISDONEM    (1 << 1)
-#define MC13783_INT_MASK_TSM            (1 << 2)
-#define MC13783_INT_MASK_WHIGHM         (1 << 3)
-#define MC13783_INT_MASK_WLOWM          (1 << 4)
-#define MC13783_INT_MASK_CHGDETM        (1 << 6)
-#define MC13783_INT_MASK_CHGOVM         (1 << 7)
-#define MC13783_INT_MASK_CHGREVM        (1 << 8)
-#define MC13783_INT_MASK_CHGSHORTM      (1 << 9)
-#define MC13783_INT_MASK_CCCVM          (1 << 10)
-#define MC13783_INT_MASK_CHGCURRM       (1 << 11)
-#define MC13783_INT_MASK_BPONM          (1 << 12)
-#define MC13783_INT_MASK_LOBATLM        (1 << 13)
-#define MC13783_INT_MASK_LOBATHM        (1 << 14)
-#define MC13783_INT_MASK_UDPM           (1 << 15)
-#define MC13783_INT_MASK_USBM           (1 << 16)
-#define MC13783_INT_MASK_IDM            (1 << 19)
-#define MC13783_INT_MASK_SE1M           (1 << 21)
-#define MC13783_INT_MASK_CKDETM         (1 << 22)
-
 /*
  * Reg Regulator Mode 0
  */
@@ -284,113 +206,15 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
 #define MC13783_SWCTRL_SW3_STBY         (1 << 21)
 #define MC13783_SWCTRL_SW3_MODE         (1 << 22)
 
-/*
- * ADC/Touch
- */
-#define MC13783_ADC0_LICELLCON          (1 << 0)
-#define MC13783_ADC0_CHRGICON           (1 << 1)
-#define MC13783_ADC0_BATICON            (1 << 2)
-#define MC13783_ADC0_RTHEN              (1 << 3)
-#define MC13783_ADC0_DTHEN              (1 << 4)
-#define MC13783_ADC0_UIDEN              (1 << 5)
-#define MC13783_ADC0_ADOUTEN            (1 << 6)
-#define MC13783_ADC0_ADOUTPER           (1 << 7)
-#define MC13783_ADC0_ADREFEN            (1 << 10)
-#define MC13783_ADC0_ADREFMODE          (1 << 11)
-#define MC13783_ADC0_TSMOD0             (1 << 12)
-#define MC13783_ADC0_TSMOD1             (1 << 13)
-#define MC13783_ADC0_TSMOD2             (1 << 14)
-#define MC13783_ADC0_CHRGRAWDIV         (1 << 15)
-#define MC13783_ADC0_ADINC1             (1 << 16)
-#define MC13783_ADC0_ADINC2             (1 << 17)
-#define MC13783_ADC0_WCOMP              (1 << 18)
-#define MC13783_ADC0_ADCBIS0            (1 << 23)
-
-#define MC13783_ADC1_ADEN               (1 << 0)
-#define MC13783_ADC1_RAND               (1 << 1)
-#define MC13783_ADC1_ADSEL              (1 << 3)
-#define MC13783_ADC1_TRIGMASK           (1 << 4)
-#define MC13783_ADC1_ADA10              (1 << 5)
-#define MC13783_ADC1_ADA11              (1 << 6)
-#define MC13783_ADC1_ADA12              (1 << 7)
-#define MC13783_ADC1_ADA20              (1 << 8)
-#define MC13783_ADC1_ADA21              (1 << 9)
-#define MC13783_ADC1_ADA22              (1 << 10)
-#define MC13783_ADC1_ATO0               (1 << 11)
-#define MC13783_ADC1_ATO1               (1 << 12)
-#define MC13783_ADC1_ATO2               (1 << 13)
-#define MC13783_ADC1_ATO3               (1 << 14)
-#define MC13783_ADC1_ATO4               (1 << 15)
-#define MC13783_ADC1_ATO5               (1 << 16)
-#define MC13783_ADC1_ATO6               (1 << 17)
-#define MC13783_ADC1_ATO7               (1 << 18)
-#define MC13783_ADC1_ATOX               (1 << 19)
-#define MC13783_ADC1_ASC                (1 << 20)
-#define MC13783_ADC1_ADTRIGIGN          (1 << 21)
-#define MC13783_ADC1_ADONESHOT          (1 << 22)
-#define MC13783_ADC1_ADCBIS1            (1 << 23)
-
-#define MC13783_ADC1_CHAN0_SHIFT        5
-#define MC13783_ADC1_CHAN1_SHIFT        8
-
-#define MC13783_ADC2_ADD10              (1 << 2)
-#define MC13783_ADC2_ADD11              (1 << 3)
-#define MC13783_ADC2_ADD12              (1 << 4)
-#define MC13783_ADC2_ADD13              (1 << 5)
-#define MC13783_ADC2_ADD14              (1 << 6)
-#define MC13783_ADC2_ADD15              (1 << 7)
-#define MC13783_ADC2_ADD16              (1 << 8)
-#define MC13783_ADC2_ADD17              (1 << 9)
-#define MC13783_ADC2_ADD18              (1 << 10)
-#define MC13783_ADC2_ADD19              (1 << 11)
-#define MC13783_ADC2_ADD20              (1 << 14)
-#define MC13783_ADC2_ADD21              (1 << 15)
-#define MC13783_ADC2_ADD22              (1 << 16)
-#define MC13783_ADC2_ADD23              (1 << 17)
-#define MC13783_ADC2_ADD24              (1 << 18)
-#define MC13783_ADC2_ADD25              (1 << 19)
-#define MC13783_ADC2_ADD26              (1 << 20)
-#define MC13783_ADC2_ADD27              (1 << 21)
-#define MC13783_ADC2_ADD28              (1 << 22)
-#define MC13783_ADC2_ADD29              (1 << 23)
+static inline int mc13783_set_bits(struct mc13783 *mc13783, unsigned int offset,
+                u32 mask, u32 val)
+{
+        int ret;
+        mc13783_lock(mc13783);
+        ret = mc13783_reg_rmw(mc13783, offset, mask, val);
+        mc13783_unlock(mc13783);
 
-#define MC13783_ADC3_WHIGH0             (1 << 0)
-#define MC13783_ADC3_WHIGH1             (1 << 1)
-#define MC13783_ADC3_WHIGH2             (1 << 2)
-#define MC13783_ADC3_WHIGH3             (1 << 3)
-#define MC13783_ADC3_WHIGH4             (1 << 4)
-#define MC13783_ADC3_WHIGH5             (1 << 5)
-#define MC13783_ADC3_ICID0              (1 << 6)
-#define MC13783_ADC3_ICID1              (1 << 7)
-#define MC13783_ADC3_ICID2              (1 << 8)
-#define MC13783_ADC3_WLOW0              (1 << 9)
-#define MC13783_ADC3_WLOW1              (1 << 10)
-#define MC13783_ADC3_WLOW2              (1 << 11)
-#define MC13783_ADC3_WLOW3              (1 << 12)
-#define MC13783_ADC3_WLOW4              (1 << 13)
-#define MC13783_ADC3_WLOW5              (1 << 14)
-#define MC13783_ADC3_ADCBIS2            (1 << 23)
-
-#define MC13783_ADC4_ADDBIS10           (1 << 2)
-#define MC13783_ADC4_ADDBIS11           (1 << 3)
-#define MC13783_ADC4_ADDBIS12           (1 << 4)
-#define MC13783_ADC4_ADDBIS13           (1 << 5)
-#define MC13783_ADC4_ADDBIS14           (1 << 6)
-#define MC13783_ADC4_ADDBIS15           (1 << 7)
-#define MC13783_ADC4_ADDBIS16           (1 << 8)
-#define MC13783_ADC4_ADDBIS17           (1 << 9)
-#define MC13783_ADC4_ADDBIS18           (1 << 10)
-#define MC13783_ADC4_ADDBIS19           (1 << 11)
-#define MC13783_ADC4_ADDBIS20           (1 << 14)
-#define MC13783_ADC4_ADDBIS21           (1 << 15)
-#define MC13783_ADC4_ADDBIS22           (1 << 16)
-#define MC13783_ADC4_ADDBIS23           (1 << 17)
-#define MC13783_ADC4_ADDBIS24           (1 << 18)
-#define MC13783_ADC4_ADDBIS25           (1 << 19)
-#define MC13783_ADC4_ADDBIS26           (1 << 20)
-#define MC13783_ADC4_ADDBIS27           (1 << 21)
-#define MC13783_ADC4_ADDBIS28           (1 << 22)
-#define MC13783_ADC4_ADDBIS29           (1 << 23)
+        return ret;
+}
 
 #endif /* __LINUX_MFD_MC13783_PRIV_H */
-
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index b3a2a7243573..35680409b8cf 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -1,28 +1,50 @@
 /*
- * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright 2009 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
  *
- * Initial development of this code was funded by
- * Phytec Messtechnik GmbH, http://www.phytec.de
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
  */
+#ifndef __LINUX_MFD_MC13783_H
+#define __LINUX_MFD_MC13783_H
 
-#ifndef __INCLUDE_LINUX_MFD_MC13783_H
-#define __INCLUDE_LINUX_MFD_MC13783_H
+#include <linux/interrupt.h>
 
 struct mc13783;
+
+void mc13783_lock(struct mc13783 *mc13783);
+void mc13783_unlock(struct mc13783 *mc13783);
+
+int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val);
+int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val);
+int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
+                u32 mask, u32 val);
+
+int mc13783_irq_request(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev);
+int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
+                irq_handler_t handler, const char *name, void *dev);
+int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev);
+int mc13783_ackirq(struct mc13783 *mc13783, int irq);
+
+int mc13783_mask(struct mc13783 *mc13783, int irq);
+int mc13783_unmask(struct mc13783 *mc13783, int irq);
+
+#define MC13783_ADC0            43
+#define MC13783_ADC0_ADREFEN            (1 << 10)
+#define MC13783_ADC0_ADREFMODE          (1 << 11)
+#define MC13783_ADC0_TSMOD0             (1 << 12)
+#define MC13783_ADC0_TSMOD1             (1 << 13)
+#define MC13783_ADC0_TSMOD2             (1 << 14)
+#define MC13783_ADC0_ADINC1             (1 << 16)
+#define MC13783_ADC0_ADINC2             (1 << 17)
+
+#define MC13783_ADC0_TSMOD_MASK         (MC13783_ADC0_TSMOD0 | \
+                                        MC13783_ADC0_TSMOD1 | \
+                                        MC13783_ADC0_TSMOD2)
+
+/* to be cleaned up */
 struct regulator_init_data;
 
 struct mc13783_regulator_init_data {
@@ -30,23 +52,30 @@ struct mc13783_regulator_init_data {
         struct regulator_init_data *init_data;
 };
 
-struct mc13783_platform_data {
-        struct mc13783_regulator_init_data *regulators;
+struct mc13783_regulator_platform_data {
         int num_regulators;
-        unsigned int flags;
+        struct mc13783_regulator_init_data *regulators;
 };
 
-/* mc13783_platform_data flags */
+struct mc13783_platform_data {
+        int num_regulators;
+        struct mc13783_regulator_init_data *regulators;
+
 #define MC13783_USE_TOUCHSCREEN (1 << 0)
 #define MC13783_USE_CODEC       (1 << 1)
 #define MC13783_USE_ADC         (1 << 2)
 #define MC13783_USE_RTC         (1 << 3)
 #define MC13783_USE_REGULATOR   (1 << 4)
+        unsigned int flags;
+};
+
+#define MC13783_ADC_MODE_TS             1
+#define MC13783_ADC_MODE_SINGLE_CHAN    2
+#define MC13783_ADC_MODE_MULT_CHAN      3
 
 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
                 unsigned int channel, unsigned int *sample);
 
-void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
 
 #define MC13783_SW_SW1A         0
 #define MC13783_SW_SW1B         1
@@ -80,5 +109,46 @@ void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
 #define MC13783_REGU_V3         29
 #define MC13783_REGU_V4         30
 
-#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
+#define MC13783_IRQ_ADCDONE     0
+#define MC13783_IRQ_ADCBISDONE  1
+#define MC13783_IRQ_TS          2
+#define MC13783_IRQ_WHIGH       3
+#define MC13783_IRQ_WLOW        4
+#define MC13783_IRQ_CHGDET      6
+#define MC13783_IRQ_CHGOV       7
+#define MC13783_IRQ_CHGREV      8
+#define MC13783_IRQ_CHGSHORT    9
+#define MC13783_IRQ_CCCV        10
+#define MC13783_IRQ_CHGCURR     11
+#define MC13783_IRQ_BPON        12
+#define MC13783_IRQ_LOBATL      13
+#define MC13783_IRQ_LOBATH      14
+#define MC13783_IRQ_UDP         15
+#define MC13783_IRQ_USB         16
+#define MC13783_IRQ_ID          19
+#define MC13783_IRQ_SE1         21
+#define MC13783_IRQ_CKDET       22
+#define MC13783_IRQ_UDM         23
+#define MC13783_IRQ_1HZ         24
+#define MC13783_IRQ_TODA        25
+#define MC13783_IRQ_ONOFD1      27
+#define MC13783_IRQ_ONOFD2      28
+#define MC13783_IRQ_ONOFD3      29
+#define MC13783_IRQ_SYSRST      30
+#define MC13783_IRQ_RTCRST      31
+#define MC13783_IRQ_PC          32
+#define MC13783_IRQ_WARM        33
+#define MC13783_IRQ_MEMHLD      34
+#define MC13783_IRQ_PWRRDY      35
+#define MC13783_IRQ_THWARNL     36
+#define MC13783_IRQ_THWARNH     37
+#define MC13783_IRQ_CLK         38
+#define MC13783_IRQ_SEMAF       39
+#define MC13783_IRQ_MC2B        41
+#define MC13783_IRQ_HSDET       42
+#define MC13783_IRQ_HSL         43
+#define MC13783_IRQ_ALSPTH      44
+#define MC13783_IRQ_AHSSHORT    45
+#define MC13783_NUM_IRQ         46
 
+#endif /* __LINUX_MFD_MC13783_H */
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
new file mode 100644
index 000000000000..ee496708e38b
--- /dev/null
+++ b/include/linux/mfd/mcp.h
@@ -0,0 +1,69 @@
+/*
+ *  linux/drivers/mfd/mcp.h
+ *
+ *  Copyright (C) 2001 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#ifndef MCP_H
+#define MCP_H
+
+#include <mach/dma.h>
+
+struct mcp_ops;
+
+struct mcp {
+        struct module   *owner;
+        struct mcp_ops  *ops;
+        spinlock_t      lock;
+        int             use_count;
+        unsigned int    sclk_rate;
+        unsigned int    rw_timeout;
+        dma_device_t    dma_audio_rd;
+        dma_device_t    dma_audio_wr;
+        dma_device_t    dma_telco_rd;
+        dma_device_t    dma_telco_wr;
+        struct device   attached_device;
+        int             gpio_base;
+};
+
+struct mcp_ops {
+        void            (*set_telecom_divisor)(struct mcp *, unsigned int);
+        void            (*set_audio_divisor)(struct mcp *, unsigned int);
+        void            (*reg_write)(struct mcp *, unsigned int, unsigned int);
+        unsigned int    (*reg_read)(struct mcp *, unsigned int);
+        void            (*enable)(struct mcp *);
+        void            (*disable)(struct mcp *);
+};
+
+void mcp_set_telecom_divisor(struct mcp *, unsigned int);
+void mcp_set_audio_divisor(struct mcp *, unsigned int);
+void mcp_reg_write(struct mcp *, unsigned int, unsigned int);
+unsigned int mcp_reg_read(struct mcp *, unsigned int);
+void mcp_enable(struct mcp *);
+void mcp_disable(struct mcp *);
+#define mcp_get_sclk_rate(mcp)  ((mcp)->sclk_rate)
+
+struct mcp *mcp_host_alloc(struct device *, size_t);
+int mcp_host_register(struct mcp *);
+void mcp_host_unregister(struct mcp *);
+
+struct mcp_driver {
+        struct device_driver drv;
+        int (*probe)(struct mcp *);
+        void (*remove)(struct mcp *);
+        int (*suspend)(struct mcp *, pm_message_t);
+        int (*resume)(struct mcp *);
+};
+
+int mcp_driver_register(struct mcp_driver *);
+void mcp_driver_unregister(struct mcp_driver *);
+
+#define mcp_get_drvdata(mcp)    dev_get_drvdata(&(mcp)->attached_device)
+#define mcp_set_drvdata(mcp,d)  dev_set_drvdata(&(mcp)->attached_device, d)
+
+#define mcp_priv(mcp)           ((void *)((mcp)+1))
+
+#endif
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index 46df7f053c29..3398bd9aab11 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -45,10 +45,6 @@ struct pcf50633_platform_data {
         u8 resumers[5];
 };
 
-struct pcf50633_subdev_pdata {
-        struct pcf50633 *pcf;
-};
-
 struct pcf50633_irq {
         void (*handler) (int, void *);
         void *data;
@@ -222,5 +218,9 @@ enum pcf50633_reg_int5 {
 #define PCF50633_REG_LEDCTL 0x2a
 #define PCF50633_REG_LEDDIM 0x2b
 
-#endif
+static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
+{
+        return dev_get_drvdata(dev);
+}
 
+#endif
diff --git a/include/linux/mfd/sh_mobile_sdhi.h b/include/linux/mfd/sh_mobile_sdhi.h
new file mode 100644
index 000000000000..3bcd7163485c
--- /dev/null
+++ b/include/linux/mfd/sh_mobile_sdhi.h
@@ -0,0 +1,8 @@
+#ifndef __SH_MOBILE_SDHI_H__
+#define __SH_MOBILE_SDHI_H__
+
+struct sh_mobile_sdhi_info {
+        void (*set_pwr)(struct platform_device *pdev, int state);
+};
+
+#endif /* __SH_MOBILE_SDHI_H__ */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h
new file mode 100644
index 000000000000..2ec317c68e59
--- /dev/null
+++ b/include/linux/mfd/twl4030-codec.h
@@ -0,0 +1,272 @@
+/*
+ * MFD driver for twl4030 codec submodule
+ *
+ * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
+ *
+ * Copyright:   (C) 2009 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#ifndef __TWL4030_CODEC_H__
+#define __TWL4030_CODEC_H__
+
+/* Codec registers */
+#define TWL4030_REG_CODEC_MODE          0x01
+#define TWL4030_REG_OPTION              0x02
+#define TWL4030_REG_UNKNOWN             0x03
+#define TWL4030_REG_MICBIAS_CTL         0x04
+#define TWL4030_REG_ANAMICL             0x05
+#define TWL4030_REG_ANAMICR             0x06
+#define TWL4030_REG_AVADC_CTL           0x07
+#define TWL4030_REG_ADCMICSEL           0x08
+#define TWL4030_REG_DIGMIXING           0x09
+#define TWL4030_REG_ATXL1PGA            0x0A
+#define TWL4030_REG_ATXR1PGA            0x0B
+#define TWL4030_REG_AVTXL2PGA           0x0C
+#define TWL4030_REG_AVTXR2PGA           0x0D
+#define TWL4030_REG_AUDIO_IF            0x0E
+#define TWL4030_REG_VOICE_IF            0x0F
+#define TWL4030_REG_ARXR1PGA            0x10
+#define TWL4030_REG_ARXL1PGA            0x11
+#define TWL4030_REG_ARXR2PGA            0x12
+#define TWL4030_REG_ARXL2PGA            0x13
+#define TWL4030_REG_VRXPGA              0x14
+#define TWL4030_REG_VSTPGA              0x15
+#define TWL4030_REG_VRX2ARXPGA          0x16
+#define TWL4030_REG_AVDAC_CTL           0x17
+#define TWL4030_REG_ARX2VTXPGA          0x18
+#define TWL4030_REG_ARXL1_APGA_CTL      0x19
+#define TWL4030_REG_ARXR1_APGA_CTL      0x1A
+#define TWL4030_REG_ARXL2_APGA_CTL      0x1B
+#define TWL4030_REG_ARXR2_APGA_CTL      0x1C
+#define TWL4030_REG_ATX2ARXPGA          0x1D
+#define TWL4030_REG_BT_IF               0x1E
+#define TWL4030_REG_BTPGA               0x1F
+#define TWL4030_REG_BTSTPGA             0x20
+#define TWL4030_REG_EAR_CTL             0x21
+#define TWL4030_REG_HS_SEL              0x22
+#define TWL4030_REG_HS_GAIN_SET         0x23
+#define TWL4030_REG_HS_POPN_SET         0x24
+#define TWL4030_REG_PREDL_CTL           0x25
+#define TWL4030_REG_PREDR_CTL           0x26
+#define TWL4030_REG_PRECKL_CTL          0x27
+#define TWL4030_REG_PRECKR_CTL          0x28
+#define TWL4030_REG_HFL_CTL             0x29
+#define TWL4030_REG_HFR_CTL             0x2A
+#define TWL4030_REG_ALC_CTL             0x2B
+#define TWL4030_REG_ALC_SET1            0x2C
+#define TWL4030_REG_ALC_SET2            0x2D
+#define TWL4030_REG_BOOST_CTL           0x2E
+#define TWL4030_REG_SOFTVOL_CTL         0x2F
+#define TWL4030_REG_DTMF_FREQSEL        0x30
+#define TWL4030_REG_DTMF_TONEXT1H       0x31
+#define TWL4030_REG_DTMF_TONEXT1L       0x32
+#define TWL4030_REG_DTMF_TONEXT2H       0x33
+#define TWL4030_REG_DTMF_TONEXT2L       0x34
+#define TWL4030_REG_DTMF_TONOFF         0x35
+#define TWL4030_REG_DTMF_WANONOFF       0x36
+#define TWL4030_REG_I2S_RX_SCRAMBLE_H   0x37
+#define TWL4030_REG_I2S_RX_SCRAMBLE_M   0x38
+#define TWL4030_REG_I2S_RX_SCRAMBLE_L   0x39
+#define TWL4030_REG_APLL_CTL            0x3A
+#define TWL4030_REG_DTMF_CTL            0x3B
+#define TWL4030_REG_DTMF_PGA_CTL2       0x3C
+#define TWL4030_REG_DTMF_PGA_CTL1       0x3D
+#define TWL4030_REG_MISC_SET_1          0x3E
+#define TWL4030_REG_PCMBTMUX            0x3F
+#define TWL4030_REG_RX_PATH_SEL         0x43
+#define TWL4030_REG_VDL_APGA_CTL        0x44
+#define TWL4030_REG_VIBRA_CTL           0x45
+#define TWL4030_REG_VIBRA_SET           0x46
+#define TWL4030_REG_VIBRA_PWM_SET       0x47
+#define TWL4030_REG_ANAMIC_GAIN         0x48
+#define TWL4030_REG_MISC_SET_2          0x49
+
+/* Bitfield Definitions */
+
+/* TWL4030_CODEC_MODE (0x01) Fields */
+#define TWL4030_APLL_RATE               0xF0
+#define TWL4030_APLL_RATE_8000          0x00
+#define TWL4030_APLL_RATE_11025         0x10
+#define TWL4030_APLL_RATE_12000         0x20
+#define TWL4030_APLL_RATE_16000         0x40
+#define TWL4030_APLL_RATE_22050         0x50
+#define TWL4030_APLL_RATE_24000         0x60
+#define TWL4030_APLL_RATE_32000         0x80
+#define TWL4030_APLL_RATE_44100         0x90
+#define TWL4030_APLL_RATE_48000         0xA0
+#define TWL4030_APLL_RATE_96000         0xE0
+#define TWL4030_SEL_16K                 0x08
+#define TWL4030_CODECPDZ                0x02
+#define TWL4030_OPT_MODE                0x01
+#define TWL4030_OPTION_1                (1 << 0)
+#define TWL4030_OPTION_2                (0 << 0)
+
+/* TWL4030_OPTION (0x02) Fields */
+#define TWL4030_ATXL1_EN                (1 << 0)
+#define TWL4030_ATXR1_EN                (1 << 1)
+#define TWL4030_ATXL2_VTXL_EN           (1 << 2)
+#define TWL4030_ATXR2_VTXR_EN           (1 << 3)
+#define TWL4030_ARXL1_VRX_EN            (1 << 4)
+#define TWL4030_ARXR1_EN                (1 << 5)
+#define TWL4030_ARXL2_EN                (1 << 6)
+#define TWL4030_ARXR2_EN                (1 << 7)
+
+/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
+#define TWL4030_MICBIAS2_CTL            0x40
+#define TWL4030_MICBIAS1_CTL            0x20
+#define TWL4030_HSMICBIAS_EN            0x04
+#define TWL4030_MICBIAS2_EN             0x02
+#define TWL4030_MICBIAS1_EN             0x01
+
+/* ANAMICL (0x05) Fields */
+#define TWL4030_CNCL_OFFSET_START       0x80
+#define TWL4030_OFFSET_CNCL_SEL         0x60
+#define TWL4030_OFFSET_CNCL_SEL_ARX1    0x00
+#define TWL4030_OFFSET_CNCL_SEL_ARX2    0x20
+#define TWL4030_OFFSET_CNCL_SEL_VRX     0x40
+#define TWL4030_OFFSET_CNCL_SEL_ALL     0x60
+#define TWL4030_MICAMPL_EN              0x10
+#define TWL4030_CKMIC_EN                0x08
+#define TWL4030_AUXL_EN                 0x04
+#define TWL4030_HSMIC_EN                0x02
+#define TWL4030_MAINMIC_EN              0x01
+
+/* ANAMICR (0x06) Fields */
+#define TWL4030_MICAMPR_EN              0x10
+#define TWL4030_AUXR_EN                 0x04
+#define TWL4030_SUBMIC_EN               0x01
+
+/* AVADC_CTL (0x07) Fields */
+#define TWL4030_ADCL_EN                 0x08
+#define TWL4030_AVADC_CLK_PRIORITY      0x04
+#define TWL4030_ADCR_EN                 0x02
+
+/* TWL4030_REG_ADCMICSEL (0x08) Fields */
+#define TWL4030_DIGMIC1_EN              0x08
+#define TWL4030_TX2IN_SEL               0x04
+#define TWL4030_DIGMIC0_EN              0x02
+#define TWL4030_TX1IN_SEL               0x01
+
+/* AUDIO_IF (0x0E) Fields */
+#define TWL4030_AIF_SLAVE_EN            0x80
+#define TWL4030_DATA_WIDTH              0x60
+#define TWL4030_DATA_WIDTH_16S_16W      0x00
+#define TWL4030_DATA_WIDTH_32S_16W      0x40
+#define TWL4030_DATA_WIDTH_32S_24W      0x60
+#define TWL4030_AIF_FORMAT              0x18
+#define TWL4030_AIF_FORMAT_CODEC        0x00
+#define TWL4030_AIF_FORMAT_LEFT         0x08
+#define TWL4030_AIF_FORMAT_RIGHT        0x10
+#define TWL4030_AIF_FORMAT_TDM          0x18
+#define TWL4030_AIF_TRI_EN              0x04
+#define TWL4030_CLK256FS_EN             0x02
+#define TWL4030_AIF_EN                  0x01
+
+/* VOICE_IF (0x0F) Fields */
+#define TWL4030_VIF_SLAVE_EN            0x80
+#define TWL4030_VIF_DIN_EN              0x40
+#define TWL4030_VIF_DOUT_EN             0x20
+#define TWL4030_VIF_SWAP                0x10
+#define TWL4030_VIF_FORMAT              0x08
+#define TWL4030_VIF_TRI_EN              0x04
+#define TWL4030_VIF_SUB_EN              0x02
+#define TWL4030_VIF_EN                  0x01
+
+/* EAR_CTL (0x21) */
+#define TWL4030_EAR_GAIN                0x30
+
+/* HS_GAIN_SET (0x23) Fields */
+#define TWL4030_HSR_GAIN                0x0C
+#define TWL4030_HSR_GAIN_PWR_DOWN       0x00
+#define TWL4030_HSR_GAIN_PLUS_6DB       0x04
+#define TWL4030_HSR_GAIN_0DB            0x08
+#define TWL4030_HSR_GAIN_MINUS_6DB      0x0C
+#define TWL4030_HSL_GAIN                0x03
+#define TWL4030_HSL_GAIN_PWR_DOWN       0x00
+#define TWL4030_HSL_GAIN_PLUS_6DB       0x01
+#define TWL4030_HSL_GAIN_0DB            0x02
+#define TWL4030_HSL_GAIN_MINUS_6DB      0x03
+
+/* HS_POPN_SET (0x24) Fields */
+#define TWL4030_VMID_EN                 0x40
+#define TWL4030_EXTMUTE                 0x20
+#define TWL4030_RAMP_DELAY              0x1C
+#define TWL4030_RAMP_DELAY_20MS         0x00
+#define TWL4030_RAMP_DELAY_40MS         0x04
+#define TWL4030_RAMP_DELAY_81MS         0x08
+#define TWL4030_RAMP_DELAY_161MS        0x0C
+#define TWL4030_RAMP_DELAY_323MS        0x10
+#define TWL4030_RAMP_DELAY_645MS        0x14
+#define TWL4030_RAMP_DELAY_1291MS       0x18
+#define TWL4030_RAMP_DELAY_2581MS       0x1C
+#define TWL4030_RAMP_EN                 0x02
+
+/* PREDL_CTL (0x25) */
+#define TWL4030_PREDL_GAIN              0x30
+
+/* PREDR_CTL (0x26) */
+#define TWL4030_PREDR_GAIN              0x30
+
+/* PRECKL_CTL (0x27) */
+#define TWL4030_PRECKL_GAIN             0x30
+
+/* PRECKR_CTL (0x28) */
+#define TWL4030_PRECKR_GAIN             0x30
+
+/* HFL_CTL (0x29, 0x2A) Fields */
+#define TWL4030_HF_CTL_HB_EN            0x04
+#define TWL4030_HF_CTL_LOOP_EN          0x08
+#define TWL4030_HF_CTL_RAMP_EN          0x10
+#define TWL4030_HF_CTL_REF_EN           0x20
+
+/* APLL_CTL (0x3A) Fields */
+#define TWL4030_APLL_EN                 0x10
+#define TWL4030_APLL_INFREQ             0x0F
+#define TWL4030_APLL_INFREQ_19200KHZ    0x05
+#define TWL4030_APLL_INFREQ_26000KHZ    0x06
+#define TWL4030_APLL_INFREQ_38400KHZ    0x0F
+
+/* REG_MISC_SET_1 (0x3E) Fields */
+#define TWL4030_CLK64_EN                0x80
+#define TWL4030_SCRAMBLE_EN             0x40
+#define TWL4030_FMLOOP_EN               0x20
+#define TWL4030_SMOOTH_ANAVOL_EN        0x02
+#define TWL4030_DIGMIC_LR_SWAP_EN       0x01
+
+/* VIBRA_CTL (0x45) */
+#define TWL4030_VIBRA_EN                0x01
+#define TWL4030_VIBRA_DIR               0x02
+#define TWL4030_VIBRA_AUDIO_SEL_L1      (0x00 << 2)
+#define TWL4030_VIBRA_AUDIO_SEL_R1      (0x01 << 2)
+#define TWL4030_VIBRA_AUDIO_SEL_L2      (0x02 << 2)
+#define TWL4030_VIBRA_AUDIO_SEL_R2      (0x03 << 2)
+#define TWL4030_VIBRA_SEL               0x10
+#define TWL4030_VIBRA_DIR_SEL           0x20
+
+/* TWL4030 codec resource IDs */
+enum twl4030_codec_res {
+        TWL4030_CODEC_RES_POWER = 0,
+        TWL4030_CODEC_RES_APLL,
+        TWL4030_CODEC_RES_MAX,
+};
+
+int twl4030_codec_disable_resource(enum twl4030_codec_res id);
+int twl4030_codec_enable_resource(enum twl4030_codec_res id);
+unsigned int twl4030_codec_get_mclk(void);
+
+#endif  /* End of __TWL4030_CODEC_H__ */
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
new file mode 100644
index 000000000000..aa9c3789bed4
--- /dev/null
+++ b/include/linux/mfd/ucb1x00.h
@@ -0,0 +1,258 @@
+/*
+ *  linux/include/mfd/ucb1x00.h
+ *
+ *  Copyright (C) 2001 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#ifndef UCB1200_H
+#define UCB1200_H
+
+#include <linux/mfd/mcp.h>
+#include <linux/gpio.h>
+
+#define UCB_IO_DATA     0x00
+#define UCB_IO_DIR      0x01
+
+#define UCB_IO_0                (1 << 0)
+#define UCB_IO_1                (1 << 1)
+#define UCB_IO_2                (1 << 2)
+#define UCB_IO_3                (1 << 3)
+#define UCB_IO_4                (1 << 4)
+#define UCB_IO_5                (1 << 5)
+#define UCB_IO_6                (1 << 6)
+#define UCB_IO_7                (1 << 7)
+#define UCB_IO_8                (1 << 8)
+#define UCB_IO_9                (1 << 9)
+
+#define UCB_IE_RIS      0x02
+#define UCB_IE_FAL      0x03
+#define UCB_IE_STATUS   0x04
+#define UCB_IE_CLEAR    0x04
+#define UCB_IE_ADC              (1 << 11)
+#define UCB_IE_TSPX             (1 << 12)
+#define UCB_IE_TSMX             (1 << 13)
+#define UCB_IE_TCLIP            (1 << 14)
+#define UCB_IE_ACLIP            (1 << 15)
+
+#define UCB_IRQ_TSPX            12
+
+#define UCB_TC_A        0x05
+#define UCB_TC_A_LOOP           (1 << 7)        /* UCB1200 */
+#define UCB_TC_A_AMPL           (1 << 7)        /* UCB1300 */
+
+#define UCB_TC_B        0x06
+#define UCB_TC_B_VOICE_ENA      (1 << 3)
+#define UCB_TC_B_CLIP           (1 << 4)
+#define UCB_TC_B_ATT            (1 << 6)
+#define UCB_TC_B_SIDE_ENA       (1 << 11)
+#define UCB_TC_B_MUTE           (1 << 13)
+#define UCB_TC_B_IN_ENA         (1 << 14)
+#define UCB_TC_B_OUT_ENA        (1 << 15)
+
+#define UCB_AC_A        0x07
+#define UCB_AC_B        0x08
+#define UCB_AC_B_LOOP           (1 << 8)
+#define UCB_AC_B_MUTE           (1 << 13)
+#define UCB_AC_B_IN_ENA         (1 << 14)
+#define UCB_AC_B_OUT_ENA        (1 << 15)
+
+#define UCB_TS_CR       0x09
+#define UCB_TS_CR_TSMX_POW      (1 << 0)
+#define UCB_TS_CR_TSPX_POW      (1 << 1)
+#define UCB_TS_CR_TSMY_POW      (1 << 2)
+#define UCB_TS_CR_TSPY_POW      (1 << 3)
+#define UCB_TS_CR_TSMX_GND      (1 << 4)
+#define UCB_TS_CR_TSPX_GND      (1 << 5)
+#define UCB_TS_CR_TSMY_GND      (1 << 6)
+#define UCB_TS_CR_TSPY_GND      (1 << 7)
+#define UCB_TS_CR_MODE_INT      (0 << 8)
+#define UCB_TS_CR_MODE_PRES     (1 << 8)
+#define UCB_TS_CR_MODE_POS      (2 << 8)
+#define UCB_TS_CR_BIAS_ENA      (1 << 11)
+#define UCB_TS_CR_TSPX_LOW      (1 << 12)
+#define UCB_TS_CR_TSMX_LOW      (1 << 13)
+
+#define UCB_ADC_CR      0x0a
+#define UCB_ADC_SYNC_ENA        (1 << 0)
+#define UCB_ADC_VREFBYP_CON     (1 << 1)
+#define UCB_ADC_INP_TSPX        (0 << 2)
+#define UCB_ADC_INP_TSMX        (1 << 2)
+#define UCB_ADC_INP_TSPY        (2 << 2)
+#define UCB_ADC_INP_TSMY        (3 << 2)
+#define UCB_ADC_INP_AD0         (4 << 2)
+#define UCB_ADC_INP_AD1         (5 << 2)
+#define UCB_ADC_INP_AD2         (6 << 2)
+#define UCB_ADC_INP_AD3         (7 << 2)
+#define UCB_ADC_EXT_REF         (1 << 5)
+#define UCB_ADC_START           (1 << 7)
+#define UCB_ADC_ENA             (1 << 15)
+
+#define UCB_ADC_DATA    0x0b
+#define UCB_ADC_DAT_VAL         (1 << 15)
+#define UCB_ADC_DAT(x)          (((x) & 0x7fe0) >> 5)
+
+#define UCB_ID          0x0c
+#define UCB_ID_1200             0x1004
+#define UCB_ID_1300             0x1005
+#define UCB_ID_TC35143          0x9712
+
+#define UCB_MODE        0x0d
+#define UCB_MODE_DYN_VFLAG_ENA  (1 << 12)
+#define UCB_MODE_AUD_OFF_CAN    (1 << 13)
+
+
+struct ucb1x00_irq {
+        void *devid;
+        void (*fn)(int, void *);
+};
+
+struct ucb1x00 {
+        spinlock_t              lock;
+        struct mcp              *mcp;
+        unsigned int            irq;
+        struct semaphore        adc_sem;
+        spinlock_t              io_lock;
+        u16                     id;
+        u16                     io_dir;
+        u16                     io_out;
+        u16                     adc_cr;
+        u16                     irq_fal_enbl;
+        u16                     irq_ris_enbl;
+        struct ucb1x00_irq      irq_handler[16];
+        struct device           dev;
+        struct list_head        node;
+        struct list_head        devs;
+        struct gpio_chip        gpio;
+};
+
+struct ucb1x00_driver;
+
+struct ucb1x00_dev {
+        struct list_head        dev_node;
+        struct list_head        drv_node;
+        struct ucb1x00          *ucb;
+        struct ucb1x00_driver   *drv;
+        void                    *priv;
+};
+
+struct ucb1x00_driver {
+        struct list_head        node;
+        struct list_head        devs;
+        int     (*add)(struct ucb1x00_dev *dev);
+        void    (*remove)(struct ucb1x00_dev *dev);
+        int     (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
+        int     (*resume)(struct ucb1x00_dev *dev);
+};
+
+#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
+
+int ucb1x00_register_driver(struct ucb1x00_driver *);
+void ucb1x00_unregister_driver(struct ucb1x00_driver *);
+
+/**
+ *      ucb1x00_clkrate - return the UCB1x00 SIB clock rate
+ *      @ucb: UCB1x00 structure describing chip
+ *
+ *      Return the SIB clock rate in Hz.
+ */
+static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
+{
+        return mcp_get_sclk_rate(ucb->mcp);
+}
+
+/**
+ *      ucb1x00_enable - enable the UCB1x00 SIB clock
+ *      @ucb: UCB1x00 structure describing chip
+ *
+ *      Enable the SIB clock.  This can be called multiple times.
+ */
+static inline void ucb1x00_enable(struct ucb1x00 *ucb)
+{
+        mcp_enable(ucb->mcp);
+}
+
+/**
+ *      ucb1x00_disable - disable the UCB1x00 SIB clock
+ *      @ucb: UCB1x00 structure describing chip
+ *
+ *      Disable the SIB clock.  The SIB clock will only be disabled
+ *      when the number of ucb1x00_enable calls match the number of
+ *      ucb1x00_disable calls.
+ */
+static inline void ucb1x00_disable(struct ucb1x00 *ucb)
+{
+        mcp_disable(ucb->mcp);
+}
+
+/**
+ *      ucb1x00_reg_write - write a UCB1x00 register
+ *      @ucb: UCB1x00 structure describing chip
+ *      @reg: UCB1x00 4-bit register index to write
+ *      @val: UCB1x00 16-bit value to write
+ *
+ *      Write the UCB1x00 register @reg with value @val.  The SIB
+ *      clock must be running for this function to return.
+ */
+static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
+{
+        mcp_reg_write(ucb->mcp, reg, val);
+}
+
+/**
+ *      ucb1x00_reg_read - read a UCB1x00 register
+ *      @ucb: UCB1x00 structure describing chip
+ *      @reg: UCB1x00 4-bit register index to write
+ *
+ *      Read the UCB1x00 register @reg and return its value.  The SIB
+ *      clock must be running for this function to return.
+ */
+static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
+{
+        return mcp_reg_read(ucb->mcp, reg);
+}
+/**
+ *      ucb1x00_set_audio_divisor - 
+ *      @ucb: UCB1x00 structure describing chip
+ *      @div: SIB clock divisor
+ */
+static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
+{
+        mcp_set_audio_divisor(ucb->mcp, div);
+}
+
+/**
+ *      ucb1x00_set_telecom_divisor -
+ *      @ucb: UCB1x00 structure describing chip
+ *      @div: SIB clock divisor
+ */
+static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
+{
+        mcp_set_telecom_divisor(ucb->mcp, div);
+}
+
+void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
+void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
+unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
+
+#define UCB_NOSYNC      (0)
+#define UCB_SYNC        (1)
+
+unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
+void ucb1x00_adc_enable(struct ucb1x00 *ucb);
+void ucb1x00_adc_disable(struct ucb1x00 *ucb);
+
+/*
+ * Which edges of the IRQ do you want to control today?
+ */
+#define UCB_RISING      (1 << 0)
+#define UCB_FALLING     (1 << 1)
+
+int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
+void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
+void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
+int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
+
+#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 91eb493bf14c..5184b79c700b 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -16,7 +16,6 @@
 #define __MFD_WM831X_CORE_H__
 
 #include <linux/interrupt.h>
-#include <linux/workqueue.h>
 
 /*
  * Register values.
@@ -117,6 +116,7 @@
 #define WM831X_DC3_SLEEP_CONTROL                0x4063
 #define WM831X_DC4_CONTROL                      0x4064
 #define WM831X_DC4_SLEEP_CONTROL                0x4065
+#define WM832X_DC4_SLEEP_CONTROL                0x4067
 #define WM831X_EPE1_CONTROL                     0x4066
 #define WM831X_EPE2_CONTROL                     0x4067
 #define WM831X_LDO1_CONTROL                     0x4068
@@ -235,6 +235,8 @@
 
 struct regulator_dev;
 
+#define WM831X_NUM_IRQ_REGS 5
+
 struct wm831x {
         struct mutex io_lock;
 
@@ -248,10 +250,11 @@ struct wm831x {
 
         int irq;  /* Our chip IRQ */
         struct mutex irq_lock;
-        struct workqueue_struct *irq_wq;
-        struct work_struct irq_work;
         unsigned int irq_base;
-        int irq_masks[5];
+        int irq_masks_cur[WM831X_NUM_IRQ_REGS];   /* Currently active value */
+        int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
+
+        int num_gpio;
 
         struct mutex auxadc_lock;
 
@@ -278,12 +281,30 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
 int wm831x_irq_init(struct wm831x *wm831x, int irq);
 void wm831x_irq_exit(struct wm831x *wm831x);
 
-int __must_check wm831x_request_irq(struct wm831x *wm831x,
-                                    unsigned int irq, irq_handler_t handler,
-                                    unsigned long flags, const char *name,
-                                    void *dev);
-void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *);
-void wm831x_disable_irq(struct wm831x *wm831x, int irq);
-void wm831x_enable_irq(struct wm831x *wm831x, int irq);
+static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
+                                                  unsigned int irq,
+                                                  irq_handler_t handler,
+                                                  unsigned long flags,
+                                                  const char *name,
+                                                  void *dev)
+{
+        return request_threaded_irq(irq, NULL, handler, flags, name, dev);
+}
+
+static inline void wm831x_free_irq(struct wm831x *wm831x,
+                                   unsigned int irq, void *dev)
+{
+        free_irq(irq, dev);
+}
+
+static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
+{
+        disable_irq(irq);
+}
+
+static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
+{
+        enable_irq(irq);
+}
 
 #endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index 90d820260aad..415c228743d5 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -91,6 +91,7 @@ struct wm831x_pdata {
         /** Called after subdevices are set up */
         int (*post_init)(struct wm831x *wm831x);
 
+        int irq_base;
         int gpio_base;
         struct wm831x_backlight_pdata *backlight;
         struct wm831x_backup_pdata *backup;
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
index f95466343fb2..955d30fc6a27 100644
--- a/include/linux/mfd/wm831x/regulator.h
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -1212,7 +1212,7 @@
 #define WM831X_LDO1_OK_SHIFT                         0  /* LDO1_OK */
 #define WM831X_LDO1_OK_WIDTH                         1  /* LDO1_OK */
 
-#define WM831X_ISINK_MAX_ISEL 56
-extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL];
+#define WM831X_ISINK_MAX_ISEL 55
+extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1];
 
 #endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 1d595de6a055..43868899bf49 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -15,7 +15,7 @@
 
 #include <linux/kernel.h>
 #include <linux/mutex.h>
-#include <linux/workqueue.h>
+#include <linux/interrupt.h>
 
 #include <linux/mfd/wm8350/audio.h>
 #include <linux/mfd/wm8350/gpio.h>
@@ -601,7 +601,7 @@ extern const u16 wm8352_mode3_defaults[];
 struct wm8350;
 
 struct wm8350_irq {
-        void (*handler) (struct wm8350 *, int, void *);
+        irq_handler_t handler;
         void *data;
 };
 
@@ -646,10 +646,12 @@ struct wm8350 {
  * @init: Function called during driver initialisation.  Should be
  *        used by the platform to configure GPIO functions and similar.
  * @irq_high: Set if WM8350 IRQ is active high.
+ * @irq_base: Base IRQ for genirq (not currently used).
  */
 struct wm8350_platform_data {
         int (*init)(struct wm8350 *wm8350);
         int irq_high;
+        int irq_base;
 };
 
 
@@ -676,11 +678,13 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
  * WM8350 internal interrupts
  */
 int wm8350_register_irq(struct wm8350 *wm8350, int irq,
-                        void (*handler) (struct wm8350 *, int, void *),
-                        void *data);
+                        irq_handler_t handler, unsigned long flags,
+                        const char *name, void *data);
 int wm8350_free_irq(struct wm8350 *wm8350, int irq);
 int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
 int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
-
+int wm8350_irq_init(struct wm8350 *wm8350, int irq,
+                    struct wm8350_platform_data *pdata);
+int wm8350_irq_exit(struct wm8350 *wm8350);
 
 #endif
diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h
index ed91e8f5d298..71af3d6ebe9d 100644
--- a/include/linux/mfd/wm8350/gpio.h
+++ b/include/linux/mfd/wm8350/gpio.h
@@ -173,6 +173,24 @@
 #define WM8350_GPIO_DEBOUNCE_ON                 1
 
 /*
+ * R30 (0x1E) - GPIO Interrupt Status
+ */
+#define WM8350_GP12_EINT                        0x1000
+#define WM8350_GP11_EINT                        0x0800
+#define WM8350_GP10_EINT                        0x0400
+#define WM8350_GP9_EINT                         0x0200
+#define WM8350_GP8_EINT                         0x0100
+#define WM8350_GP7_EINT                         0x0080
+#define WM8350_GP6_EINT                         0x0040
+#define WM8350_GP5_EINT                         0x0020
+#define WM8350_GP4_EINT                         0x0010
+#define WM8350_GP3_EINT                         0x0008
+#define WM8350_GP2_EINT                         0x0004
+#define WM8350_GP1_EINT                         0x0002
+#define WM8350_GP0_EINT                         0x0001
+
+
+/*
  * R128 (0x80) - GPIO Debounce
  */
 #define WM8350_GP12_DB                          0x1000