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-rw-r--r--include/linux/mfd/88pm80x.h2
-rw-r--r--include/linux/mfd/abx500.h17
-rw-r--r--include/linux/mfd/abx500/ab8500-bm.h37
-rw-r--r--include/linux/mfd/abx500/ab8500-gpio.h16
-rw-r--r--include/linux/mfd/abx500/ab8500-sysctrl.h5
-rw-r--r--include/linux/mfd/abx500/ab8500.h291
-rw-r--r--include/linux/mfd/abx500/ux500_chargalg.h5
-rw-r--r--include/linux/mfd/arizona/core.h4
-rw-r--r--include/linux/mfd/arizona/pdata.h42
-rw-r--r--include/linux/mfd/arizona/registers.h72
-rw-r--r--include/linux/mfd/db8500-prcmu.h20
-rw-r--r--include/linux/mfd/dbx500-prcmu.h139
-rw-r--r--include/linux/mfd/lp8788.h24
-rw-r--r--include/linux/mfd/max77693-private.h86
-rw-r--r--include/linux/mfd/max77693.h9
-rw-r--r--include/linux/mfd/max8925.h3
-rw-r--r--include/linux/mfd/max8997-private.h64
-rw-r--r--include/linux/mfd/max8997.h25
-rw-r--r--include/linux/mfd/palmas.h52
-rw-r--r--include/linux/mfd/rtsx_pci.h9
-rw-r--r--include/linux/mfd/samsung/core.h11
-rw-r--r--include/linux/mfd/tmio.h18
22 files changed, 695 insertions, 256 deletions
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index 478672ed0c3d..e94537befabd 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -365,5 +365,5 @@ static inline int pm80x_dev_resume(struct device *dev)
365 365
366extern int pm80x_init(struct i2c_client *client, 366extern int pm80x_init(struct i2c_client *client,
367 const struct i2c_device_id *id); 367 const struct i2c_device_id *id);
368extern int pm80x_deinit(struct i2c_client *client); 368extern int pm80x_deinit(void);
369#endif /* __LINUX_MFD_88PM80X_H */ 369#endif /* __LINUX_MFD_88PM80X_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index e53dcfeaee69..9ead60bc66b7 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -131,7 +131,7 @@ struct abx500_maxim_parameters {
131 * @nominal_voltage: Nominal voltage of the battery in mV 131 * @nominal_voltage: Nominal voltage of the battery in mV
132 * @termination_vol: max voltage upto which battery can be charged 132 * @termination_vol: max voltage upto which battery can be charged
133 * @termination_curr battery charging termination current in mA 133 * @termination_curr battery charging termination current in mA
134 * @recharge_vol battery voltage limit that will trigger a new 134 * @recharge_cap battery capacity limit that will trigger a new
135 * full charging cycle in the case where maintenan- 135 * full charging cycle in the case where maintenan-
136 * -ce charging has been disabled 136 * -ce charging has been disabled
137 * @normal_cur_lvl: charger current in normal state in mA 137 * @normal_cur_lvl: charger current in normal state in mA
@@ -160,7 +160,7 @@ struct abx500_battery_type {
160 int nominal_voltage; 160 int nominal_voltage;
161 int termination_vol; 161 int termination_vol;
162 int termination_curr; 162 int termination_curr;
163 int recharge_vol; 163 int recharge_cap;
164 int normal_cur_lvl; 164 int normal_cur_lvl;
165 int normal_vol_lvl; 165 int normal_vol_lvl;
166 int maint_a_cur_lvl; 166 int maint_a_cur_lvl;
@@ -224,6 +224,7 @@ struct abx500_bm_charger_parameters {
224 * @bkup_bat_v voltage which we charge the backup battery with 224 * @bkup_bat_v voltage which we charge the backup battery with
225 * @bkup_bat_i current which we charge the backup battery with 225 * @bkup_bat_i current which we charge the backup battery with
226 * @no_maintenance indicates that maintenance charging is disabled 226 * @no_maintenance indicates that maintenance charging is disabled
227 * @capacity_scaling indicates whether capacity scaling is to be used
227 * @abx500_adc_therm placement of thermistor, batctrl or battemp adc 228 * @abx500_adc_therm placement of thermistor, batctrl or battemp adc
228 * @chg_unknown_bat flag to enable charging of unknown batteries 229 * @chg_unknown_bat flag to enable charging of unknown batteries
229 * @enable_overshoot flag to enable VBAT overshoot control 230 * @enable_overshoot flag to enable VBAT overshoot control
@@ -253,7 +254,11 @@ struct abx500_bm_data {
253 int usb_safety_tmr_h; 254 int usb_safety_tmr_h;
254 int bkup_bat_v; 255 int bkup_bat_v;
255 int bkup_bat_i; 256 int bkup_bat_i;
257 bool autopower_cfg;
258 bool ac_enabled;
259 bool usb_enabled;
256 bool no_maintenance; 260 bool no_maintenance;
261 bool capacity_scaling;
257 bool chg_unknown_bat; 262 bool chg_unknown_bat;
258 bool enable_overshoot; 263 bool enable_overshoot;
259 bool auto_trig; 264 bool auto_trig;
@@ -277,9 +282,9 @@ enum {
277 NTC_INTERNAL, 282 NTC_INTERNAL,
278}; 283};
279 284
280int bmdevs_of_probe(struct device *dev, 285int ab8500_bm_of_probe(struct device *dev,
281 struct device_node *np, 286 struct device_node *np,
282 struct abx500_bm_data **battery); 287 struct abx500_bm_data *bm);
283 288
284int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg, 289int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
285 u8 value); 290 u8 value);
@@ -306,6 +311,7 @@ int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
306int abx500_get_chip_id(struct device *dev); 311int abx500_get_chip_id(struct device *dev);
307int abx500_event_registers_startup_state_get(struct device *dev, u8 *event); 312int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
308int abx500_startup_irq_enabled(struct device *dev, unsigned int irq); 313int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
314void abx500_dump_all_banks(void);
309 315
310struct abx500_ops { 316struct abx500_ops {
311 int (*get_chip_id) (struct device *); 317 int (*get_chip_id) (struct device *);
@@ -316,6 +322,7 @@ struct abx500_ops {
316 int (*mask_and_set_register) (struct device *, u8, u8, u8, u8); 322 int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
317 int (*event_registers_startup_state_get) (struct device *, u8 *); 323 int (*event_registers_startup_state_get) (struct device *, u8 *);
318 int (*startup_irq_enabled) (struct device *, unsigned int); 324 int (*startup_irq_enabled) (struct device *, unsigned int);
325 void (*dump_all_banks) (struct device *);
319}; 326};
320 327
321int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops); 328int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
diff --git a/include/linux/mfd/abx500/ab8500-bm.h b/include/linux/mfd/abx500/ab8500-bm.h
index 9bd037df97d9..8d35bfe164c8 100644
--- a/include/linux/mfd/abx500/ab8500-bm.h
+++ b/include/linux/mfd/abx500/ab8500-bm.h
@@ -23,6 +23,7 @@
23 * Bank : 0x5 23 * Bank : 0x5
24 */ 24 */
25#define AB8500_USB_LINE_STAT_REG 0x80 25#define AB8500_USB_LINE_STAT_REG 0x80
26#define AB8500_USB_LINK1_STAT_REG 0x94
26 27
27/* 28/*
28 * Charger / status register offfsets 29 * Charger / status register offfsets
@@ -225,6 +226,8 @@
225/* BatCtrl Current Source Constants */ 226/* BatCtrl Current Source Constants */
226#define BAT_CTRL_7U_ENA 0x01 227#define BAT_CTRL_7U_ENA 0x01
227#define BAT_CTRL_20U_ENA 0x02 228#define BAT_CTRL_20U_ENA 0x02
229#define BAT_CTRL_18U_ENA 0x01
230#define BAT_CTRL_16U_ENA 0x02
228#define BAT_CTRL_CMP_ENA 0x04 231#define BAT_CTRL_CMP_ENA 0x04
229#define FORCE_BAT_CTRL_CMP_HIGH 0x08 232#define FORCE_BAT_CTRL_CMP_HIGH 0x08
230#define BAT_CTRL_PULL_UP_ENA 0x10 233#define BAT_CTRL_PULL_UP_ENA 0x10
@@ -355,6 +358,7 @@ struct ab8500_bm_charger_parameters {
355 * @bkup_bat_v voltage which we charge the backup battery with 358 * @bkup_bat_v voltage which we charge the backup battery with
356 * @bkup_bat_i current which we charge the backup battery with 359 * @bkup_bat_i current which we charge the backup battery with
357 * @no_maintenance indicates that maintenance charging is disabled 360 * @no_maintenance indicates that maintenance charging is disabled
361 * @capacity_scaling indicates whether capacity scaling is to be used
358 * @adc_therm placement of thermistor, batctrl or battemp adc 362 * @adc_therm placement of thermistor, batctrl or battemp adc
359 * @chg_unknown_bat flag to enable charging of unknown batteries 363 * @chg_unknown_bat flag to enable charging of unknown batteries
360 * @enable_overshoot flag to enable VBAT overshoot control 364 * @enable_overshoot flag to enable VBAT overshoot control
@@ -383,6 +387,7 @@ struct ab8500_bm_data {
383 int bkup_bat_v; 387 int bkup_bat_v;
384 int bkup_bat_i; 388 int bkup_bat_i;
385 bool no_maintenance; 389 bool no_maintenance;
390 bool capacity_scaling;
386 bool chg_unknown_bat; 391 bool chg_unknown_bat;
387 bool enable_overshoot; 392 bool enable_overshoot;
388 enum abx500_adc_therm adc_therm; 393 enum abx500_adc_therm adc_therm;
@@ -399,26 +404,6 @@ struct ab8500_bm_data {
399 const struct ab8500_fg_parameters *fg_params; 404 const struct ab8500_fg_parameters *fg_params;
400}; 405};
401 406
402struct ab8500_charger_platform_data {
403 char **supplied_to;
404 size_t num_supplicants;
405 bool autopower_cfg;
406};
407
408struct ab8500_btemp_platform_data {
409 char **supplied_to;
410 size_t num_supplicants;
411};
412
413struct ab8500_fg_platform_data {
414 char **supplied_to;
415 size_t num_supplicants;
416};
417
418struct ab8500_chargalg_platform_data {
419 char **supplied_to;
420 size_t num_supplicants;
421};
422struct ab8500_btemp; 407struct ab8500_btemp;
423struct ab8500_gpadc; 408struct ab8500_gpadc;
424struct ab8500_fg; 409struct ab8500_fg;
@@ -434,20 +419,10 @@ struct ab8500_fg *ab8500_fg_get(void);
434int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev); 419int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
435int ab8500_fg_inst_curr_start(struct ab8500_fg *di); 420int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
436int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res); 421int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res);
422int ab8500_fg_inst_curr_started(struct ab8500_fg *di);
437int ab8500_fg_inst_curr_done(struct ab8500_fg *di); 423int ab8500_fg_inst_curr_done(struct ab8500_fg *di);
438 424
439#else 425#else
440static struct abx500_bm_data ab8500_bm_data; 426static struct abx500_bm_data ab8500_bm_data;
441
442static inline int ab8500_fg_inst_curr_start(struct ab8500_fg *di)
443{
444 return -ENODEV;
445}
446
447static inline int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res)
448{
449 return -ENODEV;
450}
451
452#endif 427#endif
453#endif /* _AB8500_BM_H */ 428#endif /* _AB8500_BM_H */
diff --git a/include/linux/mfd/abx500/ab8500-gpio.h b/include/linux/mfd/abx500/ab8500-gpio.h
index 2387c207ea86..172b2f201ae0 100644
--- a/include/linux/mfd/abx500/ab8500-gpio.h
+++ b/include/linux/mfd/abx500/ab8500-gpio.h
@@ -14,10 +14,20 @@
14 * registers. 14 * registers.
15 */ 15 */
16 16
17struct ab8500_gpio_platform_data { 17struct abx500_gpio_platform_data {
18 int gpio_base; 18 int gpio_base;
19 u32 irq_base; 19};
20 u8 config_reg[8]; 20
21enum abx500_gpio_pull_updown {
22 ABX500_GPIO_PULL_DOWN = 0x0,
23 ABX500_GPIO_PULL_NONE = 0x1,
24 ABX500_GPIO_PULL_UP = 0x3,
25};
26
27enum abx500_gpio_vinsel {
28 ABX500_GPIO_VINSEL_VBAT = 0x0,
29 ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
30 ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
21}; 31};
22 32
23#endif /* _AB8500_GPIO_H */ 33#endif /* _AB8500_GPIO_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index 10eb50973c39..ebf12e793db9 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -37,6 +37,11 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
37 return ab8500_sysctrl_write(reg, bits, 0); 37 return ab8500_sysctrl_write(reg, bits, 0);
38} 38}
39 39
40/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
41struct ab8500_sysctrl_platform_data {
42 u8 initial_req_buf_config[8];
43};
44
40/* Registers */ 45/* Registers */
41#define AB8500_TURNONSTATUS 0x100 46#define AB8500_TURNONSTATUS 0x100
42#define AB8500_RESETSTATUS 0x101 47#define AB8500_RESETSTATUS 0x101
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 1cb5698b4d76..9db0bda446a0 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -24,7 +24,7 @@ enum ab8500_version {
24 AB8500_VERSION_AB8500 = 0x0, 24 AB8500_VERSION_AB8500 = 0x0,
25 AB8500_VERSION_AB8505 = 0x1, 25 AB8500_VERSION_AB8505 = 0x1,
26 AB8500_VERSION_AB9540 = 0x2, 26 AB8500_VERSION_AB9540 = 0x2,
27 AB8500_VERSION_AB8540 = 0x3, 27 AB8500_VERSION_AB8540 = 0x4,
28 AB8500_VERSION_UNDEFINED, 28 AB8500_VERSION_UNDEFINED,
29}; 29};
30 30
@@ -32,6 +32,7 @@ enum ab8500_version {
32#define AB8500_CUTEARLY 0x00 32#define AB8500_CUTEARLY 0x00
33#define AB8500_CUT1P0 0x10 33#define AB8500_CUT1P0 0x10
34#define AB8500_CUT1P1 0x11 34#define AB8500_CUT1P1 0x11
35#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */
35#define AB8500_CUT2P0 0x20 36#define AB8500_CUT2P0 0x20
36#define AB8500_CUT3P0 0x30 37#define AB8500_CUT3P0 0x30
37#define AB8500_CUT3P3 0x33 38#define AB8500_CUT3P3 0x33
@@ -39,6 +40,7 @@ enum ab8500_version {
39/* 40/*
40 * AB8500 bank addresses 41 * AB8500 bank addresses
41 */ 42 */
43#define AB8500_M_FSM_RANK 0x0
42#define AB8500_SYS_CTRL1_BLOCK 0x1 44#define AB8500_SYS_CTRL1_BLOCK 0x1
43#define AB8500_SYS_CTRL2_BLOCK 0x2 45#define AB8500_SYS_CTRL2_BLOCK 0x2
44#define AB8500_REGU_CTRL1 0x3 46#define AB8500_REGU_CTRL1 0x3
@@ -58,6 +60,7 @@ enum ab8500_version {
58#define AB8500_DEVELOPMENT 0x11 60#define AB8500_DEVELOPMENT 0x11
59#define AB8500_DEBUG 0x12 61#define AB8500_DEBUG 0x12
60#define AB8500_PROD_TEST 0x13 62#define AB8500_PROD_TEST 0x13
63#define AB8500_STE_TEST 0x14
61#define AB8500_OTP_EMUL 0x15 64#define AB8500_OTP_EMUL 0x15
62 65
63/* 66/*
@@ -65,11 +68,11 @@ enum ab8500_version {
65 * Values used to index into array ab8500_irq_regoffset[] defined in 68 * Values used to index into array ab8500_irq_regoffset[] defined in
66 * drivers/mdf/ab8500-core.c 69 * drivers/mdf/ab8500-core.c
67 */ 70 */
68/* Definitions for AB8500 and AB9540 */ 71/* Definitions for AB8500, AB9540 and AB8540 */
69/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */ 72/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
70#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */ 73#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
71#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */ 74#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */
72#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */ 75#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */
73#define AB8500_INT_TEMP_WARM 3 76#define AB8500_INT_TEMP_WARM 3
74#define AB8500_INT_PON_KEY2DB_F 4 77#define AB8500_INT_PON_KEY2DB_F 4
75#define AB8500_INT_PON_KEY2DB_R 5 78#define AB8500_INT_PON_KEY2DB_R 5
@@ -77,18 +80,19 @@ enum ab8500_version {
77#define AB8500_INT_PON_KEY1DB_R 7 80#define AB8500_INT_PON_KEY1DB_R 7
78/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */ 81/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
79#define AB8500_INT_BATT_OVV 8 82#define AB8500_INT_BATT_OVV 8
80#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */ 83#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */
81#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */ 84#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */
82#define AB8500_INT_VBUS_DET_F 14 85#define AB8500_INT_VBUS_DET_F 14
83#define AB8500_INT_VBUS_DET_R 15 86#define AB8500_INT_VBUS_DET_R 15
84/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */ 87/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
85#define AB8500_INT_VBUS_CH_DROP_END 16 88#define AB8500_INT_VBUS_CH_DROP_END 16
86#define AB8500_INT_RTC_60S 17 89#define AB8500_INT_RTC_60S 17
87#define AB8500_INT_RTC_ALARM 18 90#define AB8500_INT_RTC_ALARM 18
91#define AB8540_INT_BIF_INT 19
88#define AB8500_INT_BAT_CTRL_INDB 20 92#define AB8500_INT_BAT_CTRL_INDB 20
89#define AB8500_INT_CH_WD_EXP 21 93#define AB8500_INT_CH_WD_EXP 21
90#define AB8500_INT_VBUS_OVV 22 94#define AB8500_INT_VBUS_OVV 22
91#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */ 95#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */
92/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */ 96/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
93#define AB8500_INT_CCN_CONV_ACC 24 97#define AB8500_INT_CCN_CONV_ACC 24
94#define AB8500_INT_INT_AUD 25 98#define AB8500_INT_INT_AUD 25
@@ -99,7 +103,7 @@ enum ab8500_version {
99#define AB8500_INT_BUP_CHG_NOT_OK 30 103#define AB8500_INT_BUP_CHG_NOT_OK 30
100#define AB8500_INT_BUP_CHG_OK 31 104#define AB8500_INT_BUP_CHG_OK 31
101/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */ 105/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
102#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */ 106#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */
103#define AB8500_INT_ACC_DETECT_1DB_F 33 107#define AB8500_INT_ACC_DETECT_1DB_F 33
104#define AB8500_INT_ACC_DETECT_1DB_R 34 108#define AB8500_INT_ACC_DETECT_1DB_R 34
105#define AB8500_INT_ACC_DETECT_22DB_F 35 109#define AB8500_INT_ACC_DETECT_22DB_F 35
@@ -108,23 +112,23 @@ enum ab8500_version {
108#define AB8500_INT_ACC_DETECT_21DB_R 38 112#define AB8500_INT_ACC_DETECT_21DB_R 38
109#define AB8500_INT_GP_SW_ADC_CONV_END 39 113#define AB8500_INT_GP_SW_ADC_CONV_END 39
110/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */ 114/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
111#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */ 115#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */
112#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */ 116#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */
113#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */ 117#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */
114#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */ 118#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */
115#define AB8500_INT_GPIO10R 44 119#define AB8500_INT_GPIO10R 44 /* not 8540 */
116#define AB8500_INT_GPIO11R 45 120#define AB8500_INT_GPIO11R 45 /* not 8540 */
117#define AB8500_INT_GPIO12R 46 /* not 8505 */ 121#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */
118#define AB8500_INT_GPIO13R 47 122#define AB8500_INT_GPIO13R 47 /* not 8540 */
119/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */ 123/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
120#define AB8500_INT_GPIO24R 48 /* not 8505 */ 124#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */
121#define AB8500_INT_GPIO25R 49 /* not 8505 */ 125#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */
122#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */ 126#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */
123#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */ 127#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */
124#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */ 128#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */
125#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */ 129#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */
126#define AB8500_INT_GPIO40R 54 130#define AB8500_INT_GPIO40R 54 /* not 8540 */
127#define AB8500_INT_GPIO41R 55 131#define AB8500_INT_GPIO41R 55 /* not 8540 */
128/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */ 132/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
129#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */ 133#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
130#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */ 134#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
@@ -135,14 +139,14 @@ enum ab8500_version {
135#define AB8500_INT_GPIO12F 62 /* not 8505 */ 139#define AB8500_INT_GPIO12F 62 /* not 8505 */
136#define AB8500_INT_GPIO13F 63 140#define AB8500_INT_GPIO13F 63
137/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */ 141/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
138#define AB8500_INT_GPIO24F 64 /* not 8505 */ 142#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */
139#define AB8500_INT_GPIO25F 65 /* not 8505 */ 143#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */
140#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */ 144#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */
141#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */ 145#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */
142#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */ 146#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */
143#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */ 147#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */
144#define AB8500_INT_GPIO40F 70 148#define AB8500_INT_GPIO40F 70 /* not 8540 */
145#define AB8500_INT_GPIO41F 71 149#define AB8500_INT_GPIO41F 71 /* not 8540 */
146/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */ 150/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
147#define AB8500_INT_ADP_SOURCE_ERROR 72 151#define AB8500_INT_ADP_SOURCE_ERROR 72
148#define AB8500_INT_ADP_SINK_ERROR 73 152#define AB8500_INT_ADP_SINK_ERROR 73
@@ -160,42 +164,44 @@ enum ab8500_version {
160#define AB8500_INT_SRP_DETECT 88 164#define AB8500_INT_SRP_DETECT 88
161#define AB8500_INT_USB_CHARGER_NOT_OKR 89 165#define AB8500_INT_USB_CHARGER_NOT_OKR 89
162#define AB8500_INT_ID_WAKEUP_R 90 166#define AB8500_INT_ID_WAKEUP_R 90
167#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */
163#define AB8500_INT_ID_DET_R1R 92 168#define AB8500_INT_ID_DET_R1R 92
164#define AB8500_INT_ID_DET_R2R 93 169#define AB8500_INT_ID_DET_R2R 93
165#define AB8500_INT_ID_DET_R3R 94 170#define AB8500_INT_ID_DET_R3R 94
166#define AB8500_INT_ID_DET_R4R 95 171#define AB8500_INT_ID_DET_R4R 95
167/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */ 172/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
168#define AB8500_INT_ID_WAKEUP_F 96 173#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */
169#define AB8500_INT_ID_DET_R1F 98 174#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */
170#define AB8500_INT_ID_DET_R2F 99 175#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */
171#define AB8500_INT_ID_DET_R3F 100 176#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */
172#define AB8500_INT_ID_DET_R4F 101 177#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */
173#define AB8500_INT_CHAUTORESTARTAFTSEC 102 178#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */
179#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */
174#define AB8500_INT_CHSTOPBYSEC 103 180#define AB8500_INT_CHSTOPBYSEC 103
175/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */ 181/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
176#define AB8500_INT_USB_CH_TH_PROT_F 104 182#define AB8500_INT_USB_CH_TH_PROT_F 104
177#define AB8500_INT_USB_CH_TH_PROT_R 105 183#define AB8500_INT_USB_CH_TH_PROT_R 105
178#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */ 184#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
179#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */ 185#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
180#define AB8500_INT_CHCURLIMNOHSCHIRP 109 186#define AB8500_INT_CHCURLIMNOHSCHIRP 109
181#define AB8500_INT_CHCURLIMHSCHIRP 110 187#define AB8500_INT_CHCURLIMHSCHIRP 110
182#define AB8500_INT_XTAL32K_KO 111 188#define AB8500_INT_XTAL32K_KO 111
183 189
184/* Definitions for AB9540 */ 190/* Definitions for AB9540 / AB8505 */
185/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */ 191/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
186#define AB9540_INT_GPIO50R 113 192#define AB9540_INT_GPIO50R 113 /* not 8540 */
187#define AB9540_INT_GPIO51R 114 /* not 8505 */ 193#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */
188#define AB9540_INT_GPIO52R 115 194#define AB9540_INT_GPIO52R 115 /* not 8540 */
189#define AB9540_INT_GPIO53R 116 195#define AB9540_INT_GPIO53R 116 /* not 8540 */
190#define AB9540_INT_GPIO54R 117 /* not 8505 */ 196#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */
191#define AB9540_INT_IEXT_CH_RF_BFN_R 118 197#define AB9540_INT_IEXT_CH_RF_BFN_R 118
192#define AB9540_INT_IEXT_CH_RF_BFN_F 119
193/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */ 198/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
194#define AB9540_INT_GPIO50F 121 199#define AB9540_INT_GPIO50F 121 /* not 8540 */
195#define AB9540_INT_GPIO51F 122 /* not 8505 */ 200#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */
196#define AB9540_INT_GPIO52F 123 201#define AB9540_INT_GPIO52F 123 /* not 8540 */
197#define AB9540_INT_GPIO53F 124 202#define AB9540_INT_GPIO53F 124 /* not 8540 */
198#define AB9540_INT_GPIO54F 125 /* not 8505 */ 203#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */
204#define AB9540_INT_IEXT_CH_RF_BFN_F 126
199/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */ 205/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
200#define AB8505_INT_KEYSTUCK 128 206#define AB8505_INT_KEYSTUCK 128
201#define AB8505_INT_IKR 129 207#define AB8505_INT_IKR 129
@@ -204,6 +210,87 @@ enum ab8500_version {
204#define AB8505_INT_KEYDEGLITCH 132 210#define AB8505_INT_KEYDEGLITCH 132
205#define AB8505_INT_MODPWRSTATUSF 134 211#define AB8505_INT_MODPWRSTATUSF 134
206#define AB8505_INT_MODPWRSTATUSR 135 212#define AB8505_INT_MODPWRSTATUSR 135
213/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
214#define AB8500_INT_HOOK_DET_NEG_F 138
215#define AB8500_INT_HOOK_DET_NEG_R 139
216#define AB8500_INT_HOOK_DET_POS_F 140
217#define AB8500_INT_HOOK_DET_POS_R 141
218#define AB8500_INT_PLUG_DET_COMP_F 142
219#define AB8500_INT_PLUG_DET_COMP_R 143
220/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
221#define AB8505_INT_COLL 144
222#define AB8505_INT_RESERR 145
223#define AB8505_INT_FRAERR 146
224#define AB8505_INT_COMERR 147
225#define AB8505_INT_SPDSET 148
226#define AB8505_INT_DSENT 149
227#define AB8505_INT_DREC 150
228#define AB8505_INT_ACC_INT 151
229/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
230#define AB8505_INT_NOPINT 152
231/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
232#define AB8540_INT_IDPLUGDETCOMPF 160
233#define AB8540_INT_IDPLUGDETCOMPR 161
234#define AB8540_INT_FMDETCOMPLOF 162
235#define AB8540_INT_FMDETCOMPLOR 163
236#define AB8540_INT_FMDETCOMPHIF 164
237#define AB8540_INT_FMDETCOMPHIR 165
238#define AB8540_INT_ID5VDETCOMPF 166
239#define AB8540_INT_ID5VDETCOMPR 167
240/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
241#define AB8540_INT_GPIO43F 168
242#define AB8540_INT_GPIO43R 169
243#define AB8540_INT_GPIO44F 170
244#define AB8540_INT_GPIO44R 171
245#define AB8540_INT_KEYPOSDETCOMPF 172
246#define AB8540_INT_KEYPOSDETCOMPR 173
247#define AB8540_INT_KEYNEGDETCOMPF 174
248#define AB8540_INT_KEYNEGDETCOMPR 175
249/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
250#define AB8540_INT_GPIO1VBATF 176
251#define AB8540_INT_GPIO1VBATR 177
252#define AB8540_INT_GPIO2VBATF 178
253#define AB8540_INT_GPIO2VBATR 179
254#define AB8540_INT_GPIO3VBATF 180
255#define AB8540_INT_GPIO3VBATR 181
256#define AB8540_INT_GPIO4VBATF 182
257#define AB8540_INT_GPIO4VBATR 183
258/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
259#define AB8540_INT_SYSCLKREQ2F 184
260#define AB8540_INT_SYSCLKREQ2R 185
261#define AB8540_INT_SYSCLKREQ3F 186
262#define AB8540_INT_SYSCLKREQ3R 187
263#define AB8540_INT_SYSCLKREQ4F 188
264#define AB8540_INT_SYSCLKREQ4R 189
265#define AB8540_INT_SYSCLKREQ5F 190
266#define AB8540_INT_SYSCLKREQ5R 191
267/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
268#define AB8540_INT_PWMOUT1F 192
269#define AB8540_INT_PWMOUT1R 193
270#define AB8540_INT_PWMCTRL0F 194
271#define AB8540_INT_PWMCTRL0R 195
272#define AB8540_INT_PWMCTRL1F 196
273#define AB8540_INT_PWMCTRL1R 197
274#define AB8540_INT_SYSCLKREQ6F 198
275#define AB8540_INT_SYSCLKREQ6R 199
276/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
277#define AB8540_INT_PWMEXTVIBRA1F 200
278#define AB8540_INT_PWMEXTVIBRA1R 201
279#define AB8540_INT_PWMEXTVIBRA2F 202
280#define AB8540_INT_PWMEXTVIBRA2R 203
281#define AB8540_INT_PWMOUT2F 204
282#define AB8540_INT_PWMOUT2R 205
283#define AB8540_INT_PWMOUT3F 206
284#define AB8540_INT_PWMOUT3R 207
285/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
286#define AB8540_INT_ADDATA2F 208
287#define AB8540_INT_ADDATA2R 209
288#define AB8540_INT_DADATA2F 210
289#define AB8540_INT_DADATA2R 211
290#define AB8540_INT_FSYNC2F 212
291#define AB8540_INT_FSYNC2R 213
292#define AB8540_INT_BITCLK2F 214
293#define AB8540_INT_BITCLK2R 215
207 294
208/* 295/*
209 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the 296 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
@@ -213,13 +300,24 @@ enum ab8500_version {
213 * which is larger. 300 * which is larger.
214 */ 301 */
215#define AB8500_NR_IRQS 112 302#define AB8500_NR_IRQS 112
216#define AB8505_NR_IRQS 136 303#define AB8505_NR_IRQS 153
217#define AB9540_NR_IRQS 136 304#define AB9540_NR_IRQS 153
305#define AB8540_NR_IRQS 216
218/* This is set to the roof of any AB8500 chip variant IRQ counts */ 306/* This is set to the roof of any AB8500 chip variant IRQ counts */
219#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS 307#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS
220 308
221#define AB8500_NUM_IRQ_REGS 14 309#define AB8500_NUM_IRQ_REGS 14
222#define AB9540_NUM_IRQ_REGS 17 310#define AB9540_NUM_IRQ_REGS 20
311#define AB8540_NUM_IRQ_REGS 27
312
313/* Turn On Status Event */
314#define AB8500_POR_ON_VBAT 0x01
315#define AB8500_POW_KEY_1_ON 0x02
316#define AB8500_POW_KEY_2_ON 0x04
317#define AB8500_RTC_ALARM 0x08
318#define AB8500_MAIN_CH_DET 0x10
319#define AB8500_VBUS_DET 0x20
320#define AB8500_USB_ID_DET 0x40
223 321
224/** 322/**
225 * struct ab8500 - ab8500 internal structure 323 * struct ab8500 - ab8500 internal structure
@@ -270,10 +368,12 @@ struct regulator_reg_init;
270struct regulator_init_data; 368struct regulator_init_data;
271struct ab8500_gpio_platform_data; 369struct ab8500_gpio_platform_data;
272struct ab8500_codec_platform_data; 370struct ab8500_codec_platform_data;
371struct ab8500_sysctrl_platform_data;
273 372
274/** 373/**
275 * struct ab8500_platform_data - AB8500 platform data 374 * struct ab8500_platform_data - AB8500 platform data
276 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used 375 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
376 * @pm_power_off: Should machine pm power off hook be registered or not
277 * @init: board-specific initialization after detection of ab8500 377 * @init: board-specific initialization after detection of ab8500
278 * @num_regulator_reg_init: number of regulator init registers 378 * @num_regulator_reg_init: number of regulator init registers
279 * @regulator_reg_init: regulator init registers 379 * @regulator_reg_init: regulator init registers
@@ -282,13 +382,15 @@ struct ab8500_codec_platform_data;
282 */ 382 */
283struct ab8500_platform_data { 383struct ab8500_platform_data {
284 int irq_base; 384 int irq_base;
385 bool pm_power_off;
285 void (*init) (struct ab8500 *); 386 void (*init) (struct ab8500 *);
286 int num_regulator_reg_init; 387 int num_regulator_reg_init;
287 struct ab8500_regulator_reg_init *regulator_reg_init; 388 struct ab8500_regulator_reg_init *regulator_reg_init;
288 int num_regulator; 389 int num_regulator;
289 struct regulator_init_data *regulator; 390 struct regulator_init_data *regulator;
290 struct ab8500_gpio_platform_data *gpio; 391 struct abx500_gpio_platform_data *gpio;
291 struct ab8500_codec_platform_data *codec; 392 struct ab8500_codec_platform_data *codec;
393 struct ab8500_sysctrl_platform_data *sysctrl;
292}; 394};
293 395
294extern int ab8500_init(struct ab8500 *ab8500, 396extern int ab8500_init(struct ab8500 *ab8500,
@@ -335,10 +437,87 @@ static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
335 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0)); 437 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
336} 438}
337 439
440static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
441{
442 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
443}
444
338/* exclude also ab8505, ab9540... */ 445/* exclude also ab8505, ab9540... */
339static inline int is_ab8500_2p0(struct ab8500 *ab) 446static inline int is_ab8500_2p0(struct ab8500 *ab)
340{ 447{
341 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); 448 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
342} 449}
343 450
451static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
452{
453 return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
454}
455
456static inline int is_ab8505_2p0(struct ab8500 *ab)
457{
458 return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
459}
460
461static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
462{
463 return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
464}
465
466static inline int is_ab9540_2p0(struct ab8500 *ab)
467{
468 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
469}
470
471/*
472 * Be careful, the marketing name for this chip is 2.1
473 * but the value read from the chip is 3.0 (0x30)
474 */
475static inline int is_ab9540_3p0(struct ab8500 *ab)
476{
477 return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
478}
479
480static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
481{
482 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
483}
484
485static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
486{
487 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
488}
489
490static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
491{
492 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
493}
494
495static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
496{
497 return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
498}
499
500static inline int is_ab8540_2p0(struct ab8500 *ab)
501{
502 return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
503}
504
505static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
506{
507 return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
508}
509
510static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
511{
512 return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
513}
514
515#ifdef CONFIG_AB8500_DEBUG
516void ab8500_dump_all_banks(struct device *dev);
517void ab8500_debug_register_interrupt(int line);
518#else
519static inline void ab8500_dump_all_banks(struct device *dev) {}
520static inline void ab8500_debug_register_interrupt(int line) {}
521#endif
522
344#endif /* MFD_AB8500_H */ 523#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/abx500/ux500_chargalg.h b/include/linux/mfd/abx500/ux500_chargalg.h
index 9b07725750c9..d43ac0f35526 100644
--- a/include/linux/mfd/abx500/ux500_chargalg.h
+++ b/include/linux/mfd/abx500/ux500_chargalg.h
@@ -27,12 +27,17 @@ struct ux500_charger_ops {
27 * @ops ux500 charger operations 27 * @ops ux500 charger operations
28 * @max_out_volt maximum output charger voltage in mV 28 * @max_out_volt maximum output charger voltage in mV
29 * @max_out_curr maximum output charger current in mA 29 * @max_out_curr maximum output charger current in mA
30 * @enabled indicates if this charger is used or not
31 * @external external charger unit (pm2xxx)
30 */ 32 */
31struct ux500_charger { 33struct ux500_charger {
32 struct power_supply psy; 34 struct power_supply psy;
33 struct ux500_charger_ops ops; 35 struct ux500_charger_ops ops;
34 int max_out_volt; 36 int max_out_volt;
35 int max_out_curr; 37 int max_out_curr;
38 int wdt_refresh;
39 bool enabled;
40 bool external;
36}; 41};
37 42
38#endif 43#endif
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index a580363a7d29..a710255528d7 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -75,8 +75,10 @@ enum arizona_type {
75#define ARIZONA_IRQ_DCS_HP_DONE 47 75#define ARIZONA_IRQ_DCS_HP_DONE 47
76#define ARIZONA_IRQ_FLL2_CLOCK_OK 48 76#define ARIZONA_IRQ_FLL2_CLOCK_OK 48
77#define ARIZONA_IRQ_FLL1_CLOCK_OK 49 77#define ARIZONA_IRQ_FLL1_CLOCK_OK 49
78#define ARIZONA_IRQ_MICD_CLAMP_RISE 50
79#define ARIZONA_IRQ_MICD_CLAMP_FALL 51
78 80
79#define ARIZONA_NUM_IRQ 50 81#define ARIZONA_NUM_IRQ 52
80 82
81struct snd_soc_dapm_context; 83struct snd_soc_dapm_context;
82 84
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
index 8b1d1daaae16..455c51d22d6b 100644
--- a/include/linux/mfd/arizona/pdata.h
+++ b/include/linux/mfd/arizona/pdata.h
@@ -56,12 +56,16 @@
56#define ARIZONA_DMIC_MICBIAS2 2 56#define ARIZONA_DMIC_MICBIAS2 2
57#define ARIZONA_DMIC_MICBIAS3 3 57#define ARIZONA_DMIC_MICBIAS3 3
58 58
59#define ARIZONA_MAX_MICBIAS 3
60
59#define ARIZONA_INMODE_DIFF 0 61#define ARIZONA_INMODE_DIFF 0
60#define ARIZONA_INMODE_SE 1 62#define ARIZONA_INMODE_SE 1
61#define ARIZONA_INMODE_DMIC 2 63#define ARIZONA_INMODE_DMIC 2
62 64
63#define ARIZONA_MAX_OUTPUT 6 65#define ARIZONA_MAX_OUTPUT 6
64 66
67#define ARIZONA_MAX_AIF 3
68
65#define ARIZONA_HAP_ACT_ERM 0 69#define ARIZONA_HAP_ACT_ERM 0
66#define ARIZONA_HAP_ACT_LRA 2 70#define ARIZONA_HAP_ACT_LRA 2
67 71
@@ -69,6 +73,13 @@
69 73
70struct regulator_init_data; 74struct regulator_init_data;
71 75
76struct arizona_micbias {
77 int mV; /** Regulated voltage */
78 unsigned int ext_cap:1; /** External capacitor fitted */
79 unsigned int discharge:1; /** Actively discharge */
80 unsigned int fast_start:1; /** Enable aggressive startup ramp rate */
81};
82
72struct arizona_micd_config { 83struct arizona_micd_config {
73 unsigned int src; 84 unsigned int src;
74 unsigned int bias; 85 unsigned int bias;
@@ -96,9 +107,37 @@ struct arizona_pdata {
96 /** Pin state for GPIO pins */ 107 /** Pin state for GPIO pins */
97 int gpio_defaults[ARIZONA_MAX_GPIO]; 108 int gpio_defaults[ARIZONA_MAX_GPIO];
98 109
110 /**
111 * Maximum number of channels clocks will be generated for,
112 * useful for systems where and I2S bus with multiple data
113 * lines is mastered.
114 */
115 int max_channels_clocked[ARIZONA_MAX_AIF];
116
117 /** GPIO5 is used for jack detection */
118 bool jd_gpio5;
119
120 /** Use the headphone detect circuit to identify the accessory */
121 bool hpdet_acc_id;
122
123 /** GPIO used for mic isolation with HPDET */
124 int hpdet_id_gpio;
125
99 /** GPIO for mic detection polarity */ 126 /** GPIO for mic detection polarity */
100 int micd_pol_gpio; 127 int micd_pol_gpio;
101 128
129 /** Mic detect ramp rate */
130 int micd_bias_start_time;
131
132 /** Mic detect sample rate */
133 int micd_rate;
134
135 /** Mic detect debounce level */
136 int micd_dbtime;
137
138 /** Force MICBIAS on for mic detect */
139 bool micd_force_micbias;
140
102 /** Headset polarity configurations */ 141 /** Headset polarity configurations */
103 struct arizona_micd_config *micd_configs; 142 struct arizona_micd_config *micd_configs;
104 int num_micd_configs; 143 int num_micd_configs;
@@ -106,6 +145,9 @@ struct arizona_pdata {
106 /** Reference voltage for DMIC inputs */ 145 /** Reference voltage for DMIC inputs */
107 int dmic_ref[ARIZONA_MAX_INPUT]; 146 int dmic_ref[ARIZONA_MAX_INPUT];
108 147
148 /** MICBIAS configurations */
149 struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
150
109 /** Mode of input structures */ 151 /** Mode of input structures */
110 int inmode[ARIZONA_MAX_INPUT]; 152 int inmode[ARIZONA_MAX_INPUT];
111 153
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 1f6fe31a4d5c..340355136069 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -119,6 +119,8 @@
119#define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293 119#define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
120#define ARIZONA_HEADPHONE_DETECT_1 0x29B 120#define ARIZONA_HEADPHONE_DETECT_1 0x29B
121#define ARIZONA_HEADPHONE_DETECT_2 0x29C 121#define ARIZONA_HEADPHONE_DETECT_2 0x29C
122#define ARIZONA_HP_DACVAL 0x29F
123#define ARIZONA_MICD_CLAMP_CONTROL 0x2A2
122#define ARIZONA_MIC_DETECT_1 0x2A3 124#define ARIZONA_MIC_DETECT_1 0x2A3
123#define ARIZONA_MIC_DETECT_2 0x2A4 125#define ARIZONA_MIC_DETECT_2 0x2A4
124#define ARIZONA_MIC_DETECT_3 0x2A5 126#define ARIZONA_MIC_DETECT_3 0x2A5
@@ -982,18 +984,34 @@
982#define ARIZONA_DSP1_STATUS_1 0x1104 984#define ARIZONA_DSP1_STATUS_1 0x1104
983#define ARIZONA_DSP1_STATUS_2 0x1105 985#define ARIZONA_DSP1_STATUS_2 0x1105
984#define ARIZONA_DSP1_STATUS_3 0x1106 986#define ARIZONA_DSP1_STATUS_3 0x1106
987#define ARIZONA_DSP1_SCRATCH_0 0x1140
988#define ARIZONA_DSP1_SCRATCH_1 0x1141
989#define ARIZONA_DSP1_SCRATCH_2 0x1142
990#define ARIZONA_DSP1_SCRATCH_3 0x1143
985#define ARIZONA_DSP2_CONTROL_1 0x1200 991#define ARIZONA_DSP2_CONTROL_1 0x1200
986#define ARIZONA_DSP2_CLOCKING_1 0x1201 992#define ARIZONA_DSP2_CLOCKING_1 0x1201
987#define ARIZONA_DSP2_STATUS_1 0x1204 993#define ARIZONA_DSP2_STATUS_1 0x1204
988#define ARIZONA_DSP2_STATUS_2 0x1205 994#define ARIZONA_DSP2_STATUS_2 0x1205
995#define ARIZONA_DSP2_SCRATCH_0 0x1240
996#define ARIZONA_DSP2_SCRATCH_1 0x1241
997#define ARIZONA_DSP2_SCRATCH_2 0x1242
998#define ARIZONA_DSP2_SCRATCH_3 0x1243
989#define ARIZONA_DSP3_CONTROL_1 0x1300 999#define ARIZONA_DSP3_CONTROL_1 0x1300
990#define ARIZONA_DSP3_CLOCKING_1 0x1301 1000#define ARIZONA_DSP3_CLOCKING_1 0x1301
991#define ARIZONA_DSP3_STATUS_1 0x1304 1001#define ARIZONA_DSP3_STATUS_1 0x1304
992#define ARIZONA_DSP3_STATUS_2 0x1305 1002#define ARIZONA_DSP3_STATUS_2 0x1305
1003#define ARIZONA_DSP3_SCRATCH_0 0x1340
1004#define ARIZONA_DSP3_SCRATCH_1 0x1341
1005#define ARIZONA_DSP3_SCRATCH_2 0x1342
1006#define ARIZONA_DSP3_SCRATCH_3 0x1343
993#define ARIZONA_DSP4_CONTROL_1 0x1400 1007#define ARIZONA_DSP4_CONTROL_1 0x1400
994#define ARIZONA_DSP4_CLOCKING_1 0x1401 1008#define ARIZONA_DSP4_CLOCKING_1 0x1401
995#define ARIZONA_DSP4_STATUS_1 0x1404 1009#define ARIZONA_DSP4_STATUS_1 0x1404
996#define ARIZONA_DSP4_STATUS_2 0x1405 1010#define ARIZONA_DSP4_STATUS_2 0x1405
1011#define ARIZONA_DSP4_SCRATCH_0 0x1440
1012#define ARIZONA_DSP4_SCRATCH_1 0x1441
1013#define ARIZONA_DSP4_SCRATCH_2 0x1442
1014#define ARIZONA_DSP4_SCRATCH_3 0x1443
997 1015
998/* 1016/*
999 * Field Definitions. 1017 * Field Definitions.
@@ -1194,6 +1212,14 @@
1194/* 1212/*
1195 * R64 (0x40) - Wake control 1213 * R64 (0x40) - Wake control
1196 */ 1214 */
1215#define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */
1216#define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */
1217#define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */
1218#define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */
1219#define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */
1220#define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */
1221#define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */
1222#define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */
1197#define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */ 1223#define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
1198#define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */ 1224#define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
1199#define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */ 1225#define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
@@ -2035,6 +2061,9 @@
2035/* 2061/*
2036 * R667 (0x29B) - Headphone Detect 1 2062 * R667 (0x29B) - Headphone Detect 1
2037 */ 2063 */
2064#define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */
2065#define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */
2066#define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */
2038#define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */ 2067#define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
2039#define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */ 2068#define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
2040#define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */ 2069#define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
@@ -2069,6 +2098,21 @@
2069#define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 2098#define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
2070#define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 2099#define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
2071 2100
2101#define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */
2102#define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */
2103#define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */
2104#define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */
2105#define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */
2106#define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */
2107#define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */
2108
2109/*
2110 * R674 (0x2A2) - MICD clamp control
2111 */
2112#define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */
2113#define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */
2114#define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */
2115
2072/* 2116/*
2073 * R675 (0x2A3) - Mic Detect 1 2117 * R675 (0x2A3) - Mic Detect 1
2074 */ 2118 */
@@ -5239,6 +5283,14 @@
5239/* 5283/*
5240 * R3408 (0xD50) - AOD wkup and trig 5284 * R3408 (0xD50) - AOD wkup and trig
5241 */ 5285 */
5286#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
5287#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
5288#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */
5289#define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */
5290#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
5291#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
5292#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */
5293#define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */
5242#define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */ 5294#define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
5243#define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */ 5295#define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
5244#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */ 5296#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
@@ -5267,6 +5319,12 @@
5267/* 5319/*
5268 * R3409 (0xD51) - AOD IRQ1 5320 * R3409 (0xD51) - AOD IRQ1
5269 */ 5321 */
5322#define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */
5323#define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */
5324#define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */
5325#define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */
5326#define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */
5327#define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */
5270#define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */ 5328#define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
5271#define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */ 5329#define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
5272#define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */ 5330#define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
@@ -5295,6 +5353,12 @@
5295/* 5353/*
5296 * R3410 (0xD52) - AOD IRQ2 5354 * R3410 (0xD52) - AOD IRQ2
5297 */ 5355 */
5356#define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */
5357#define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */
5358#define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */
5359#define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */
5360#define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */
5361#define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */
5298#define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */ 5362#define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
5299#define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */ 5363#define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
5300#define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */ 5364#define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
@@ -5379,6 +5443,10 @@
5379/* 5443/*
5380 * R3413 (0xD55) - AOD IRQ Raw Status 5444 * R3413 (0xD55) - AOD IRQ Raw Status
5381 */ 5445 */
5446#define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */
5447#define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */
5448#define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */
5449#define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */
5382#define ARIZONA_GP5_STS 0x0004 /* GP5_STS */ 5450#define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
5383#define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */ 5451#define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
5384#define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */ 5452#define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
@@ -5395,6 +5463,10 @@
5395/* 5463/*
5396 * R3414 (0xD56) - Jack detect debounce 5464 * R3414 (0xD56) - Jack detect debounce
5397 */ 5465 */
5466#define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */
5467#define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */
5468#define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */
5469#define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */
5398#define ARIZONA_JD2_DB 0x0002 /* JD2_DB */ 5470#define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
5399#define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */ 5471#define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
5400#define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */ 5472#define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 6ee4247df11e..77a46ae2fc17 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -16,12 +16,6 @@
16/* 16/*
17 * Registers 17 * Registers
18 */ 18 */
19#define DB8500_PRCM_GPIOCR 0x138
20#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
21#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
22#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
23#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)
24
25#define DB8500_PRCM_LINE_VALUE 0x170 19#define DB8500_PRCM_LINE_VALUE 0x170
26#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3) 20#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
27 21
@@ -493,20 +487,6 @@ struct prcmu_auto_pm_config {
493 u8 sva_policy; 487 u8 sva_policy;
494}; 488};
495 489
496#define PRCMU_FW_PROJECT_U8500 2
497#define PRCMU_FW_PROJECT_U9500 4
498#define PRCMU_FW_PROJECT_U8500_C2 7
499#define PRCMU_FW_PROJECT_U9500_C2 11
500#define PRCMU_FW_PROJECT_U8520 13
501#define PRCMU_FW_PROJECT_U8420 14
502
503struct prcmu_fw_version {
504 u8 project;
505 u8 api_version;
506 u8 func_version;
507 u8 errata;
508};
509
510#ifdef CONFIG_MFD_DB8500_PRCMU 490#ifdef CONFIG_MFD_DB8500_PRCMU
511 491
512void db8500_prcmu_early_init(void); 492void db8500_prcmu_early_init(void);
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index c202d6c4d879..3abcca91eecd 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -12,6 +12,10 @@
12#include <linux/notifier.h> 12#include <linux/notifier.h>
13#include <linux/err.h> 13#include <linux/err.h>
14 14
15/* Offset for the firmware version within the TCPM */
16#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
17#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
18
15/* PRCMU Wakeup defines */ 19/* PRCMU Wakeup defines */
16enum prcmu_wakeup_index { 20enum prcmu_wakeup_index {
17 PRCMU_WAKEUP_INDEX_RTC, 21 PRCMU_WAKEUP_INDEX_RTC,
@@ -147,6 +151,18 @@ enum prcmu_clock {
147}; 151};
148 152
149/** 153/**
154 * enum prcmu_wdog_id - PRCMU watchdog IDs
155 * @PRCMU_WDOG_ALL: use all timers
156 * @PRCMU_WDOG_CPU1: use first CPU timer only
157 * @PRCMU_WDOG_CPU2: use second CPU timer conly
158 */
159enum prcmu_wdog_id {
160 PRCMU_WDOG_ALL = 0x00,
161 PRCMU_WDOG_CPU1 = 0x01,
162 PRCMU_WDOG_CPU2 = 0x02,
163};
164
165/**
150 * enum ape_opp - APE OPP states definition 166 * enum ape_opp - APE OPP states definition
151 * @APE_OPP_INIT: 167 * @APE_OPP_INIT:
152 * @APE_NO_CHANGE: The APE operating point is unchanged 168 * @APE_NO_CHANGE: The APE operating point is unchanged
@@ -214,12 +230,52 @@ enum ddr_pwrst {
214 DDR_PWR_STATE_OFFHIGHLAT = 0x03 230 DDR_PWR_STATE_OFFHIGHLAT = 0x03
215}; 231};
216 232
233#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
234
235struct prcmu_pdata
236{
237 bool enable_set_ddr_opp;
238 bool enable_ape_opp_100_voltage;
239 struct ab8500_platform_data *ab_platdata;
240 u32 version_offset;
241 u32 legacy_offset;
242 u32 adt_offset;
243};
244
245#define PRCMU_FW_PROJECT_U8500 2
246#define PRCMU_FW_PROJECT_U8400 3
247#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
248#define PRCMU_FW_PROJECT_U8500_MBB 5
249#define PRCMU_FW_PROJECT_U8500_C1 6
250#define PRCMU_FW_PROJECT_U8500_C2 7
251#define PRCMU_FW_PROJECT_U8500_C3 8
252#define PRCMU_FW_PROJECT_U8500_C4 9
253#define PRCMU_FW_PROJECT_U9500_MBL 10
254#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
255#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
256#define PRCMU_FW_PROJECT_U8520 13
257#define PRCMU_FW_PROJECT_U8420 14
258#define PRCMU_FW_PROJECT_A9420 20
259/* [32..63] 9540 and derivatives */
260#define PRCMU_FW_PROJECT_U9540 32
261/* [64..95] 8540 and derivatives */
262#define PRCMU_FW_PROJECT_L8540 64
263/* [96..126] 8580 and derivatives */
264#define PRCMU_FW_PROJECT_L8580 96
265
266#define PRCMU_FW_PROJECT_NAME_LEN 20
267struct prcmu_fw_version {
268 u32 project; /* Notice, project shifted with 8 on ux540 */
269 u8 api_version;
270 u8 func_version;
271 u8 errata;
272 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
273};
274
217#include <linux/mfd/db8500-prcmu.h> 275#include <linux/mfd/db8500-prcmu.h>
218 276
219#if defined(CONFIG_UX500_SOC_DB8500) 277#if defined(CONFIG_UX500_SOC_DB8500)
220 278
221#include <mach/id.h>
222
223static inline void __init prcmu_early_init(void) 279static inline void __init prcmu_early_init(void)
224{ 280{
225 return db8500_prcmu_early_init(); 281 return db8500_prcmu_early_init();
@@ -626,85 +682,6 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
626 prcmu_write_masked(reg, bits, 0); 682 prcmu_write_masked(reg, bits, 0);
627} 683}
628 684
629#if defined(CONFIG_UX500_SOC_DB8500)
630
631/**
632 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
633 */
634static inline void prcmu_enable_spi2(void)
635{
636 if (cpu_is_u8500())
637 prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
638}
639
640/**
641 * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
642 */
643static inline void prcmu_disable_spi2(void)
644{
645 if (cpu_is_u8500())
646 prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
647}
648
649/**
650 * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
651 * and UARTMOD on OtherAlternateC3.
652 */
653static inline void prcmu_enable_stm_mod_uart(void)
654{
655 if (cpu_is_u8500()) {
656 prcmu_set(DB8500_PRCM_GPIOCR,
657 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
658 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
659 }
660}
661
662/**
663 * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
664 * and UARTMOD on OtherAlternateC3.
665 */
666static inline void prcmu_disable_stm_mod_uart(void)
667{
668 if (cpu_is_u8500()) {
669 prcmu_clear(DB8500_PRCM_GPIOCR,
670 (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
671 DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
672 }
673}
674
675/**
676 * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
677 */
678static inline void prcmu_enable_stm_ape(void)
679{
680 if (cpu_is_u8500()) {
681 prcmu_set(DB8500_PRCM_GPIOCR,
682 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
683 }
684}
685
686/**
687 * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
688 */
689static inline void prcmu_disable_stm_ape(void)
690{
691 if (cpu_is_u8500()) {
692 prcmu_clear(DB8500_PRCM_GPIOCR,
693 DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
694 }
695}
696
697#else
698
699static inline void prcmu_enable_spi2(void) {}
700static inline void prcmu_disable_spi2(void) {}
701static inline void prcmu_enable_stm_mod_uart(void) {}
702static inline void prcmu_disable_stm_mod_uart(void) {}
703static inline void prcmu_enable_stm_ape(void) {}
704static inline void prcmu_disable_stm_ape(void) {}
705
706#endif
707
708/* PRCMU QoS APE OPP class */ 685/* PRCMU QoS APE OPP class */
709#define PRCMU_QOS_APE_OPP 1 686#define PRCMU_QOS_APE_OPP 1
710#define PRCMU_QOS_DDR_OPP 2 687#define PRCMU_QOS_DDR_OPP 2
diff --git a/include/linux/mfd/lp8788.h b/include/linux/mfd/lp8788.h
index 2a32b16f79cb..786bf6679a28 100644
--- a/include/linux/mfd/lp8788.h
+++ b/include/linux/mfd/lp8788.h
@@ -16,6 +16,7 @@
16 16
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/irqdomain.h> 18#include <linux/irqdomain.h>
19#include <linux/pwm.h>
19#include <linux/regmap.h> 20#include <linux/regmap.h>
20 21
21#define LP8788_DEV_BUCK "lp8788-buck" 22#define LP8788_DEV_BUCK "lp8788-buck"
@@ -124,11 +125,6 @@ enum lp8788_bl_ramp_step {
124 LP8788_RAMP_65538us, 125 LP8788_RAMP_65538us,
125}; 126};
126 127
127enum lp8788_bl_pwm_polarity {
128 LP8788_PWM_ACTIVE_HIGH,
129 LP8788_PWM_ACTIVE_LOW,
130};
131
132enum lp8788_isink_scale { 128enum lp8788_isink_scale {
133 LP8788_ISINK_SCALE_100mA, 129 LP8788_ISINK_SCALE_100mA,
134 LP8788_ISINK_SCALE_120mA, 130 LP8788_ISINK_SCALE_120mA,
@@ -229,16 +225,6 @@ struct lp8788_charger_platform_data {
229}; 225};
230 226
231/* 227/*
232 * struct lp8788_bl_pwm_data
233 * @pwm_set_intensity : set duty of pwm
234 * @pwm_get_intensity : get current duty of pwm
235 */
236struct lp8788_bl_pwm_data {
237 void (*pwm_set_intensity) (int brightness, int max_brightness);
238 int (*pwm_get_intensity) (int max_brightness);
239};
240
241/*
242 * struct lp8788_backlight_platform_data 228 * struct lp8788_backlight_platform_data
243 * @name : backlight driver name. (default: "lcd-backlight") 229 * @name : backlight driver name. (default: "lcd-backlight")
244 * @initial_brightness : initial value of backlight brightness 230 * @initial_brightness : initial value of backlight brightness
@@ -248,8 +234,8 @@ struct lp8788_bl_pwm_data {
248 * @rise_time : brightness ramp up step time 234 * @rise_time : brightness ramp up step time
249 * @fall_time : brightness ramp down step time 235 * @fall_time : brightness ramp down step time
250 * @pwm_pol : pwm polarity setting when bl_mode is pwm based 236 * @pwm_pol : pwm polarity setting when bl_mode is pwm based
251 * @pwm_data : platform specific pwm generation functions 237 * @period_ns : platform specific pwm period value. unit is nano.
252 * only valid when bl_mode is pwm based 238 Only valid when bl_mode is LP8788_BL_COMB_PWM_BASED
253 */ 239 */
254struct lp8788_backlight_platform_data { 240struct lp8788_backlight_platform_data {
255 char *name; 241 char *name;
@@ -259,8 +245,8 @@ struct lp8788_backlight_platform_data {
259 enum lp8788_bl_full_scale_current full_scale; 245 enum lp8788_bl_full_scale_current full_scale;
260 enum lp8788_bl_ramp_step rise_time; 246 enum lp8788_bl_ramp_step rise_time;
261 enum lp8788_bl_ramp_step fall_time; 247 enum lp8788_bl_ramp_step fall_time;
262 enum lp8788_bl_pwm_polarity pwm_pol; 248 enum pwm_polarity pwm_pol;
263 struct lp8788_bl_pwm_data pwm_data; 249 unsigned int period_ns;
264}; 250};
265 251
266/* 252/*
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
index 1eeae5c07915..5b18ecde69b5 100644
--- a/include/linux/mfd/max77693-private.h
+++ b/include/linux/mfd/max77693-private.h
@@ -106,6 +106,92 @@ enum max77693_muic_reg {
106 MAX77693_MUIC_REG_END, 106 MAX77693_MUIC_REG_END,
107}; 107};
108 108
109/* MAX77693 MUIC - STATUS1~3 Register */
110#define STATUS1_ADC_SHIFT (0)
111#define STATUS1_ADCLOW_SHIFT (5)
112#define STATUS1_ADCERR_SHIFT (6)
113#define STATUS1_ADC1K_SHIFT (7)
114#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
115#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
116#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
117#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
118
119#define STATUS2_CHGTYP_SHIFT (0)
120#define STATUS2_CHGDETRUN_SHIFT (3)
121#define STATUS2_DCDTMR_SHIFT (4)
122#define STATUS2_DXOVP_SHIFT (5)
123#define STATUS2_VBVOLT_SHIFT (6)
124#define STATUS2_VIDRM_SHIFT (7)
125#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
126#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
127#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
128#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
129#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
130#define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
131
132#define STATUS3_OVP_SHIFT (2)
133#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
134
135/* MAX77693 CDETCTRL1~2 register */
136#define CDETCTRL1_CHGDETEN_SHIFT (0)
137#define CDETCTRL1_CHGTYPMAN_SHIFT (1)
138#define CDETCTRL1_DCDEN_SHIFT (2)
139#define CDETCTRL1_DCD2SCT_SHIFT (3)
140#define CDETCTRL1_CDDELAY_SHIFT (4)
141#define CDETCTRL1_DCDCPL_SHIFT (5)
142#define CDETCTRL1_CDPDET_SHIFT (7)
143#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
144#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
145#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
146#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
147#define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
148#define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
149#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
150
151#define CDETCTRL2_VIDRMEN_SHIFT (1)
152#define CDETCTRL2_DXOVPEN_SHIFT (3)
153#define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
154#define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
155
156/* MAX77693 MUIC - CONTROL1~3 register */
157#define COMN1SW_SHIFT (0)
158#define COMP2SW_SHIFT (3)
159#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
160#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
161#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
162#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
163 | (1 << COMN1SW_SHIFT))
164#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
165 | (2 << COMN1SW_SHIFT))
166#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
167 | (3 << COMN1SW_SHIFT))
168#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
169 | (0 << COMN1SW_SHIFT))
170
171#define CONTROL2_LOWPWR_SHIFT (0)
172#define CONTROL2_ADCEN_SHIFT (1)
173#define CONTROL2_CPEN_SHIFT (2)
174#define CONTROL2_SFOUTASRT_SHIFT (3)
175#define CONTROL2_SFOUTORD_SHIFT (4)
176#define CONTROL2_ACCDET_SHIFT (5)
177#define CONTROL2_USBCPINT_SHIFT (6)
178#define CONTROL2_RCPS_SHIFT (7)
179#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
180#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
181#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
182#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
183#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
184#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
185#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
186#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
187
188#define CONTROL3_JIGSET_SHIFT (0)
189#define CONTROL3_BTLDSET_SHIFT (2)
190#define CONTROL3_ADCDBSET_SHIFT (4)
191#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
192#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
193#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
194
109/* Slave addr = 0x90: Haptic */ 195/* Slave addr = 0x90: Haptic */
110enum max77693_haptic_reg { 196enum max77693_haptic_reg {
111 MAX77693_HAPTIC_REG_STATUS = 0x00, 197 MAX77693_HAPTIC_REG_STATUS = 0x00,
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
index fe03b2d35d4f..3109a6c5c948 100644
--- a/include/linux/mfd/max77693.h
+++ b/include/linux/mfd/max77693.h
@@ -38,6 +38,15 @@ struct max77693_reg_data {
38struct max77693_muic_platform_data { 38struct max77693_muic_platform_data {
39 struct max77693_reg_data *init_data; 39 struct max77693_reg_data *init_data;
40 int num_init_data; 40 int num_init_data;
41
42 int detcable_delay_ms;
43
44 /*
45 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
46 * h/w path of COMP2/COMN1 on CONTROL1 register.
47 */
48 int path_usb;
49 int path_uart;
41}; 50};
42 51
43struct max77693_platform_data { 52struct max77693_platform_data {
diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h
index 74d8e2969630..ce8502e9e7dc 100644
--- a/include/linux/mfd/max8925.h
+++ b/include/linux/mfd/max8925.h
@@ -190,6 +190,8 @@ enum {
190 MAX8925_NR_IRQS, 190 MAX8925_NR_IRQS,
191}; 191};
192 192
193
194
193struct max8925_chip { 195struct max8925_chip {
194 struct device *dev; 196 struct device *dev;
195 struct i2c_client *i2c; 197 struct i2c_client *i2c;
@@ -201,7 +203,6 @@ struct max8925_chip {
201 int irq_base; 203 int irq_base;
202 int core_irq; 204 int core_irq;
203 int tsc_irq; 205 int tsc_irq;
204
205 unsigned int wakeup_flag; 206 unsigned int wakeup_flag;
206}; 207};
207 208
diff --git a/include/linux/mfd/max8997-private.h b/include/linux/mfd/max8997-private.h
index 6ae21bf47d64..fb465dfbb59e 100644
--- a/include/linux/mfd/max8997-private.h
+++ b/include/linux/mfd/max8997-private.h
@@ -194,6 +194,70 @@ enum max8997_muic_reg {
194 MAX8997_MUIC_REG_END = 0xf, 194 MAX8997_MUIC_REG_END = 0xf,
195}; 195};
196 196
197/* MAX8997-MUIC STATUS1 register */
198#define STATUS1_ADC_SHIFT 0
199#define STATUS1_ADCLOW_SHIFT 5
200#define STATUS1_ADCERR_SHIFT 6
201#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
202#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
203#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
204
205/* MAX8997-MUIC STATUS2 register */
206#define STATUS2_CHGTYP_SHIFT 0
207#define STATUS2_CHGDETRUN_SHIFT 3
208#define STATUS2_DCDTMR_SHIFT 4
209#define STATUS2_DBCHG_SHIFT 5
210#define STATUS2_VBVOLT_SHIFT 6
211#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
212#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
213#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
214#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
215#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
216
217/* MAX8997-MUIC STATUS3 register */
218#define STATUS3_OVP_SHIFT 2
219#define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
220
221/* MAX8997-MUIC CONTROL1 register */
222#define COMN1SW_SHIFT 0
223#define COMP2SW_SHIFT 3
224#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
225#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
226#define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
227
228#define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
229 | (1 << COMN1SW_SHIFT))
230#define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
231 | (2 << COMN1SW_SHIFT))
232#define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
233 | (3 << COMN1SW_SHIFT))
234#define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
235 | (0 << COMN1SW_SHIFT))
236
237#define CONTROL2_LOWPWR_SHIFT (0)
238#define CONTROL2_ADCEN_SHIFT (1)
239#define CONTROL2_CPEN_SHIFT (2)
240#define CONTROL2_SFOUTASRT_SHIFT (3)
241#define CONTROL2_SFOUTORD_SHIFT (4)
242#define CONTROL2_ACCDET_SHIFT (5)
243#define CONTROL2_USBCPINT_SHIFT (6)
244#define CONTROL2_RCPS_SHIFT (7)
245#define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
246#define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
247#define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
248#define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
249#define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
250#define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
251#define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
252#define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
253
254#define CONTROL3_JIGSET_SHIFT (0)
255#define CONTROL3_BTLDSET_SHIFT (2)
256#define CONTROL3_ADCDBSET_SHIFT (4)
257#define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
258#define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
259#define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
260
197enum max8997_haptic_reg { 261enum max8997_haptic_reg {
198 MAX8997_HAPTIC_REG_GENERAL = 0x00, 262 MAX8997_HAPTIC_REG_GENERAL = 0x00,
199 MAX8997_HAPTIC_REG_CONF1 = 0x01, 263 MAX8997_HAPTIC_REG_CONF1 = 0x01,
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 1d4a4fe6ac33..cf815577bd68 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -78,21 +78,6 @@ struct max8997_regulator_data {
78 struct device_node *reg_node; 78 struct device_node *reg_node;
79}; 79};
80 80
81enum max8997_muic_usb_type {
82 MAX8997_USB_HOST,
83 MAX8997_USB_DEVICE,
84};
85
86enum max8997_muic_charger_type {
87 MAX8997_CHARGER_TYPE_NONE = 0,
88 MAX8997_CHARGER_TYPE_USB,
89 MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT,
90 MAX8997_CHARGER_TYPE_DEDICATED_CHG,
91 MAX8997_CHARGER_TYPE_500MA,
92 MAX8997_CHARGER_TYPE_1A,
93 MAX8997_CHARGER_TYPE_DEAD_BATTERY = 7,
94};
95
96struct max8997_muic_reg_data { 81struct max8997_muic_reg_data {
97 u8 addr; 82 u8 addr;
98 u8 data; 83 u8 data;
@@ -107,6 +92,16 @@ struct max8997_muic_reg_data {
107struct max8997_muic_platform_data { 92struct max8997_muic_platform_data {
108 struct max8997_muic_reg_data *init_data; 93 struct max8997_muic_reg_data *init_data;
109 int num_init_data; 94 int num_init_data;
95
96 /* Check cable state after certain delay */
97 int detcable_delay_ms;
98
99 /*
100 * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB
101 * h/w path of COMP2/COMN1 on CONTROL1 register.
102 */
103 int path_usb;
104 int path_uart;
110}; 105};
111 106
112enum max8997_haptic_motor_type { 107enum max8997_haptic_motor_type {
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 29f6616e12f0..a4d13d7cd001 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -2789,4 +2789,56 @@ enum usb_irq_events {
2789#define PALMAS_GPADC_TRIM15 0xE 2789#define PALMAS_GPADC_TRIM15 0xE
2790#define PALMAS_GPADC_TRIM16 0xF 2790#define PALMAS_GPADC_TRIM16 0xF
2791 2791
2792static inline int palmas_read(struct palmas *palmas, unsigned int base,
2793 unsigned int reg, unsigned int *val)
2794{
2795 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2796 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2797
2798 return regmap_read(palmas->regmap[slave_id], addr, val);
2799}
2800
2801static inline int palmas_write(struct palmas *palmas, unsigned int base,
2802 unsigned int reg, unsigned int value)
2803{
2804 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2805 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2806
2807 return regmap_write(palmas->regmap[slave_id], addr, value);
2808}
2809
2810static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2811 unsigned int reg, const void *val, size_t val_count)
2812{
2813 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2814 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2815
2816 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2817 val, val_count);
2818}
2819
2820static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2821 unsigned int reg, void *val, size_t val_count)
2822{
2823 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2824 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2825
2826 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2827 val, val_count);
2828}
2829
2830static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2831 unsigned int reg, unsigned int mask, unsigned int val)
2832{
2833 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2834 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2835
2836 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2837}
2838
2839static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2840{
2841 return regmap_irq_get_virq(palmas->irq_data, irq);
2842}
2843
2792#endif /* __LINUX_MFD_PALMAS_H */ 2844#endif /* __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 4b117a3f54d4..26ea7f1b7caf 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -465,7 +465,7 @@
465#define SD_RSP_TYPE_R6 0x01 465#define SD_RSP_TYPE_R6 0x01
466#define SD_RSP_TYPE_R7 0x01 466#define SD_RSP_TYPE_R7 0x01
467 467
468/* SD_CONFIURE3 */ 468/* SD_CONFIGURE3 */
469#define SD_RSP_80CLK_TIMEOUT_EN 0x01 469#define SD_RSP_80CLK_TIMEOUT_EN 0x01
470 470
471/* Card Transfer Reset Register */ 471/* Card Transfer Reset Register */
@@ -581,8 +581,11 @@
581#define CARD_GPIO_DIR 0xFD57 581#define CARD_GPIO_DIR 0xFD57
582#define CARD_GPIO 0xFD58 582#define CARD_GPIO 0xFD58
583#define CARD_DATA_SOURCE 0xFD5B 583#define CARD_DATA_SOURCE 0xFD5B
584#define SD30_CLK_DRIVE_SEL 0xFD5A
584#define CARD_SELECT 0xFD5C 585#define CARD_SELECT 0xFD5C
585#define SD30_DRIVE_SEL 0xFD5E 586#define SD30_DRIVE_SEL 0xFD5E
587#define SD30_CMD_DRIVE_SEL 0xFD5E
588#define SD30_DAT_DRIVE_SEL 0xFD5F
586#define CARD_CLK_EN 0xFD69 589#define CARD_CLK_EN 0xFD69
587#define SDIO_CTRL 0xFD6B 590#define SDIO_CTRL 0xFD6B
588#define CD_PAD_CTL 0xFD73 591#define CD_PAD_CTL 0xFD73
@@ -655,6 +658,8 @@
655#define MSGTXDATA3 0xFE47 658#define MSGTXDATA3 0xFE47
656#define MSGTXCTL 0xFE48 659#define MSGTXCTL 0xFE48
657#define PETXCFG 0xFE49 660#define PETXCFG 0xFE49
661#define LTR_CTL 0xFE4A
662#define OBFF_CFG 0xFE4C
658 663
659#define CDRESUMECTL 0xFE52 664#define CDRESUMECTL 0xFE52
660#define WAKE_SEL_CTL 0xFE54 665#define WAKE_SEL_CTL 0xFE54
@@ -735,6 +740,7 @@ struct rtsx_pcr {
735 740
736 unsigned int card_inserted; 741 unsigned int card_inserted;
737 unsigned int card_removed; 742 unsigned int card_removed;
743 unsigned int card_exist;
738 744
739 struct delayed_work carddet_work; 745 struct delayed_work carddet_work;
740 struct delayed_work idle_work; 746 struct delayed_work idle_work;
@@ -799,6 +805,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
799 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); 805 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
800int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card); 806int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
801int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card); 807int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
808int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
802int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage); 809int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
803unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr); 810unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
804void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr); 811void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/core.h
index b50c38f8bc48..f0f4de3b4ccc 100644
--- a/include/linux/mfd/samsung/core.h
+++ b/include/linux/mfd/samsung/core.h
@@ -26,6 +26,7 @@ enum sec_device_type {
26/** 26/**
27 * struct sec_pmic_dev - s5m87xx master device for sub-drivers 27 * struct sec_pmic_dev - s5m87xx master device for sub-drivers
28 * @dev: master device of the chip (can be used to access platform data) 28 * @dev: master device of the chip (can be used to access platform data)
29 * @pdata: pointer to private data used to pass platform data to child
29 * @i2c: i2c client private data for regulator 30 * @i2c: i2c client private data for regulator
30 * @rtc: i2c client private data for rtc 31 * @rtc: i2c client private data for rtc
31 * @iolock: mutex for serializing io access 32 * @iolock: mutex for serializing io access
@@ -39,6 +40,7 @@ enum sec_device_type {
39 */ 40 */
40struct sec_pmic_dev { 41struct sec_pmic_dev {
41 struct device *dev; 42 struct device *dev;
43 struct sec_platform_data *pdata;
42 struct regmap *regmap; 44 struct regmap *regmap;
43 struct i2c_client *i2c; 45 struct i2c_client *i2c;
44 struct i2c_client *rtc; 46 struct i2c_client *rtc;
@@ -82,11 +84,11 @@ struct sec_platform_data {
82 84
83 int buck_gpios[3]; 85 int buck_gpios[3];
84 int buck_ds[3]; 86 int buck_ds[3];
85 int buck2_voltage[8]; 87 unsigned int buck2_voltage[8];
86 bool buck2_gpiodvs; 88 bool buck2_gpiodvs;
87 int buck3_voltage[8]; 89 unsigned int buck3_voltage[8];
88 bool buck3_gpiodvs; 90 bool buck3_gpiodvs;
89 int buck4_voltage[8]; 91 unsigned int buck4_voltage[8];
90 bool buck4_gpiodvs; 92 bool buck4_gpiodvs;
91 93
92 int buck_set1; 94 int buck_set1;
@@ -127,6 +129,7 @@ struct sec_platform_data {
127struct sec_regulator_data { 129struct sec_regulator_data {
128 int id; 130 int id;
129 struct regulator_init_data *initdata; 131 struct regulator_init_data *initdata;
132 struct device_node *reg_node;
130}; 133};
131 134
132/* 135/*
@@ -136,7 +139,7 @@ struct sec_regulator_data {
136 */ 139 */
137struct sec_opmode_data { 140struct sec_opmode_data {
138 int id; 141 int id;
139 int mode; 142 unsigned int mode;
140}; 143};
141 144
142/* 145/*
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index d83af39815ab..99bf3e665997 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -65,12 +65,6 @@
65 */ 65 */
66#define TMIO_MMC_SDIO_IRQ (1 << 2) 66#define TMIO_MMC_SDIO_IRQ (1 << 2)
67/* 67/*
68 * Some platforms can detect card insertion events with controller powered
69 * down, using a GPIO IRQ, in which case they have to fill in cd_irq, cd_gpio,
70 * and cd_flags fields of struct tmio_mmc_data.
71 */
72#define TMIO_MMC_HAS_COLD_CD (1 << 3)
73/*
74 * Some controllers require waiting for the SD bus to become 68 * Some controllers require waiting for the SD bus to become
75 * idle before writing to some registers. 69 * idle before writing to some registers.
76 */ 70 */
@@ -117,18 +111,6 @@ struct tmio_mmc_data {
117}; 111};
118 112
119/* 113/*
120 * This function is deprecated and will be removed soon. Please, convert your
121 * platform to use drivers/mmc/core/cd-gpio.c
122 */
123#include <linux/mmc/host.h>
124static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
125{
126 if (pdata)
127 mmc_detect_change(dev_get_drvdata(pdata->dev),
128 msecs_to_jiffies(100));
129}
130
131/*
132 * data for the NAND controller 114 * data for the NAND controller
133 */ 115 */
134struct tmio_nand_data { 116struct tmio_nand_data {
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 11:04:38 -0400