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Diffstat (limited to 'include/linux/mfd/wm8400-private.h')
-rw-r--r-- | include/linux/mfd/wm8400-private.h | 936 |
1 files changed, 936 insertions, 0 deletions
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h new file mode 100644 index 000000000000..2aab4e93a5c9 --- /dev/null +++ b/include/linux/mfd/wm8400-private.h | |||
@@ -0,0 +1,936 @@ | |||
1 | /* | ||
2 | * wm8400 private definitions. | ||
3 | * | ||
4 | * Copyright 2008 Wolfson Microelectronics plc | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
19 | */ | ||
20 | |||
21 | #ifndef __LINUX_MFD_WM8400_PRIV_H | ||
22 | #define __LINUX_MFD_WM8400_PRIV_H | ||
23 | |||
24 | #include <linux/mfd/wm8400.h> | ||
25 | #include <linux/mutex.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | |||
28 | #define WM8400_REGISTER_COUNT 0x55 | ||
29 | |||
30 | struct wm8400 { | ||
31 | struct device *dev; | ||
32 | |||
33 | int (*read_dev)(void *data, char reg, int count, u16 *dst); | ||
34 | int (*write_dev)(void *data, char reg, int count, const u16 *src); | ||
35 | |||
36 | struct mutex io_lock; | ||
37 | void *io_data; | ||
38 | |||
39 | u16 reg_cache[WM8400_REGISTER_COUNT]; | ||
40 | |||
41 | struct platform_device regulators[6]; | ||
42 | }; | ||
43 | |||
44 | /* | ||
45 | * Register values. | ||
46 | */ | ||
47 | #define WM8400_RESET_ID 0x00 | ||
48 | #define WM8400_ID 0x01 | ||
49 | #define WM8400_POWER_MANAGEMENT_1 0x02 | ||
50 | #define WM8400_POWER_MANAGEMENT_2 0x03 | ||
51 | #define WM8400_POWER_MANAGEMENT_3 0x04 | ||
52 | #define WM8400_AUDIO_INTERFACE_1 0x05 | ||
53 | #define WM8400_AUDIO_INTERFACE_2 0x06 | ||
54 | #define WM8400_CLOCKING_1 0x07 | ||
55 | #define WM8400_CLOCKING_2 0x08 | ||
56 | #define WM8400_AUDIO_INTERFACE_3 0x09 | ||
57 | #define WM8400_AUDIO_INTERFACE_4 0x0A | ||
58 | #define WM8400_DAC_CTRL 0x0B | ||
59 | #define WM8400_LEFT_DAC_DIGITAL_VOLUME 0x0C | ||
60 | #define WM8400_RIGHT_DAC_DIGITAL_VOLUME 0x0D | ||
61 | #define WM8400_DIGITAL_SIDE_TONE 0x0E | ||
62 | #define WM8400_ADC_CTRL 0x0F | ||
63 | #define WM8400_LEFT_ADC_DIGITAL_VOLUME 0x10 | ||
64 | #define WM8400_RIGHT_ADC_DIGITAL_VOLUME 0x11 | ||
65 | #define WM8400_GPIO_CTRL_1 0x12 | ||
66 | #define WM8400_GPIO1_GPIO2 0x13 | ||
67 | #define WM8400_GPIO3_GPIO4 0x14 | ||
68 | #define WM8400_GPIO5_GPIO6 0x15 | ||
69 | #define WM8400_GPIOCTRL_2 0x16 | ||
70 | #define WM8400_GPIO_POL 0x17 | ||
71 | #define WM8400_LEFT_LINE_INPUT_1_2_VOLUME 0x18 | ||
72 | #define WM8400_LEFT_LINE_INPUT_3_4_VOLUME 0x19 | ||
73 | #define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A | ||
74 | #define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B | ||
75 | #define WM8400_LEFT_OUTPUT_VOLUME 0x1C | ||
76 | #define WM8400_RIGHT_OUTPUT_VOLUME 0x1D | ||
77 | #define WM8400_LINE_OUTPUTS_VOLUME 0x1E | ||
78 | #define WM8400_OUT3_4_VOLUME 0x1F | ||
79 | #define WM8400_LEFT_OPGA_VOLUME 0x20 | ||
80 | #define WM8400_RIGHT_OPGA_VOLUME 0x21 | ||
81 | #define WM8400_SPEAKER_VOLUME 0x22 | ||
82 | #define WM8400_CLASSD1 0x23 | ||
83 | #define WM8400_CLASSD3 0x25 | ||
84 | #define WM8400_INPUT_MIXER1 0x27 | ||
85 | #define WM8400_INPUT_MIXER2 0x28 | ||
86 | #define WM8400_INPUT_MIXER3 0x29 | ||
87 | #define WM8400_INPUT_MIXER4 0x2A | ||
88 | #define WM8400_INPUT_MIXER5 0x2B | ||
89 | #define WM8400_INPUT_MIXER6 0x2C | ||
90 | #define WM8400_OUTPUT_MIXER1 0x2D | ||
91 | #define WM8400_OUTPUT_MIXER2 0x2E | ||
92 | #define WM8400_OUTPUT_MIXER3 0x2F | ||
93 | #define WM8400_OUTPUT_MIXER4 0x30 | ||
94 | #define WM8400_OUTPUT_MIXER5 0x31 | ||
95 | #define WM8400_OUTPUT_MIXER6 0x32 | ||
96 | #define WM8400_OUT3_4_MIXER 0x33 | ||
97 | #define WM8400_LINE_MIXER1 0x34 | ||
98 | #define WM8400_LINE_MIXER2 0x35 | ||
99 | #define WM8400_SPEAKER_MIXER 0x36 | ||
100 | #define WM8400_ADDITIONAL_CONTROL 0x37 | ||
101 | #define WM8400_ANTIPOP1 0x38 | ||
102 | #define WM8400_ANTIPOP2 0x39 | ||
103 | #define WM8400_MICBIAS 0x3A | ||
104 | #define WM8400_FLL_CONTROL_1 0x3C | ||
105 | #define WM8400_FLL_CONTROL_2 0x3D | ||
106 | #define WM8400_FLL_CONTROL_3 0x3E | ||
107 | #define WM8400_FLL_CONTROL_4 0x3F | ||
108 | #define WM8400_LDO1_CONTROL 0x41 | ||
109 | #define WM8400_LDO2_CONTROL 0x42 | ||
110 | #define WM8400_LDO3_CONTROL 0x43 | ||
111 | #define WM8400_LDO4_CONTROL 0x44 | ||
112 | #define WM8400_DCDC1_CONTROL_1 0x46 | ||
113 | #define WM8400_DCDC1_CONTROL_2 0x47 | ||
114 | #define WM8400_DCDC2_CONTROL_1 0x48 | ||
115 | #define WM8400_DCDC2_CONTROL_2 0x49 | ||
116 | #define WM8400_INTERFACE 0x4B | ||
117 | #define WM8400_PM_GENERAL 0x4C | ||
118 | #define WM8400_PM_SHUTDOWN_CONTROL 0x4E | ||
119 | #define WM8400_INTERRUPT_STATUS_1 0x4F | ||
120 | #define WM8400_INTERRUPT_STATUS_1_MASK 0x50 | ||
121 | #define WM8400_INTERRUPT_LEVELS 0x51 | ||
122 | #define WM8400_SHUTDOWN_REASON 0x52 | ||
123 | #define WM8400_LINE_CIRCUITS 0x54 | ||
124 | |||
125 | /* | ||
126 | * Field Definitions. | ||
127 | */ | ||
128 | |||
129 | /* | ||
130 | * R0 (0x00) - Reset/ID | ||
131 | */ | ||
132 | #define WM8400_SW_RESET_CHIP_ID_MASK 0xFFFF /* SW_RESET/CHIP_ID - [15:0] */ | ||
133 | #define WM8400_SW_RESET_CHIP_ID_SHIFT 0 /* SW_RESET/CHIP_ID - [15:0] */ | ||
134 | #define WM8400_SW_RESET_CHIP_ID_WIDTH 16 /* SW_RESET/CHIP_ID - [15:0] */ | ||
135 | |||
136 | /* | ||
137 | * R1 (0x01) - ID | ||
138 | */ | ||
139 | #define WM8400_CHIP_REV_MASK 0x7000 /* CHIP_REV - [14:12] */ | ||
140 | #define WM8400_CHIP_REV_SHIFT 12 /* CHIP_REV - [14:12] */ | ||
141 | #define WM8400_CHIP_REV_WIDTH 3 /* CHIP_REV - [14:12] */ | ||
142 | |||
143 | /* | ||
144 | * R18 (0x12) - GPIO CTRL 1 | ||
145 | */ | ||
146 | #define WM8400_IRQ 0x1000 /* IRQ */ | ||
147 | #define WM8400_IRQ_MASK 0x1000 /* IRQ */ | ||
148 | #define WM8400_IRQ_SHIFT 12 /* IRQ */ | ||
149 | #define WM8400_IRQ_WIDTH 1 /* IRQ */ | ||
150 | #define WM8400_TEMPOK 0x0800 /* TEMPOK */ | ||
151 | #define WM8400_TEMPOK_MASK 0x0800 /* TEMPOK */ | ||
152 | #define WM8400_TEMPOK_SHIFT 11 /* TEMPOK */ | ||
153 | #define WM8400_TEMPOK_WIDTH 1 /* TEMPOK */ | ||
154 | #define WM8400_MIC1SHRT 0x0400 /* MIC1SHRT */ | ||
155 | #define WM8400_MIC1SHRT_MASK 0x0400 /* MIC1SHRT */ | ||
156 | #define WM8400_MIC1SHRT_SHIFT 10 /* MIC1SHRT */ | ||
157 | #define WM8400_MIC1SHRT_WIDTH 1 /* MIC1SHRT */ | ||
158 | #define WM8400_MIC1DET 0x0200 /* MIC1DET */ | ||
159 | #define WM8400_MIC1DET_MASK 0x0200 /* MIC1DET */ | ||
160 | #define WM8400_MIC1DET_SHIFT 9 /* MIC1DET */ | ||
161 | #define WM8400_MIC1DET_WIDTH 1 /* MIC1DET */ | ||
162 | #define WM8400_FLL_LCK 0x0100 /* FLL_LCK */ | ||
163 | #define WM8400_FLL_LCK_MASK 0x0100 /* FLL_LCK */ | ||
164 | #define WM8400_FLL_LCK_SHIFT 8 /* FLL_LCK */ | ||
165 | #define WM8400_FLL_LCK_WIDTH 1 /* FLL_LCK */ | ||
166 | #define WM8400_GPIO_STATUS_MASK 0x00FF /* GPIO_STATUS - [7:0] */ | ||
167 | #define WM8400_GPIO_STATUS_SHIFT 0 /* GPIO_STATUS - [7:0] */ | ||
168 | #define WM8400_GPIO_STATUS_WIDTH 8 /* GPIO_STATUS - [7:0] */ | ||
169 | |||
170 | /* | ||
171 | * R19 (0x13) - GPIO1 & GPIO2 | ||
172 | */ | ||
173 | #define WM8400_GPIO2_DEB_ENA 0x8000 /* GPIO2_DEB_ENA */ | ||
174 | #define WM8400_GPIO2_DEB_ENA_MASK 0x8000 /* GPIO2_DEB_ENA */ | ||
175 | #define WM8400_GPIO2_DEB_ENA_SHIFT 15 /* GPIO2_DEB_ENA */ | ||
176 | #define WM8400_GPIO2_DEB_ENA_WIDTH 1 /* GPIO2_DEB_ENA */ | ||
177 | #define WM8400_GPIO2_IRQ_ENA 0x4000 /* GPIO2_IRQ_ENA */ | ||
178 | #define WM8400_GPIO2_IRQ_ENA_MASK 0x4000 /* GPIO2_IRQ_ENA */ | ||
179 | #define WM8400_GPIO2_IRQ_ENA_SHIFT 14 /* GPIO2_IRQ_ENA */ | ||
180 | #define WM8400_GPIO2_IRQ_ENA_WIDTH 1 /* GPIO2_IRQ_ENA */ | ||
181 | #define WM8400_GPIO2_PU 0x2000 /* GPIO2_PU */ | ||
182 | #define WM8400_GPIO2_PU_MASK 0x2000 /* GPIO2_PU */ | ||
183 | #define WM8400_GPIO2_PU_SHIFT 13 /* GPIO2_PU */ | ||
184 | #define WM8400_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ | ||
185 | #define WM8400_GPIO2_PD 0x1000 /* GPIO2_PD */ | ||
186 | #define WM8400_GPIO2_PD_MASK 0x1000 /* GPIO2_PD */ | ||
187 | #define WM8400_GPIO2_PD_SHIFT 12 /* GPIO2_PD */ | ||
188 | #define WM8400_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ | ||
189 | #define WM8400_GPIO2_SEL_MASK 0x0F00 /* GPIO2_SEL - [11:8] */ | ||
190 | #define WM8400_GPIO2_SEL_SHIFT 8 /* GPIO2_SEL - [11:8] */ | ||
191 | #define WM8400_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [11:8] */ | ||
192 | #define WM8400_GPIO1_DEB_ENA 0x0080 /* GPIO1_DEB_ENA */ | ||
193 | #define WM8400_GPIO1_DEB_ENA_MASK 0x0080 /* GPIO1_DEB_ENA */ | ||
194 | #define WM8400_GPIO1_DEB_ENA_SHIFT 7 /* GPIO1_DEB_ENA */ | ||
195 | #define WM8400_GPIO1_DEB_ENA_WIDTH 1 /* GPIO1_DEB_ENA */ | ||
196 | #define WM8400_GPIO1_IRQ_ENA 0x0040 /* GPIO1_IRQ_ENA */ | ||
197 | #define WM8400_GPIO1_IRQ_ENA_MASK 0x0040 /* GPIO1_IRQ_ENA */ | ||
198 | #define WM8400_GPIO1_IRQ_ENA_SHIFT 6 /* GPIO1_IRQ_ENA */ | ||
199 | #define WM8400_GPIO1_IRQ_ENA_WIDTH 1 /* GPIO1_IRQ_ENA */ | ||
200 | #define WM8400_GPIO1_PU 0x0020 /* GPIO1_PU */ | ||
201 | #define WM8400_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ | ||
202 | #define WM8400_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ | ||
203 | #define WM8400_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ | ||
204 | #define WM8400_GPIO1_PD 0x0010 /* GPIO1_PD */ | ||
205 | #define WM8400_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ | ||
206 | #define WM8400_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ | ||
207 | #define WM8400_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ | ||
208 | #define WM8400_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ | ||
209 | #define WM8400_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ | ||
210 | #define WM8400_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ | ||
211 | |||
212 | /* | ||
213 | * R20 (0x14) - GPIO3 & GPIO4 | ||
214 | */ | ||
215 | #define WM8400_GPIO4_DEB_ENA 0x8000 /* GPIO4_DEB_ENA */ | ||
216 | #define WM8400_GPIO4_DEB_ENA_MASK 0x8000 /* GPIO4_DEB_ENA */ | ||
217 | #define WM8400_GPIO4_DEB_ENA_SHIFT 15 /* GPIO4_DEB_ENA */ | ||
218 | #define WM8400_GPIO4_DEB_ENA_WIDTH 1 /* GPIO4_DEB_ENA */ | ||
219 | #define WM8400_GPIO4_IRQ_ENA 0x4000 /* GPIO4_IRQ_ENA */ | ||
220 | #define WM8400_GPIO4_IRQ_ENA_MASK 0x4000 /* GPIO4_IRQ_ENA */ | ||
221 | #define WM8400_GPIO4_IRQ_ENA_SHIFT 14 /* GPIO4_IRQ_ENA */ | ||
222 | #define WM8400_GPIO4_IRQ_ENA_WIDTH 1 /* GPIO4_IRQ_ENA */ | ||
223 | #define WM8400_GPIO4_PU 0x2000 /* GPIO4_PU */ | ||
224 | #define WM8400_GPIO4_PU_MASK 0x2000 /* GPIO4_PU */ | ||
225 | #define WM8400_GPIO4_PU_SHIFT 13 /* GPIO4_PU */ | ||
226 | #define WM8400_GPIO4_PU_WIDTH 1 /* GPIO4_PU */ | ||
227 | #define WM8400_GPIO4_PD 0x1000 /* GPIO4_PD */ | ||
228 | #define WM8400_GPIO4_PD_MASK 0x1000 /* GPIO4_PD */ | ||
229 | #define WM8400_GPIO4_PD_SHIFT 12 /* GPIO4_PD */ | ||
230 | #define WM8400_GPIO4_PD_WIDTH 1 /* GPIO4_PD */ | ||
231 | #define WM8400_GPIO4_SEL_MASK 0x0F00 /* GPIO4_SEL - [11:8] */ | ||
232 | #define WM8400_GPIO4_SEL_SHIFT 8 /* GPIO4_SEL - [11:8] */ | ||
233 | #define WM8400_GPIO4_SEL_WIDTH 4 /* GPIO4_SEL - [11:8] */ | ||
234 | #define WM8400_GPIO3_DEB_ENA 0x0080 /* GPIO3_DEB_ENA */ | ||
235 | #define WM8400_GPIO3_DEB_ENA_MASK 0x0080 /* GPIO3_DEB_ENA */ | ||
236 | #define WM8400_GPIO3_DEB_ENA_SHIFT 7 /* GPIO3_DEB_ENA */ | ||
237 | #define WM8400_GPIO3_DEB_ENA_WIDTH 1 /* GPIO3_DEB_ENA */ | ||
238 | #define WM8400_GPIO3_IRQ_ENA 0x0040 /* GPIO3_IRQ_ENA */ | ||
239 | #define WM8400_GPIO3_IRQ_ENA_MASK 0x0040 /* GPIO3_IRQ_ENA */ | ||
240 | #define WM8400_GPIO3_IRQ_ENA_SHIFT 6 /* GPIO3_IRQ_ENA */ | ||
241 | #define WM8400_GPIO3_IRQ_ENA_WIDTH 1 /* GPIO3_IRQ_ENA */ | ||
242 | #define WM8400_GPIO3_PU 0x0020 /* GPIO3_PU */ | ||
243 | #define WM8400_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ | ||
244 | #define WM8400_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ | ||
245 | #define WM8400_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ | ||
246 | #define WM8400_GPIO3_PD 0x0010 /* GPIO3_PD */ | ||
247 | #define WM8400_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ | ||
248 | #define WM8400_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ | ||
249 | #define WM8400_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ | ||
250 | #define WM8400_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ | ||
251 | #define WM8400_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ | ||
252 | #define WM8400_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ | ||
253 | |||
254 | /* | ||
255 | * R21 (0x15) - GPIO5 & GPIO6 | ||
256 | */ | ||
257 | #define WM8400_GPIO6_DEB_ENA 0x8000 /* GPIO6_DEB_ENA */ | ||
258 | #define WM8400_GPIO6_DEB_ENA_MASK 0x8000 /* GPIO6_DEB_ENA */ | ||
259 | #define WM8400_GPIO6_DEB_ENA_SHIFT 15 /* GPIO6_DEB_ENA */ | ||
260 | #define WM8400_GPIO6_DEB_ENA_WIDTH 1 /* GPIO6_DEB_ENA */ | ||
261 | #define WM8400_GPIO6_IRQ_ENA 0x4000 /* GPIO6_IRQ_ENA */ | ||
262 | #define WM8400_GPIO6_IRQ_ENA_MASK 0x4000 /* GPIO6_IRQ_ENA */ | ||
263 | #define WM8400_GPIO6_IRQ_ENA_SHIFT 14 /* GPIO6_IRQ_ENA */ | ||
264 | #define WM8400_GPIO6_IRQ_ENA_WIDTH 1 /* GPIO6_IRQ_ENA */ | ||
265 | #define WM8400_GPIO6_PU 0x2000 /* GPIO6_PU */ | ||
266 | #define WM8400_GPIO6_PU_MASK 0x2000 /* GPIO6_PU */ | ||
267 | #define WM8400_GPIO6_PU_SHIFT 13 /* GPIO6_PU */ | ||
268 | #define WM8400_GPIO6_PU_WIDTH 1 /* GPIO6_PU */ | ||
269 | #define WM8400_GPIO6_PD 0x1000 /* GPIO6_PD */ | ||
270 | #define WM8400_GPIO6_PD_MASK 0x1000 /* GPIO6_PD */ | ||
271 | #define WM8400_GPIO6_PD_SHIFT 12 /* GPIO6_PD */ | ||
272 | #define WM8400_GPIO6_PD_WIDTH 1 /* GPIO6_PD */ | ||
273 | #define WM8400_GPIO6_SEL_MASK 0x0F00 /* GPIO6_SEL - [11:8] */ | ||
274 | #define WM8400_GPIO6_SEL_SHIFT 8 /* GPIO6_SEL - [11:8] */ | ||
275 | #define WM8400_GPIO6_SEL_WIDTH 4 /* GPIO6_SEL - [11:8] */ | ||
276 | #define WM8400_GPIO5_DEB_ENA 0x0080 /* GPIO5_DEB_ENA */ | ||
277 | #define WM8400_GPIO5_DEB_ENA_MASK 0x0080 /* GPIO5_DEB_ENA */ | ||
278 | #define WM8400_GPIO5_DEB_ENA_SHIFT 7 /* GPIO5_DEB_ENA */ | ||
279 | #define WM8400_GPIO5_DEB_ENA_WIDTH 1 /* GPIO5_DEB_ENA */ | ||
280 | #define WM8400_GPIO5_IRQ_ENA 0x0040 /* GPIO5_IRQ_ENA */ | ||
281 | #define WM8400_GPIO5_IRQ_ENA_MASK 0x0040 /* GPIO5_IRQ_ENA */ | ||
282 | #define WM8400_GPIO5_IRQ_ENA_SHIFT 6 /* GPIO5_IRQ_ENA */ | ||
283 | #define WM8400_GPIO5_IRQ_ENA_WIDTH 1 /* GPIO5_IRQ_ENA */ | ||
284 | #define WM8400_GPIO5_PU 0x0020 /* GPIO5_PU */ | ||
285 | #define WM8400_GPIO5_PU_MASK 0x0020 /* GPIO5_PU */ | ||
286 | #define WM8400_GPIO5_PU_SHIFT 5 /* GPIO5_PU */ | ||
287 | #define WM8400_GPIO5_PU_WIDTH 1 /* GPIO5_PU */ | ||
288 | #define WM8400_GPIO5_PD 0x0010 /* GPIO5_PD */ | ||
289 | #define WM8400_GPIO5_PD_MASK 0x0010 /* GPIO5_PD */ | ||
290 | #define WM8400_GPIO5_PD_SHIFT 4 /* GPIO5_PD */ | ||
291 | #define WM8400_GPIO5_PD_WIDTH 1 /* GPIO5_PD */ | ||
292 | #define WM8400_GPIO5_SEL_MASK 0x000F /* GPIO5_SEL - [3:0] */ | ||
293 | #define WM8400_GPIO5_SEL_SHIFT 0 /* GPIO5_SEL - [3:0] */ | ||
294 | #define WM8400_GPIO5_SEL_WIDTH 4 /* GPIO5_SEL - [3:0] */ | ||
295 | |||
296 | /* | ||
297 | * R22 (0x16) - GPIOCTRL 2 | ||
298 | */ | ||
299 | #define WM8400_TEMPOK_IRQ_ENA 0x0800 /* TEMPOK_IRQ_ENA */ | ||
300 | #define WM8400_TEMPOK_IRQ_ENA_MASK 0x0800 /* TEMPOK_IRQ_ENA */ | ||
301 | #define WM8400_TEMPOK_IRQ_ENA_SHIFT 11 /* TEMPOK_IRQ_ENA */ | ||
302 | #define WM8400_TEMPOK_IRQ_ENA_WIDTH 1 /* TEMPOK_IRQ_ENA */ | ||
303 | #define WM8400_MIC1SHRT_IRQ_ENA 0x0400 /* MIC1SHRT_IRQ_ENA */ | ||
304 | #define WM8400_MIC1SHRT_IRQ_ENA_MASK 0x0400 /* MIC1SHRT_IRQ_ENA */ | ||
305 | #define WM8400_MIC1SHRT_IRQ_ENA_SHIFT 10 /* MIC1SHRT_IRQ_ENA */ | ||
306 | #define WM8400_MIC1SHRT_IRQ_ENA_WIDTH 1 /* MIC1SHRT_IRQ_ENA */ | ||
307 | #define WM8400_MIC1DET_IRQ_ENA 0x0200 /* MIC1DET_IRQ_ENA */ | ||
308 | #define WM8400_MIC1DET_IRQ_ENA_MASK 0x0200 /* MIC1DET_IRQ_ENA */ | ||
309 | #define WM8400_MIC1DET_IRQ_ENA_SHIFT 9 /* MIC1DET_IRQ_ENA */ | ||
310 | #define WM8400_MIC1DET_IRQ_ENA_WIDTH 1 /* MIC1DET_IRQ_ENA */ | ||
311 | #define WM8400_FLL_LCK_IRQ_ENA 0x0100 /* FLL_LCK_IRQ_ENA */ | ||
312 | #define WM8400_FLL_LCK_IRQ_ENA_MASK 0x0100 /* FLL_LCK_IRQ_ENA */ | ||
313 | #define WM8400_FLL_LCK_IRQ_ENA_SHIFT 8 /* FLL_LCK_IRQ_ENA */ | ||
314 | #define WM8400_FLL_LCK_IRQ_ENA_WIDTH 1 /* FLL_LCK_IRQ_ENA */ | ||
315 | #define WM8400_GPI8_DEB_ENA 0x0080 /* GPI8_DEB_ENA */ | ||
316 | #define WM8400_GPI8_DEB_ENA_MASK 0x0080 /* GPI8_DEB_ENA */ | ||
317 | #define WM8400_GPI8_DEB_ENA_SHIFT 7 /* GPI8_DEB_ENA */ | ||
318 | #define WM8400_GPI8_DEB_ENA_WIDTH 1 /* GPI8_DEB_ENA */ | ||
319 | #define WM8400_GPI8_IRQ_ENA 0x0040 /* GPI8_IRQ_ENA */ | ||
320 | #define WM8400_GPI8_IRQ_ENA_MASK 0x0040 /* GPI8_IRQ_ENA */ | ||
321 | #define WM8400_GPI8_IRQ_ENA_SHIFT 6 /* GPI8_IRQ_ENA */ | ||
322 | #define WM8400_GPI8_IRQ_ENA_WIDTH 1 /* GPI8_IRQ_ENA */ | ||
323 | #define WM8400_GPI8_ENA 0x0010 /* GPI8_ENA */ | ||
324 | #define WM8400_GPI8_ENA_MASK 0x0010 /* GPI8_ENA */ | ||
325 | #define WM8400_GPI8_ENA_SHIFT 4 /* GPI8_ENA */ | ||
326 | #define WM8400_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ | ||
327 | #define WM8400_GPI7_DEB_ENA 0x0008 /* GPI7_DEB_ENA */ | ||
328 | #define WM8400_GPI7_DEB_ENA_MASK 0x0008 /* GPI7_DEB_ENA */ | ||
329 | #define WM8400_GPI7_DEB_ENA_SHIFT 3 /* GPI7_DEB_ENA */ | ||
330 | #define WM8400_GPI7_DEB_ENA_WIDTH 1 /* GPI7_DEB_ENA */ | ||
331 | #define WM8400_GPI7_IRQ_ENA 0x0004 /* GPI7_IRQ_ENA */ | ||
332 | #define WM8400_GPI7_IRQ_ENA_MASK 0x0004 /* GPI7_IRQ_ENA */ | ||
333 | #define WM8400_GPI7_IRQ_ENA_SHIFT 2 /* GPI7_IRQ_ENA */ | ||
334 | #define WM8400_GPI7_IRQ_ENA_WIDTH 1 /* GPI7_IRQ_ENA */ | ||
335 | #define WM8400_GPI7_ENA 0x0001 /* GPI7_ENA */ | ||
336 | #define WM8400_GPI7_ENA_MASK 0x0001 /* GPI7_ENA */ | ||
337 | #define WM8400_GPI7_ENA_SHIFT 0 /* GPI7_ENA */ | ||
338 | #define WM8400_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ | ||
339 | |||
340 | /* | ||
341 | * R23 (0x17) - GPIO_POL | ||
342 | */ | ||
343 | #define WM8400_IRQ_INV 0x1000 /* IRQ_INV */ | ||
344 | #define WM8400_IRQ_INV_MASK 0x1000 /* IRQ_INV */ | ||
345 | #define WM8400_IRQ_INV_SHIFT 12 /* IRQ_INV */ | ||
346 | #define WM8400_IRQ_INV_WIDTH 1 /* IRQ_INV */ | ||
347 | #define WM8400_TEMPOK_POL 0x0800 /* TEMPOK_POL */ | ||
348 | #define WM8400_TEMPOK_POL_MASK 0x0800 /* TEMPOK_POL */ | ||
349 | #define WM8400_TEMPOK_POL_SHIFT 11 /* TEMPOK_POL */ | ||
350 | #define WM8400_TEMPOK_POL_WIDTH 1 /* TEMPOK_POL */ | ||
351 | #define WM8400_MIC1SHRT_POL 0x0400 /* MIC1SHRT_POL */ | ||
352 | #define WM8400_MIC1SHRT_POL_MASK 0x0400 /* MIC1SHRT_POL */ | ||
353 | #define WM8400_MIC1SHRT_POL_SHIFT 10 /* MIC1SHRT_POL */ | ||
354 | #define WM8400_MIC1SHRT_POL_WIDTH 1 /* MIC1SHRT_POL */ | ||
355 | #define WM8400_MIC1DET_POL 0x0200 /* MIC1DET_POL */ | ||
356 | #define WM8400_MIC1DET_POL_MASK 0x0200 /* MIC1DET_POL */ | ||
357 | #define WM8400_MIC1DET_POL_SHIFT 9 /* MIC1DET_POL */ | ||
358 | #define WM8400_MIC1DET_POL_WIDTH 1 /* MIC1DET_POL */ | ||
359 | #define WM8400_FLL_LCK_POL 0x0100 /* FLL_LCK_POL */ | ||
360 | #define WM8400_FLL_LCK_POL_MASK 0x0100 /* FLL_LCK_POL */ | ||
361 | #define WM8400_FLL_LCK_POL_SHIFT 8 /* FLL_LCK_POL */ | ||
362 | #define WM8400_FLL_LCK_POL_WIDTH 1 /* FLL_LCK_POL */ | ||
363 | #define WM8400_GPIO_POL_MASK 0x00FF /* GPIO_POL - [7:0] */ | ||
364 | #define WM8400_GPIO_POL_SHIFT 0 /* GPIO_POL - [7:0] */ | ||
365 | #define WM8400_GPIO_POL_WIDTH 8 /* GPIO_POL - [7:0] */ | ||
366 | |||
367 | /* | ||
368 | * R65 (0x41) - LDO 1 Control | ||
369 | */ | ||
370 | #define WM8400_LDO1_ENA 0x8000 /* LDO1_ENA */ | ||
371 | #define WM8400_LDO1_ENA_MASK 0x8000 /* LDO1_ENA */ | ||
372 | #define WM8400_LDO1_ENA_SHIFT 15 /* LDO1_ENA */ | ||
373 | #define WM8400_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ | ||
374 | #define WM8400_LDO1_SWI 0x4000 /* LDO1_SWI */ | ||
375 | #define WM8400_LDO1_SWI_MASK 0x4000 /* LDO1_SWI */ | ||
376 | #define WM8400_LDO1_SWI_SHIFT 14 /* LDO1_SWI */ | ||
377 | #define WM8400_LDO1_SWI_WIDTH 1 /* LDO1_SWI */ | ||
378 | #define WM8400_LDO1_OPFLT 0x1000 /* LDO1_OPFLT */ | ||
379 | #define WM8400_LDO1_OPFLT_MASK 0x1000 /* LDO1_OPFLT */ | ||
380 | #define WM8400_LDO1_OPFLT_SHIFT 12 /* LDO1_OPFLT */ | ||
381 | #define WM8400_LDO1_OPFLT_WIDTH 1 /* LDO1_OPFLT */ | ||
382 | #define WM8400_LDO1_ERRACT 0x0800 /* LDO1_ERRACT */ | ||
383 | #define WM8400_LDO1_ERRACT_MASK 0x0800 /* LDO1_ERRACT */ | ||
384 | #define WM8400_LDO1_ERRACT_SHIFT 11 /* LDO1_ERRACT */ | ||
385 | #define WM8400_LDO1_ERRACT_WIDTH 1 /* LDO1_ERRACT */ | ||
386 | #define WM8400_LDO1_HIB_MODE 0x0400 /* LDO1_HIB_MODE */ | ||
387 | #define WM8400_LDO1_HIB_MODE_MASK 0x0400 /* LDO1_HIB_MODE */ | ||
388 | #define WM8400_LDO1_HIB_MODE_SHIFT 10 /* LDO1_HIB_MODE */ | ||
389 | #define WM8400_LDO1_HIB_MODE_WIDTH 1 /* LDO1_HIB_MODE */ | ||
390 | #define WM8400_LDO1_VIMG_MASK 0x03E0 /* LDO1_VIMG - [9:5] */ | ||
391 | #define WM8400_LDO1_VIMG_SHIFT 5 /* LDO1_VIMG - [9:5] */ | ||
392 | #define WM8400_LDO1_VIMG_WIDTH 5 /* LDO1_VIMG - [9:5] */ | ||
393 | #define WM8400_LDO1_VSEL_MASK 0x001F /* LDO1_VSEL - [4:0] */ | ||
394 | #define WM8400_LDO1_VSEL_SHIFT 0 /* LDO1_VSEL - [4:0] */ | ||
395 | #define WM8400_LDO1_VSEL_WIDTH 5 /* LDO1_VSEL - [4:0] */ | ||
396 | |||
397 | /* | ||
398 | * R66 (0x42) - LDO 2 Control | ||
399 | */ | ||
400 | #define WM8400_LDO2_ENA 0x8000 /* LDO2_ENA */ | ||
401 | #define WM8400_LDO2_ENA_MASK 0x8000 /* LDO2_ENA */ | ||
402 | #define WM8400_LDO2_ENA_SHIFT 15 /* LDO2_ENA */ | ||
403 | #define WM8400_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ | ||
404 | #define WM8400_LDO2_SWI 0x4000 /* LDO2_SWI */ | ||
405 | #define WM8400_LDO2_SWI_MASK 0x4000 /* LDO2_SWI */ | ||
406 | #define WM8400_LDO2_SWI_SHIFT 14 /* LDO2_SWI */ | ||
407 | #define WM8400_LDO2_SWI_WIDTH 1 /* LDO2_SWI */ | ||
408 | #define WM8400_LDO2_OPFLT 0x1000 /* LDO2_OPFLT */ | ||
409 | #define WM8400_LDO2_OPFLT_MASK 0x1000 /* LDO2_OPFLT */ | ||
410 | #define WM8400_LDO2_OPFLT_SHIFT 12 /* LDO2_OPFLT */ | ||
411 | #define WM8400_LDO2_OPFLT_WIDTH 1 /* LDO2_OPFLT */ | ||
412 | #define WM8400_LDO2_ERRACT 0x0800 /* LDO2_ERRACT */ | ||
413 | #define WM8400_LDO2_ERRACT_MASK 0x0800 /* LDO2_ERRACT */ | ||
414 | #define WM8400_LDO2_ERRACT_SHIFT 11 /* LDO2_ERRACT */ | ||
415 | #define WM8400_LDO2_ERRACT_WIDTH 1 /* LDO2_ERRACT */ | ||
416 | #define WM8400_LDO2_HIB_MODE 0x0400 /* LDO2_HIB_MODE */ | ||
417 | #define WM8400_LDO2_HIB_MODE_MASK 0x0400 /* LDO2_HIB_MODE */ | ||
418 | #define WM8400_LDO2_HIB_MODE_SHIFT 10 /* LDO2_HIB_MODE */ | ||
419 | #define WM8400_LDO2_HIB_MODE_WIDTH 1 /* LDO2_HIB_MODE */ | ||
420 | #define WM8400_LDO2_VIMG_MASK 0x03E0 /* LDO2_VIMG - [9:5] */ | ||
421 | #define WM8400_LDO2_VIMG_SHIFT 5 /* LDO2_VIMG - [9:5] */ | ||
422 | #define WM8400_LDO2_VIMG_WIDTH 5 /* LDO2_VIMG - [9:5] */ | ||
423 | #define WM8400_LDO2_VSEL_MASK 0x001F /* LDO2_VSEL - [4:0] */ | ||
424 | #define WM8400_LDO2_VSEL_SHIFT 0 /* LDO2_VSEL - [4:0] */ | ||
425 | #define WM8400_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [4:0] */ | ||
426 | |||
427 | /* | ||
428 | * R67 (0x43) - LDO 3 Control | ||
429 | */ | ||
430 | #define WM8400_LDO3_ENA 0x8000 /* LDO3_ENA */ | ||
431 | #define WM8400_LDO3_ENA_MASK 0x8000 /* LDO3_ENA */ | ||
432 | #define WM8400_LDO3_ENA_SHIFT 15 /* LDO3_ENA */ | ||
433 | #define WM8400_LDO3_ENA_WIDTH 1 /* LDO3_ENA */ | ||
434 | #define WM8400_LDO3_SWI 0x4000 /* LDO3_SWI */ | ||
435 | #define WM8400_LDO3_SWI_MASK 0x4000 /* LDO3_SWI */ | ||
436 | #define WM8400_LDO3_SWI_SHIFT 14 /* LDO3_SWI */ | ||
437 | #define WM8400_LDO3_SWI_WIDTH 1 /* LDO3_SWI */ | ||
438 | #define WM8400_LDO3_OPFLT 0x1000 /* LDO3_OPFLT */ | ||
439 | #define WM8400_LDO3_OPFLT_MASK 0x1000 /* LDO3_OPFLT */ | ||
440 | #define WM8400_LDO3_OPFLT_SHIFT 12 /* LDO3_OPFLT */ | ||
441 | #define WM8400_LDO3_OPFLT_WIDTH 1 /* LDO3_OPFLT */ | ||
442 | #define WM8400_LDO3_ERRACT 0x0800 /* LDO3_ERRACT */ | ||
443 | #define WM8400_LDO3_ERRACT_MASK 0x0800 /* LDO3_ERRACT */ | ||
444 | #define WM8400_LDO3_ERRACT_SHIFT 11 /* LDO3_ERRACT */ | ||
445 | #define WM8400_LDO3_ERRACT_WIDTH 1 /* LDO3_ERRACT */ | ||
446 | #define WM8400_LDO3_HIB_MODE 0x0400 /* LDO3_HIB_MODE */ | ||
447 | #define WM8400_LDO3_HIB_MODE_MASK 0x0400 /* LDO3_HIB_MODE */ | ||
448 | #define WM8400_LDO3_HIB_MODE_SHIFT 10 /* LDO3_HIB_MODE */ | ||
449 | #define WM8400_LDO3_HIB_MODE_WIDTH 1 /* LDO3_HIB_MODE */ | ||
450 | #define WM8400_LDO3_VIMG_MASK 0x03E0 /* LDO3_VIMG - [9:5] */ | ||
451 | #define WM8400_LDO3_VIMG_SHIFT 5 /* LDO3_VIMG - [9:5] */ | ||
452 | #define WM8400_LDO3_VIMG_WIDTH 5 /* LDO3_VIMG - [9:5] */ | ||
453 | #define WM8400_LDO3_VSEL_MASK 0x001F /* LDO3_VSEL - [4:0] */ | ||
454 | #define WM8400_LDO3_VSEL_SHIFT 0 /* LDO3_VSEL - [4:0] */ | ||
455 | #define WM8400_LDO3_VSEL_WIDTH 5 /* LDO3_VSEL - [4:0] */ | ||
456 | |||
457 | /* | ||
458 | * R68 (0x44) - LDO 4 Control | ||
459 | */ | ||
460 | #define WM8400_LDO4_ENA 0x8000 /* LDO4_ENA */ | ||
461 | #define WM8400_LDO4_ENA_MASK 0x8000 /* LDO4_ENA */ | ||
462 | #define WM8400_LDO4_ENA_SHIFT 15 /* LDO4_ENA */ | ||
463 | #define WM8400_LDO4_ENA_WIDTH 1 /* LDO4_ENA */ | ||
464 | #define WM8400_LDO4_SWI 0x4000 /* LDO4_SWI */ | ||
465 | #define WM8400_LDO4_SWI_MASK 0x4000 /* LDO4_SWI */ | ||
466 | #define WM8400_LDO4_SWI_SHIFT 14 /* LDO4_SWI */ | ||
467 | #define WM8400_LDO4_SWI_WIDTH 1 /* LDO4_SWI */ | ||
468 | #define WM8400_LDO4_OPFLT 0x1000 /* LDO4_OPFLT */ | ||
469 | #define WM8400_LDO4_OPFLT_MASK 0x1000 /* LDO4_OPFLT */ | ||
470 | #define WM8400_LDO4_OPFLT_SHIFT 12 /* LDO4_OPFLT */ | ||
471 | #define WM8400_LDO4_OPFLT_WIDTH 1 /* LDO4_OPFLT */ | ||
472 | #define WM8400_LDO4_ERRACT 0x0800 /* LDO4_ERRACT */ | ||
473 | #define WM8400_LDO4_ERRACT_MASK 0x0800 /* LDO4_ERRACT */ | ||
474 | #define WM8400_LDO4_ERRACT_SHIFT 11 /* LDO4_ERRACT */ | ||
475 | #define WM8400_LDO4_ERRACT_WIDTH 1 /* LDO4_ERRACT */ | ||
476 | #define WM8400_LDO4_HIB_MODE 0x0400 /* LDO4_HIB_MODE */ | ||
477 | #define WM8400_LDO4_HIB_MODE_MASK 0x0400 /* LDO4_HIB_MODE */ | ||
478 | #define WM8400_LDO4_HIB_MODE_SHIFT 10 /* LDO4_HIB_MODE */ | ||
479 | #define WM8400_LDO4_HIB_MODE_WIDTH 1 /* LDO4_HIB_MODE */ | ||
480 | #define WM8400_LDO4_VIMG_MASK 0x03E0 /* LDO4_VIMG - [9:5] */ | ||
481 | #define WM8400_LDO4_VIMG_SHIFT 5 /* LDO4_VIMG - [9:5] */ | ||
482 | #define WM8400_LDO4_VIMG_WIDTH 5 /* LDO4_VIMG - [9:5] */ | ||
483 | #define WM8400_LDO4_VSEL_MASK 0x001F /* LDO4_VSEL - [4:0] */ | ||
484 | #define WM8400_LDO4_VSEL_SHIFT 0 /* LDO4_VSEL - [4:0] */ | ||
485 | #define WM8400_LDO4_VSEL_WIDTH 5 /* LDO4_VSEL - [4:0] */ | ||
486 | |||
487 | /* | ||
488 | * R70 (0x46) - DCDC1 Control 1 | ||
489 | */ | ||
490 | #define WM8400_DC1_ENA 0x8000 /* DC1_ENA */ | ||
491 | #define WM8400_DC1_ENA_MASK 0x8000 /* DC1_ENA */ | ||
492 | #define WM8400_DC1_ENA_SHIFT 15 /* DC1_ENA */ | ||
493 | #define WM8400_DC1_ENA_WIDTH 1 /* DC1_ENA */ | ||
494 | #define WM8400_DC1_ACTIVE 0x4000 /* DC1_ACTIVE */ | ||
495 | #define WM8400_DC1_ACTIVE_MASK 0x4000 /* DC1_ACTIVE */ | ||
496 | #define WM8400_DC1_ACTIVE_SHIFT 14 /* DC1_ACTIVE */ | ||
497 | #define WM8400_DC1_ACTIVE_WIDTH 1 /* DC1_ACTIVE */ | ||
498 | #define WM8400_DC1_SLEEP 0x2000 /* DC1_SLEEP */ | ||
499 | #define WM8400_DC1_SLEEP_MASK 0x2000 /* DC1_SLEEP */ | ||
500 | #define WM8400_DC1_SLEEP_SHIFT 13 /* DC1_SLEEP */ | ||
501 | #define WM8400_DC1_SLEEP_WIDTH 1 /* DC1_SLEEP */ | ||
502 | #define WM8400_DC1_OPFLT 0x1000 /* DC1_OPFLT */ | ||
503 | #define WM8400_DC1_OPFLT_MASK 0x1000 /* DC1_OPFLT */ | ||
504 | #define WM8400_DC1_OPFLT_SHIFT 12 /* DC1_OPFLT */ | ||
505 | #define WM8400_DC1_OPFLT_WIDTH 1 /* DC1_OPFLT */ | ||
506 | #define WM8400_DC1_ERRACT 0x0800 /* DC1_ERRACT */ | ||
507 | #define WM8400_DC1_ERRACT_MASK 0x0800 /* DC1_ERRACT */ | ||
508 | #define WM8400_DC1_ERRACT_SHIFT 11 /* DC1_ERRACT */ | ||
509 | #define WM8400_DC1_ERRACT_WIDTH 1 /* DC1_ERRACT */ | ||
510 | #define WM8400_DC1_HIB_MODE 0x0400 /* DC1_HIB_MODE */ | ||
511 | #define WM8400_DC1_HIB_MODE_MASK 0x0400 /* DC1_HIB_MODE */ | ||
512 | #define WM8400_DC1_HIB_MODE_SHIFT 10 /* DC1_HIB_MODE */ | ||
513 | #define WM8400_DC1_HIB_MODE_WIDTH 1 /* DC1_HIB_MODE */ | ||
514 | #define WM8400_DC1_SOFTST_MASK 0x0300 /* DC1_SOFTST - [9:8] */ | ||
515 | #define WM8400_DC1_SOFTST_SHIFT 8 /* DC1_SOFTST - [9:8] */ | ||
516 | #define WM8400_DC1_SOFTST_WIDTH 2 /* DC1_SOFTST - [9:8] */ | ||
517 | #define WM8400_DC1_OV_PROT 0x0080 /* DC1_OV_PROT */ | ||
518 | #define WM8400_DC1_OV_PROT_MASK 0x0080 /* DC1_OV_PROT */ | ||
519 | #define WM8400_DC1_OV_PROT_SHIFT 7 /* DC1_OV_PROT */ | ||
520 | #define WM8400_DC1_OV_PROT_WIDTH 1 /* DC1_OV_PROT */ | ||
521 | #define WM8400_DC1_VSEL_MASK 0x007F /* DC1_VSEL - [6:0] */ | ||
522 | #define WM8400_DC1_VSEL_SHIFT 0 /* DC1_VSEL - [6:0] */ | ||
523 | #define WM8400_DC1_VSEL_WIDTH 7 /* DC1_VSEL - [6:0] */ | ||
524 | |||
525 | /* | ||
526 | * R71 (0x47) - DCDC1 Control 2 | ||
527 | */ | ||
528 | #define WM8400_DC1_FRC_PWM 0x2000 /* DC1_FRC_PWM */ | ||
529 | #define WM8400_DC1_FRC_PWM_MASK 0x2000 /* DC1_FRC_PWM */ | ||
530 | #define WM8400_DC1_FRC_PWM_SHIFT 13 /* DC1_FRC_PWM */ | ||
531 | #define WM8400_DC1_FRC_PWM_WIDTH 1 /* DC1_FRC_PWM */ | ||
532 | #define WM8400_DC1_STBY_LIM_MASK 0x0300 /* DC1_STBY_LIM - [9:8] */ | ||
533 | #define WM8400_DC1_STBY_LIM_SHIFT 8 /* DC1_STBY_LIM - [9:8] */ | ||
534 | #define WM8400_DC1_STBY_LIM_WIDTH 2 /* DC1_STBY_LIM - [9:8] */ | ||
535 | #define WM8400_DC1_ACT_LIM 0x0080 /* DC1_ACT_LIM */ | ||
536 | #define WM8400_DC1_ACT_LIM_MASK 0x0080 /* DC1_ACT_LIM */ | ||
537 | #define WM8400_DC1_ACT_LIM_SHIFT 7 /* DC1_ACT_LIM */ | ||
538 | #define WM8400_DC1_ACT_LIM_WIDTH 1 /* DC1_ACT_LIM */ | ||
539 | #define WM8400_DC1_VIMG_MASK 0x007F /* DC1_VIMG - [6:0] */ | ||
540 | #define WM8400_DC1_VIMG_SHIFT 0 /* DC1_VIMG - [6:0] */ | ||
541 | #define WM8400_DC1_VIMG_WIDTH 7 /* DC1_VIMG - [6:0] */ | ||
542 | |||
543 | /* | ||
544 | * R72 (0x48) - DCDC2 Control 1 | ||
545 | */ | ||
546 | #define WM8400_DC2_ENA 0x8000 /* DC2_ENA */ | ||
547 | #define WM8400_DC2_ENA_MASK 0x8000 /* DC2_ENA */ | ||
548 | #define WM8400_DC2_ENA_SHIFT 15 /* DC2_ENA */ | ||
549 | #define WM8400_DC2_ENA_WIDTH 1 /* DC2_ENA */ | ||
550 | #define WM8400_DC2_ACTIVE 0x4000 /* DC2_ACTIVE */ | ||
551 | #define WM8400_DC2_ACTIVE_MASK 0x4000 /* DC2_ACTIVE */ | ||
552 | #define WM8400_DC2_ACTIVE_SHIFT 14 /* DC2_ACTIVE */ | ||
553 | #define WM8400_DC2_ACTIVE_WIDTH 1 /* DC2_ACTIVE */ | ||
554 | #define WM8400_DC2_SLEEP 0x2000 /* DC2_SLEEP */ | ||
555 | #define WM8400_DC2_SLEEP_MASK 0x2000 /* DC2_SLEEP */ | ||
556 | #define WM8400_DC2_SLEEP_SHIFT 13 /* DC2_SLEEP */ | ||
557 | #define WM8400_DC2_SLEEP_WIDTH 1 /* DC2_SLEEP */ | ||
558 | #define WM8400_DC2_OPFLT 0x1000 /* DC2_OPFLT */ | ||
559 | #define WM8400_DC2_OPFLT_MASK 0x1000 /* DC2_OPFLT */ | ||
560 | #define WM8400_DC2_OPFLT_SHIFT 12 /* DC2_OPFLT */ | ||
561 | #define WM8400_DC2_OPFLT_WIDTH 1 /* DC2_OPFLT */ | ||
562 | #define WM8400_DC2_ERRACT 0x0800 /* DC2_ERRACT */ | ||
563 | #define WM8400_DC2_ERRACT_MASK 0x0800 /* DC2_ERRACT */ | ||
564 | #define WM8400_DC2_ERRACT_SHIFT 11 /* DC2_ERRACT */ | ||
565 | #define WM8400_DC2_ERRACT_WIDTH 1 /* DC2_ERRACT */ | ||
566 | #define WM8400_DC2_HIB_MODE 0x0400 /* DC2_HIB_MODE */ | ||
567 | #define WM8400_DC2_HIB_MODE_MASK 0x0400 /* DC2_HIB_MODE */ | ||
568 | #define WM8400_DC2_HIB_MODE_SHIFT 10 /* DC2_HIB_MODE */ | ||
569 | #define WM8400_DC2_HIB_MODE_WIDTH 1 /* DC2_HIB_MODE */ | ||
570 | #define WM8400_DC2_SOFTST_MASK 0x0300 /* DC2_SOFTST - [9:8] */ | ||
571 | #define WM8400_DC2_SOFTST_SHIFT 8 /* DC2_SOFTST - [9:8] */ | ||
572 | #define WM8400_DC2_SOFTST_WIDTH 2 /* DC2_SOFTST - [9:8] */ | ||
573 | #define WM8400_DC2_OV_PROT 0x0080 /* DC2_OV_PROT */ | ||
574 | #define WM8400_DC2_OV_PROT_MASK 0x0080 /* DC2_OV_PROT */ | ||
575 | #define WM8400_DC2_OV_PROT_SHIFT 7 /* DC2_OV_PROT */ | ||
576 | #define WM8400_DC2_OV_PROT_WIDTH 1 /* DC2_OV_PROT */ | ||
577 | #define WM8400_DC2_VSEL_MASK 0x007F /* DC2_VSEL - [6:0] */ | ||
578 | #define WM8400_DC2_VSEL_SHIFT 0 /* DC2_VSEL - [6:0] */ | ||
579 | #define WM8400_DC2_VSEL_WIDTH 7 /* DC2_VSEL - [6:0] */ | ||
580 | |||
581 | /* | ||
582 | * R73 (0x49) - DCDC2 Control 2 | ||
583 | */ | ||
584 | #define WM8400_DC2_FRC_PWM 0x2000 /* DC2_FRC_PWM */ | ||
585 | #define WM8400_DC2_FRC_PWM_MASK 0x2000 /* DC2_FRC_PWM */ | ||
586 | #define WM8400_DC2_FRC_PWM_SHIFT 13 /* DC2_FRC_PWM */ | ||
587 | #define WM8400_DC2_FRC_PWM_WIDTH 1 /* DC2_FRC_PWM */ | ||
588 | #define WM8400_DC2_STBY_LIM_MASK 0x0300 /* DC2_STBY_LIM - [9:8] */ | ||
589 | #define WM8400_DC2_STBY_LIM_SHIFT 8 /* DC2_STBY_LIM - [9:8] */ | ||
590 | #define WM8400_DC2_STBY_LIM_WIDTH 2 /* DC2_STBY_LIM - [9:8] */ | ||
591 | #define WM8400_DC2_ACT_LIM 0x0080 /* DC2_ACT_LIM */ | ||
592 | #define WM8400_DC2_ACT_LIM_MASK 0x0080 /* DC2_ACT_LIM */ | ||
593 | #define WM8400_DC2_ACT_LIM_SHIFT 7 /* DC2_ACT_LIM */ | ||
594 | #define WM8400_DC2_ACT_LIM_WIDTH 1 /* DC2_ACT_LIM */ | ||
595 | #define WM8400_DC2_VIMG_MASK 0x007F /* DC2_VIMG - [6:0] */ | ||
596 | #define WM8400_DC2_VIMG_SHIFT 0 /* DC2_VIMG - [6:0] */ | ||
597 | #define WM8400_DC2_VIMG_WIDTH 7 /* DC2_VIMG - [6:0] */ | ||
598 | |||
599 | /* | ||
600 | * R75 (0x4B) - Interface | ||
601 | */ | ||
602 | #define WM8400_AUTOINC 0x0008 /* AUTOINC */ | ||
603 | #define WM8400_AUTOINC_MASK 0x0008 /* AUTOINC */ | ||
604 | #define WM8400_AUTOINC_SHIFT 3 /* AUTOINC */ | ||
605 | #define WM8400_AUTOINC_WIDTH 1 /* AUTOINC */ | ||
606 | #define WM8400_ARA_ENA 0x0004 /* ARA_ENA */ | ||
607 | #define WM8400_ARA_ENA_MASK 0x0004 /* ARA_ENA */ | ||
608 | #define WM8400_ARA_ENA_SHIFT 2 /* ARA_ENA */ | ||
609 | #define WM8400_ARA_ENA_WIDTH 1 /* ARA_ENA */ | ||
610 | #define WM8400_SPI_CFG 0x0002 /* SPI_CFG */ | ||
611 | #define WM8400_SPI_CFG_MASK 0x0002 /* SPI_CFG */ | ||
612 | #define WM8400_SPI_CFG_SHIFT 1 /* SPI_CFG */ | ||
613 | #define WM8400_SPI_CFG_WIDTH 1 /* SPI_CFG */ | ||
614 | |||
615 | /* | ||
616 | * R76 (0x4C) - PM GENERAL | ||
617 | */ | ||
618 | #define WM8400_CODEC_SOFTST 0x8000 /* CODEC_SOFTST */ | ||
619 | #define WM8400_CODEC_SOFTST_MASK 0x8000 /* CODEC_SOFTST */ | ||
620 | #define WM8400_CODEC_SOFTST_SHIFT 15 /* CODEC_SOFTST */ | ||
621 | #define WM8400_CODEC_SOFTST_WIDTH 1 /* CODEC_SOFTST */ | ||
622 | #define WM8400_CODEC_SOFTSD 0x4000 /* CODEC_SOFTSD */ | ||
623 | #define WM8400_CODEC_SOFTSD_MASK 0x4000 /* CODEC_SOFTSD */ | ||
624 | #define WM8400_CODEC_SOFTSD_SHIFT 14 /* CODEC_SOFTSD */ | ||
625 | #define WM8400_CODEC_SOFTSD_WIDTH 1 /* CODEC_SOFTSD */ | ||
626 | #define WM8400_CHIP_SOFTSD 0x2000 /* CHIP_SOFTSD */ | ||
627 | #define WM8400_CHIP_SOFTSD_MASK 0x2000 /* CHIP_SOFTSD */ | ||
628 | #define WM8400_CHIP_SOFTSD_SHIFT 13 /* CHIP_SOFTSD */ | ||
629 | #define WM8400_CHIP_SOFTSD_WIDTH 1 /* CHIP_SOFTSD */ | ||
630 | #define WM8400_DSLEEP1_POL 0x0008 /* DSLEEP1_POL */ | ||
631 | #define WM8400_DSLEEP1_POL_MASK 0x0008 /* DSLEEP1_POL */ | ||
632 | #define WM8400_DSLEEP1_POL_SHIFT 3 /* DSLEEP1_POL */ | ||
633 | #define WM8400_DSLEEP1_POL_WIDTH 1 /* DSLEEP1_POL */ | ||
634 | #define WM8400_DSLEEP2_POL 0x0004 /* DSLEEP2_POL */ | ||
635 | #define WM8400_DSLEEP2_POL_MASK 0x0004 /* DSLEEP2_POL */ | ||
636 | #define WM8400_DSLEEP2_POL_SHIFT 2 /* DSLEEP2_POL */ | ||
637 | #define WM8400_DSLEEP2_POL_WIDTH 1 /* DSLEEP2_POL */ | ||
638 | #define WM8400_PWR_STATE_MASK 0x0003 /* PWR_STATE - [1:0] */ | ||
639 | #define WM8400_PWR_STATE_SHIFT 0 /* PWR_STATE - [1:0] */ | ||
640 | #define WM8400_PWR_STATE_WIDTH 2 /* PWR_STATE - [1:0] */ | ||
641 | |||
642 | /* | ||
643 | * R78 (0x4E) - PM Shutdown Control | ||
644 | */ | ||
645 | #define WM8400_CHIP_GT150_ERRACT 0x0200 /* CHIP_GT150_ERRACT */ | ||
646 | #define WM8400_CHIP_GT150_ERRACT_MASK 0x0200 /* CHIP_GT150_ERRACT */ | ||
647 | #define WM8400_CHIP_GT150_ERRACT_SHIFT 9 /* CHIP_GT150_ERRACT */ | ||
648 | #define WM8400_CHIP_GT150_ERRACT_WIDTH 1 /* CHIP_GT150_ERRACT */ | ||
649 | #define WM8400_CHIP_GT115_ERRACT 0x0100 /* CHIP_GT115_ERRACT */ | ||
650 | #define WM8400_CHIP_GT115_ERRACT_MASK 0x0100 /* CHIP_GT115_ERRACT */ | ||
651 | #define WM8400_CHIP_GT115_ERRACT_SHIFT 8 /* CHIP_GT115_ERRACT */ | ||
652 | #define WM8400_CHIP_GT115_ERRACT_WIDTH 1 /* CHIP_GT115_ERRACT */ | ||
653 | #define WM8400_LINE_CMP_ERRACT 0x0080 /* LINE_CMP_ERRACT */ | ||
654 | #define WM8400_LINE_CMP_ERRACT_MASK 0x0080 /* LINE_CMP_ERRACT */ | ||
655 | #define WM8400_LINE_CMP_ERRACT_SHIFT 7 /* LINE_CMP_ERRACT */ | ||
656 | #define WM8400_LINE_CMP_ERRACT_WIDTH 1 /* LINE_CMP_ERRACT */ | ||
657 | #define WM8400_UVLO_ERRACT 0x0040 /* UVLO_ERRACT */ | ||
658 | #define WM8400_UVLO_ERRACT_MASK 0x0040 /* UVLO_ERRACT */ | ||
659 | #define WM8400_UVLO_ERRACT_SHIFT 6 /* UVLO_ERRACT */ | ||
660 | #define WM8400_UVLO_ERRACT_WIDTH 1 /* UVLO_ERRACT */ | ||
661 | |||
662 | /* | ||
663 | * R79 (0x4F) - Interrupt Status 1 | ||
664 | */ | ||
665 | #define WM8400_MICD_CINT 0x8000 /* MICD_CINT */ | ||
666 | #define WM8400_MICD_CINT_MASK 0x8000 /* MICD_CINT */ | ||
667 | #define WM8400_MICD_CINT_SHIFT 15 /* MICD_CINT */ | ||
668 | #define WM8400_MICD_CINT_WIDTH 1 /* MICD_CINT */ | ||
669 | #define WM8400_MICSCD_CINT 0x4000 /* MICSCD_CINT */ | ||
670 | #define WM8400_MICSCD_CINT_MASK 0x4000 /* MICSCD_CINT */ | ||
671 | #define WM8400_MICSCD_CINT_SHIFT 14 /* MICSCD_CINT */ | ||
672 | #define WM8400_MICSCD_CINT_WIDTH 1 /* MICSCD_CINT */ | ||
673 | #define WM8400_JDL_CINT 0x2000 /* JDL_CINT */ | ||
674 | #define WM8400_JDL_CINT_MASK 0x2000 /* JDL_CINT */ | ||
675 | #define WM8400_JDL_CINT_SHIFT 13 /* JDL_CINT */ | ||
676 | #define WM8400_JDL_CINT_WIDTH 1 /* JDL_CINT */ | ||
677 | #define WM8400_JDR_CINT 0x1000 /* JDR_CINT */ | ||
678 | #define WM8400_JDR_CINT_MASK 0x1000 /* JDR_CINT */ | ||
679 | #define WM8400_JDR_CINT_SHIFT 12 /* JDR_CINT */ | ||
680 | #define WM8400_JDR_CINT_WIDTH 1 /* JDR_CINT */ | ||
681 | #define WM8400_CODEC_SEQ_END_EINT 0x0800 /* CODEC_SEQ_END_EINT */ | ||
682 | #define WM8400_CODEC_SEQ_END_EINT_MASK 0x0800 /* CODEC_SEQ_END_EINT */ | ||
683 | #define WM8400_CODEC_SEQ_END_EINT_SHIFT 11 /* CODEC_SEQ_END_EINT */ | ||
684 | #define WM8400_CODEC_SEQ_END_EINT_WIDTH 1 /* CODEC_SEQ_END_EINT */ | ||
685 | #define WM8400_CDEL_TO_EINT 0x0400 /* CDEL_TO_EINT */ | ||
686 | #define WM8400_CDEL_TO_EINT_MASK 0x0400 /* CDEL_TO_EINT */ | ||
687 | #define WM8400_CDEL_TO_EINT_SHIFT 10 /* CDEL_TO_EINT */ | ||
688 | #define WM8400_CDEL_TO_EINT_WIDTH 1 /* CDEL_TO_EINT */ | ||
689 | #define WM8400_CHIP_GT150_EINT 0x0200 /* CHIP_GT150_EINT */ | ||
690 | #define WM8400_CHIP_GT150_EINT_MASK 0x0200 /* CHIP_GT150_EINT */ | ||
691 | #define WM8400_CHIP_GT150_EINT_SHIFT 9 /* CHIP_GT150_EINT */ | ||
692 | #define WM8400_CHIP_GT150_EINT_WIDTH 1 /* CHIP_GT150_EINT */ | ||
693 | #define WM8400_CHIP_GT115_EINT 0x0100 /* CHIP_GT115_EINT */ | ||
694 | #define WM8400_CHIP_GT115_EINT_MASK 0x0100 /* CHIP_GT115_EINT */ | ||
695 | #define WM8400_CHIP_GT115_EINT_SHIFT 8 /* CHIP_GT115_EINT */ | ||
696 | #define WM8400_CHIP_GT115_EINT_WIDTH 1 /* CHIP_GT115_EINT */ | ||
697 | #define WM8400_LINE_CMP_EINT 0x0080 /* LINE_CMP_EINT */ | ||
698 | #define WM8400_LINE_CMP_EINT_MASK 0x0080 /* LINE_CMP_EINT */ | ||
699 | #define WM8400_LINE_CMP_EINT_SHIFT 7 /* LINE_CMP_EINT */ | ||
700 | #define WM8400_LINE_CMP_EINT_WIDTH 1 /* LINE_CMP_EINT */ | ||
701 | #define WM8400_UVLO_EINT 0x0040 /* UVLO_EINT */ | ||
702 | #define WM8400_UVLO_EINT_MASK 0x0040 /* UVLO_EINT */ | ||
703 | #define WM8400_UVLO_EINT_SHIFT 6 /* UVLO_EINT */ | ||
704 | #define WM8400_UVLO_EINT_WIDTH 1 /* UVLO_EINT */ | ||
705 | #define WM8400_DC2_UV_EINT 0x0020 /* DC2_UV_EINT */ | ||
706 | #define WM8400_DC2_UV_EINT_MASK 0x0020 /* DC2_UV_EINT */ | ||
707 | #define WM8400_DC2_UV_EINT_SHIFT 5 /* DC2_UV_EINT */ | ||
708 | #define WM8400_DC2_UV_EINT_WIDTH 1 /* DC2_UV_EINT */ | ||
709 | #define WM8400_DC1_UV_EINT 0x0010 /* DC1_UV_EINT */ | ||
710 | #define WM8400_DC1_UV_EINT_MASK 0x0010 /* DC1_UV_EINT */ | ||
711 | #define WM8400_DC1_UV_EINT_SHIFT 4 /* DC1_UV_EINT */ | ||
712 | #define WM8400_DC1_UV_EINT_WIDTH 1 /* DC1_UV_EINT */ | ||
713 | #define WM8400_LDO4_UV_EINT 0x0008 /* LDO4_UV_EINT */ | ||
714 | #define WM8400_LDO4_UV_EINT_MASK 0x0008 /* LDO4_UV_EINT */ | ||
715 | #define WM8400_LDO4_UV_EINT_SHIFT 3 /* LDO4_UV_EINT */ | ||
716 | #define WM8400_LDO4_UV_EINT_WIDTH 1 /* LDO4_UV_EINT */ | ||
717 | #define WM8400_LDO3_UV_EINT 0x0004 /* LDO3_UV_EINT */ | ||
718 | #define WM8400_LDO3_UV_EINT_MASK 0x0004 /* LDO3_UV_EINT */ | ||
719 | #define WM8400_LDO3_UV_EINT_SHIFT 2 /* LDO3_UV_EINT */ | ||
720 | #define WM8400_LDO3_UV_EINT_WIDTH 1 /* LDO3_UV_EINT */ | ||
721 | #define WM8400_LDO2_UV_EINT 0x0002 /* LDO2_UV_EINT */ | ||
722 | #define WM8400_LDO2_UV_EINT_MASK 0x0002 /* LDO2_UV_EINT */ | ||
723 | #define WM8400_LDO2_UV_EINT_SHIFT 1 /* LDO2_UV_EINT */ | ||
724 | #define WM8400_LDO2_UV_EINT_WIDTH 1 /* LDO2_UV_EINT */ | ||
725 | #define WM8400_LDO1_UV_EINT 0x0001 /* LDO1_UV_EINT */ | ||
726 | #define WM8400_LDO1_UV_EINT_MASK 0x0001 /* LDO1_UV_EINT */ | ||
727 | #define WM8400_LDO1_UV_EINT_SHIFT 0 /* LDO1_UV_EINT */ | ||
728 | #define WM8400_LDO1_UV_EINT_WIDTH 1 /* LDO1_UV_EINT */ | ||
729 | |||
730 | /* | ||
731 | * R80 (0x50) - Interrupt Status 1 Mask | ||
732 | */ | ||
733 | #define WM8400_IM_MICD_CINT 0x8000 /* IM_MICD_CINT */ | ||
734 | #define WM8400_IM_MICD_CINT_MASK 0x8000 /* IM_MICD_CINT */ | ||
735 | #define WM8400_IM_MICD_CINT_SHIFT 15 /* IM_MICD_CINT */ | ||
736 | #define WM8400_IM_MICD_CINT_WIDTH 1 /* IM_MICD_CINT */ | ||
737 | #define WM8400_IM_MICSCD_CINT 0x4000 /* IM_MICSCD_CINT */ | ||
738 | #define WM8400_IM_MICSCD_CINT_MASK 0x4000 /* IM_MICSCD_CINT */ | ||
739 | #define WM8400_IM_MICSCD_CINT_SHIFT 14 /* IM_MICSCD_CINT */ | ||
740 | #define WM8400_IM_MICSCD_CINT_WIDTH 1 /* IM_MICSCD_CINT */ | ||
741 | #define WM8400_IM_JDL_CINT 0x2000 /* IM_JDL_CINT */ | ||
742 | #define WM8400_IM_JDL_CINT_MASK 0x2000 /* IM_JDL_CINT */ | ||
743 | #define WM8400_IM_JDL_CINT_SHIFT 13 /* IM_JDL_CINT */ | ||
744 | #define WM8400_IM_JDL_CINT_WIDTH 1 /* IM_JDL_CINT */ | ||
745 | #define WM8400_IM_JDR_CINT 0x1000 /* IM_JDR_CINT */ | ||
746 | #define WM8400_IM_JDR_CINT_MASK 0x1000 /* IM_JDR_CINT */ | ||
747 | #define WM8400_IM_JDR_CINT_SHIFT 12 /* IM_JDR_CINT */ | ||
748 | #define WM8400_IM_JDR_CINT_WIDTH 1 /* IM_JDR_CINT */ | ||
749 | #define WM8400_IM_CODEC_SEQ_END_EINT 0x0800 /* IM_CODEC_SEQ_END_EINT */ | ||
750 | #define WM8400_IM_CODEC_SEQ_END_EINT_MASK 0x0800 /* IM_CODEC_SEQ_END_EINT */ | ||
751 | #define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT 11 /* IM_CODEC_SEQ_END_EINT */ | ||
752 | #define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH 1 /* IM_CODEC_SEQ_END_EINT */ | ||
753 | #define WM8400_IM_CDEL_TO_EINT 0x0400 /* IM_CDEL_TO_EINT */ | ||
754 | #define WM8400_IM_CDEL_TO_EINT_MASK 0x0400 /* IM_CDEL_TO_EINT */ | ||
755 | #define WM8400_IM_CDEL_TO_EINT_SHIFT 10 /* IM_CDEL_TO_EINT */ | ||
756 | #define WM8400_IM_CDEL_TO_EINT_WIDTH 1 /* IM_CDEL_TO_EINT */ | ||
757 | #define WM8400_IM_CHIP_GT150_EINT 0x0200 /* IM_CHIP_GT150_EINT */ | ||
758 | #define WM8400_IM_CHIP_GT150_EINT_MASK 0x0200 /* IM_CHIP_GT150_EINT */ | ||
759 | #define WM8400_IM_CHIP_GT150_EINT_SHIFT 9 /* IM_CHIP_GT150_EINT */ | ||
760 | #define WM8400_IM_CHIP_GT150_EINT_WIDTH 1 /* IM_CHIP_GT150_EINT */ | ||
761 | #define WM8400_IM_CHIP_GT115_EINT 0x0100 /* IM_CHIP_GT115_EINT */ | ||
762 | #define WM8400_IM_CHIP_GT115_EINT_MASK 0x0100 /* IM_CHIP_GT115_EINT */ | ||
763 | #define WM8400_IM_CHIP_GT115_EINT_SHIFT 8 /* IM_CHIP_GT115_EINT */ | ||
764 | #define WM8400_IM_CHIP_GT115_EINT_WIDTH 1 /* IM_CHIP_GT115_EINT */ | ||
765 | #define WM8400_IM_LINE_CMP_EINT 0x0080 /* IM_LINE_CMP_EINT */ | ||
766 | #define WM8400_IM_LINE_CMP_EINT_MASK 0x0080 /* IM_LINE_CMP_EINT */ | ||
767 | #define WM8400_IM_LINE_CMP_EINT_SHIFT 7 /* IM_LINE_CMP_EINT */ | ||
768 | #define WM8400_IM_LINE_CMP_EINT_WIDTH 1 /* IM_LINE_CMP_EINT */ | ||
769 | #define WM8400_IM_UVLO_EINT 0x0040 /* IM_UVLO_EINT */ | ||
770 | #define WM8400_IM_UVLO_EINT_MASK 0x0040 /* IM_UVLO_EINT */ | ||
771 | #define WM8400_IM_UVLO_EINT_SHIFT 6 /* IM_UVLO_EINT */ | ||
772 | #define WM8400_IM_UVLO_EINT_WIDTH 1 /* IM_UVLO_EINT */ | ||
773 | #define WM8400_IM_DC2_UV_EINT 0x0020 /* IM_DC2_UV_EINT */ | ||
774 | #define WM8400_IM_DC2_UV_EINT_MASK 0x0020 /* IM_DC2_UV_EINT */ | ||
775 | #define WM8400_IM_DC2_UV_EINT_SHIFT 5 /* IM_DC2_UV_EINT */ | ||
776 | #define WM8400_IM_DC2_UV_EINT_WIDTH 1 /* IM_DC2_UV_EINT */ | ||
777 | #define WM8400_IM_DC1_UV_EINT 0x0010 /* IM_DC1_UV_EINT */ | ||
778 | #define WM8400_IM_DC1_UV_EINT_MASK 0x0010 /* IM_DC1_UV_EINT */ | ||
779 | #define WM8400_IM_DC1_UV_EINT_SHIFT 4 /* IM_DC1_UV_EINT */ | ||
780 | #define WM8400_IM_DC1_UV_EINT_WIDTH 1 /* IM_DC1_UV_EINT */ | ||
781 | #define WM8400_IM_LDO4_UV_EINT 0x0008 /* IM_LDO4_UV_EINT */ | ||
782 | #define WM8400_IM_LDO4_UV_EINT_MASK 0x0008 /* IM_LDO4_UV_EINT */ | ||
783 | #define WM8400_IM_LDO4_UV_EINT_SHIFT 3 /* IM_LDO4_UV_EINT */ | ||
784 | #define WM8400_IM_LDO4_UV_EINT_WIDTH 1 /* IM_LDO4_UV_EINT */ | ||
785 | #define WM8400_IM_LDO3_UV_EINT 0x0004 /* IM_LDO3_UV_EINT */ | ||
786 | #define WM8400_IM_LDO3_UV_EINT_MASK 0x0004 /* IM_LDO3_UV_EINT */ | ||
787 | #define WM8400_IM_LDO3_UV_EINT_SHIFT 2 /* IM_LDO3_UV_EINT */ | ||
788 | #define WM8400_IM_LDO3_UV_EINT_WIDTH 1 /* IM_LDO3_UV_EINT */ | ||
789 | #define WM8400_IM_LDO2_UV_EINT 0x0002 /* IM_LDO2_UV_EINT */ | ||
790 | #define WM8400_IM_LDO2_UV_EINT_MASK 0x0002 /* IM_LDO2_UV_EINT */ | ||
791 | #define WM8400_IM_LDO2_UV_EINT_SHIFT 1 /* IM_LDO2_UV_EINT */ | ||
792 | #define WM8400_IM_LDO2_UV_EINT_WIDTH 1 /* IM_LDO2_UV_EINT */ | ||
793 | #define WM8400_IM_LDO1_UV_EINT 0x0001 /* IM_LDO1_UV_EINT */ | ||
794 | #define WM8400_IM_LDO1_UV_EINT_MASK 0x0001 /* IM_LDO1_UV_EINT */ | ||
795 | #define WM8400_IM_LDO1_UV_EINT_SHIFT 0 /* IM_LDO1_UV_EINT */ | ||
796 | #define WM8400_IM_LDO1_UV_EINT_WIDTH 1 /* IM_LDO1_UV_EINT */ | ||
797 | |||
798 | /* | ||
799 | * R81 (0x51) - Interrupt Levels | ||
800 | */ | ||
801 | #define WM8400_MICD_LVL 0x8000 /* MICD_LVL */ | ||
802 | #define WM8400_MICD_LVL_MASK 0x8000 /* MICD_LVL */ | ||
803 | #define WM8400_MICD_LVL_SHIFT 15 /* MICD_LVL */ | ||
804 | #define WM8400_MICD_LVL_WIDTH 1 /* MICD_LVL */ | ||
805 | #define WM8400_MICSCD_LVL 0x4000 /* MICSCD_LVL */ | ||
806 | #define WM8400_MICSCD_LVL_MASK 0x4000 /* MICSCD_LVL */ | ||
807 | #define WM8400_MICSCD_LVL_SHIFT 14 /* MICSCD_LVL */ | ||
808 | #define WM8400_MICSCD_LVL_WIDTH 1 /* MICSCD_LVL */ | ||
809 | #define WM8400_JDL_LVL 0x2000 /* JDL_LVL */ | ||
810 | #define WM8400_JDL_LVL_MASK 0x2000 /* JDL_LVL */ | ||
811 | #define WM8400_JDL_LVL_SHIFT 13 /* JDL_LVL */ | ||
812 | #define WM8400_JDL_LVL_WIDTH 1 /* JDL_LVL */ | ||
813 | #define WM8400_JDR_LVL 0x1000 /* JDR_LVL */ | ||
814 | #define WM8400_JDR_LVL_MASK 0x1000 /* JDR_LVL */ | ||
815 | #define WM8400_JDR_LVL_SHIFT 12 /* JDR_LVL */ | ||
816 | #define WM8400_JDR_LVL_WIDTH 1 /* JDR_LVL */ | ||
817 | #define WM8400_CODEC_SEQ_END_LVL 0x0800 /* CODEC_SEQ_END_LVL */ | ||
818 | #define WM8400_CODEC_SEQ_END_LVL_MASK 0x0800 /* CODEC_SEQ_END_LVL */ | ||
819 | #define WM8400_CODEC_SEQ_END_LVL_SHIFT 11 /* CODEC_SEQ_END_LVL */ | ||
820 | #define WM8400_CODEC_SEQ_END_LVL_WIDTH 1 /* CODEC_SEQ_END_LVL */ | ||
821 | #define WM8400_CDEL_TO_LVL 0x0400 /* CDEL_TO_LVL */ | ||
822 | #define WM8400_CDEL_TO_LVL_MASK 0x0400 /* CDEL_TO_LVL */ | ||
823 | #define WM8400_CDEL_TO_LVL_SHIFT 10 /* CDEL_TO_LVL */ | ||
824 | #define WM8400_CDEL_TO_LVL_WIDTH 1 /* CDEL_TO_LVL */ | ||
825 | #define WM8400_CHIP_GT150_LVL 0x0200 /* CHIP_GT150_LVL */ | ||
826 | #define WM8400_CHIP_GT150_LVL_MASK 0x0200 /* CHIP_GT150_LVL */ | ||
827 | #define WM8400_CHIP_GT150_LVL_SHIFT 9 /* CHIP_GT150_LVL */ | ||
828 | #define WM8400_CHIP_GT150_LVL_WIDTH 1 /* CHIP_GT150_LVL */ | ||
829 | #define WM8400_CHIP_GT115_LVL 0x0100 /* CHIP_GT115_LVL */ | ||
830 | #define WM8400_CHIP_GT115_LVL_MASK 0x0100 /* CHIP_GT115_LVL */ | ||
831 | #define WM8400_CHIP_GT115_LVL_SHIFT 8 /* CHIP_GT115_LVL */ | ||
832 | #define WM8400_CHIP_GT115_LVL_WIDTH 1 /* CHIP_GT115_LVL */ | ||
833 | #define WM8400_LINE_CMP_LVL 0x0080 /* LINE_CMP_LVL */ | ||
834 | #define WM8400_LINE_CMP_LVL_MASK 0x0080 /* LINE_CMP_LVL */ | ||
835 | #define WM8400_LINE_CMP_LVL_SHIFT 7 /* LINE_CMP_LVL */ | ||
836 | #define WM8400_LINE_CMP_LVL_WIDTH 1 /* LINE_CMP_LVL */ | ||
837 | #define WM8400_UVLO_LVL 0x0040 /* UVLO_LVL */ | ||
838 | #define WM8400_UVLO_LVL_MASK 0x0040 /* UVLO_LVL */ | ||
839 | #define WM8400_UVLO_LVL_SHIFT 6 /* UVLO_LVL */ | ||
840 | #define WM8400_UVLO_LVL_WIDTH 1 /* UVLO_LVL */ | ||
841 | #define WM8400_DC2_UV_LVL 0x0020 /* DC2_UV_LVL */ | ||
842 | #define WM8400_DC2_UV_LVL_MASK 0x0020 /* DC2_UV_LVL */ | ||
843 | #define WM8400_DC2_UV_LVL_SHIFT 5 /* DC2_UV_LVL */ | ||
844 | #define WM8400_DC2_UV_LVL_WIDTH 1 /* DC2_UV_LVL */ | ||
845 | #define WM8400_DC1_UV_LVL 0x0010 /* DC1_UV_LVL */ | ||
846 | #define WM8400_DC1_UV_LVL_MASK 0x0010 /* DC1_UV_LVL */ | ||
847 | #define WM8400_DC1_UV_LVL_SHIFT 4 /* DC1_UV_LVL */ | ||
848 | #define WM8400_DC1_UV_LVL_WIDTH 1 /* DC1_UV_LVL */ | ||
849 | #define WM8400_LDO4_UV_LVL 0x0008 /* LDO4_UV_LVL */ | ||
850 | #define WM8400_LDO4_UV_LVL_MASK 0x0008 /* LDO4_UV_LVL */ | ||
851 | #define WM8400_LDO4_UV_LVL_SHIFT 3 /* LDO4_UV_LVL */ | ||
852 | #define WM8400_LDO4_UV_LVL_WIDTH 1 /* LDO4_UV_LVL */ | ||
853 | #define WM8400_LDO3_UV_LVL 0x0004 /* LDO3_UV_LVL */ | ||
854 | #define WM8400_LDO3_UV_LVL_MASK 0x0004 /* LDO3_UV_LVL */ | ||
855 | #define WM8400_LDO3_UV_LVL_SHIFT 2 /* LDO3_UV_LVL */ | ||
856 | #define WM8400_LDO3_UV_LVL_WIDTH 1 /* LDO3_UV_LVL */ | ||
857 | #define WM8400_LDO2_UV_LVL 0x0002 /* LDO2_UV_LVL */ | ||
858 | #define WM8400_LDO2_UV_LVL_MASK 0x0002 /* LDO2_UV_LVL */ | ||
859 | #define WM8400_LDO2_UV_LVL_SHIFT 1 /* LDO2_UV_LVL */ | ||
860 | #define WM8400_LDO2_UV_LVL_WIDTH 1 /* LDO2_UV_LVL */ | ||
861 | #define WM8400_LDO1_UV_LVL 0x0001 /* LDO1_UV_LVL */ | ||
862 | #define WM8400_LDO1_UV_LVL_MASK 0x0001 /* LDO1_UV_LVL */ | ||
863 | #define WM8400_LDO1_UV_LVL_SHIFT 0 /* LDO1_UV_LVL */ | ||
864 | #define WM8400_LDO1_UV_LVL_WIDTH 1 /* LDO1_UV_LVL */ | ||
865 | |||
866 | /* | ||
867 | * R82 (0x52) - Shutdown Reason | ||
868 | */ | ||
869 | #define WM8400_SDR_CHIP_SOFTSD 0x2000 /* SDR_CHIP_SOFTSD */ | ||
870 | #define WM8400_SDR_CHIP_SOFTSD_MASK 0x2000 /* SDR_CHIP_SOFTSD */ | ||
871 | #define WM8400_SDR_CHIP_SOFTSD_SHIFT 13 /* SDR_CHIP_SOFTSD */ | ||
872 | #define WM8400_SDR_CHIP_SOFTSD_WIDTH 1 /* SDR_CHIP_SOFTSD */ | ||
873 | #define WM8400_SDR_NPDN 0x0800 /* SDR_NPDN */ | ||
874 | #define WM8400_SDR_NPDN_MASK 0x0800 /* SDR_NPDN */ | ||
875 | #define WM8400_SDR_NPDN_SHIFT 11 /* SDR_NPDN */ | ||
876 | #define WM8400_SDR_NPDN_WIDTH 1 /* SDR_NPDN */ | ||
877 | #define WM8400_SDR_CHIP_GT150 0x0200 /* SDR_CHIP_GT150 */ | ||
878 | #define WM8400_SDR_CHIP_GT150_MASK 0x0200 /* SDR_CHIP_GT150 */ | ||
879 | #define WM8400_SDR_CHIP_GT150_SHIFT 9 /* SDR_CHIP_GT150 */ | ||
880 | #define WM8400_SDR_CHIP_GT150_WIDTH 1 /* SDR_CHIP_GT150 */ | ||
881 | #define WM8400_SDR_CHIP_GT115 0x0100 /* SDR_CHIP_GT115 */ | ||
882 | #define WM8400_SDR_CHIP_GT115_MASK 0x0100 /* SDR_CHIP_GT115 */ | ||
883 | #define WM8400_SDR_CHIP_GT115_SHIFT 8 /* SDR_CHIP_GT115 */ | ||
884 | #define WM8400_SDR_CHIP_GT115_WIDTH 1 /* SDR_CHIP_GT115 */ | ||
885 | #define WM8400_SDR_LINE_CMP 0x0080 /* SDR_LINE_CMP */ | ||
886 | #define WM8400_SDR_LINE_CMP_MASK 0x0080 /* SDR_LINE_CMP */ | ||
887 | #define WM8400_SDR_LINE_CMP_SHIFT 7 /* SDR_LINE_CMP */ | ||
888 | #define WM8400_SDR_LINE_CMP_WIDTH 1 /* SDR_LINE_CMP */ | ||
889 | #define WM8400_SDR_UVLO 0x0040 /* SDR_UVLO */ | ||
890 | #define WM8400_SDR_UVLO_MASK 0x0040 /* SDR_UVLO */ | ||
891 | #define WM8400_SDR_UVLO_SHIFT 6 /* SDR_UVLO */ | ||
892 | #define WM8400_SDR_UVLO_WIDTH 1 /* SDR_UVLO */ | ||
893 | #define WM8400_SDR_DC2_UV 0x0020 /* SDR_DC2_UV */ | ||
894 | #define WM8400_SDR_DC2_UV_MASK 0x0020 /* SDR_DC2_UV */ | ||
895 | #define WM8400_SDR_DC2_UV_SHIFT 5 /* SDR_DC2_UV */ | ||
896 | #define WM8400_SDR_DC2_UV_WIDTH 1 /* SDR_DC2_UV */ | ||
897 | #define WM8400_SDR_DC1_UV 0x0010 /* SDR_DC1_UV */ | ||
898 | #define WM8400_SDR_DC1_UV_MASK 0x0010 /* SDR_DC1_UV */ | ||
899 | #define WM8400_SDR_DC1_UV_SHIFT 4 /* SDR_DC1_UV */ | ||
900 | #define WM8400_SDR_DC1_UV_WIDTH 1 /* SDR_DC1_UV */ | ||
901 | #define WM8400_SDR_LDO4_UV 0x0008 /* SDR_LDO4_UV */ | ||
902 | #define WM8400_SDR_LDO4_UV_MASK 0x0008 /* SDR_LDO4_UV */ | ||
903 | #define WM8400_SDR_LDO4_UV_SHIFT 3 /* SDR_LDO4_UV */ | ||
904 | #define WM8400_SDR_LDO4_UV_WIDTH 1 /* SDR_LDO4_UV */ | ||
905 | #define WM8400_SDR_LDO3_UV 0x0004 /* SDR_LDO3_UV */ | ||
906 | #define WM8400_SDR_LDO3_UV_MASK 0x0004 /* SDR_LDO3_UV */ | ||
907 | #define WM8400_SDR_LDO3_UV_SHIFT 2 /* SDR_LDO3_UV */ | ||
908 | #define WM8400_SDR_LDO3_UV_WIDTH 1 /* SDR_LDO3_UV */ | ||
909 | #define WM8400_SDR_LDO2_UV 0x0002 /* SDR_LDO2_UV */ | ||
910 | #define WM8400_SDR_LDO2_UV_MASK 0x0002 /* SDR_LDO2_UV */ | ||
911 | #define WM8400_SDR_LDO2_UV_SHIFT 1 /* SDR_LDO2_UV */ | ||
912 | #define WM8400_SDR_LDO2_UV_WIDTH 1 /* SDR_LDO2_UV */ | ||
913 | #define WM8400_SDR_LDO1_UV 0x0001 /* SDR_LDO1_UV */ | ||
914 | #define WM8400_SDR_LDO1_UV_MASK 0x0001 /* SDR_LDO1_UV */ | ||
915 | #define WM8400_SDR_LDO1_UV_SHIFT 0 /* SDR_LDO1_UV */ | ||
916 | #define WM8400_SDR_LDO1_UV_WIDTH 1 /* SDR_LDO1_UV */ | ||
917 | |||
918 | /* | ||
919 | * R84 (0x54) - Line Circuits | ||
920 | */ | ||
921 | #define WM8400_BG_LINE_COMP 0x8000 /* BG_LINE_COMP */ | ||
922 | #define WM8400_BG_LINE_COMP_MASK 0x8000 /* BG_LINE_COMP */ | ||
923 | #define WM8400_BG_LINE_COMP_SHIFT 15 /* BG_LINE_COMP */ | ||
924 | #define WM8400_BG_LINE_COMP_WIDTH 1 /* BG_LINE_COMP */ | ||
925 | #define WM8400_LINE_CMP_VTHI_MASK 0x00F0 /* LINE_CMP_VTHI - [7:4] */ | ||
926 | #define WM8400_LINE_CMP_VTHI_SHIFT 4 /* LINE_CMP_VTHI - [7:4] */ | ||
927 | #define WM8400_LINE_CMP_VTHI_WIDTH 4 /* LINE_CMP_VTHI - [7:4] */ | ||
928 | #define WM8400_LINE_CMP_VTHD_MASK 0x000F /* LINE_CMP_VTHD - [3:0] */ | ||
929 | #define WM8400_LINE_CMP_VTHD_SHIFT 0 /* LINE_CMP_VTHD - [3:0] */ | ||
930 | #define WM8400_LINE_CMP_VTHD_WIDTH 4 /* LINE_CMP_VTHD - [3:0] */ | ||
931 | |||
932 | u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg); | ||
933 | int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data); | ||
934 | int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val); | ||
935 | |||
936 | #endif | ||