diff options
Diffstat (limited to 'include/linux/mfd/wm8350')
-rw-r--r-- | include/linux/mfd/wm8350/audio.h | 598 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/comparator.h | 167 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/core.h | 631 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/gpio.h | 342 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/pmic.h | 741 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/rtc.h | 266 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/supply.h | 111 | ||||
-rw-r--r-- | include/linux/mfd/wm8350/wdt.h | 28 |
8 files changed, 2884 insertions, 0 deletions
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h new file mode 100644 index 000000000000..217bb22ebb8e --- /dev/null +++ b/include/linux/mfd/wm8350/audio.h | |||
@@ -0,0 +1,598 @@ | |||
1 | /* | ||
2 | * audio.h -- Audio Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __LINUX_MFD_WM8350_AUDIO_H_ | ||
14 | #define __LINUX_MFD_WM8350_AUDIO_H_ | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | #define WM8350_CLOCK_CONTROL_1 0x28 | ||
19 | #define WM8350_CLOCK_CONTROL_2 0x29 | ||
20 | #define WM8350_FLL_CONTROL_1 0x2A | ||
21 | #define WM8350_FLL_CONTROL_2 0x2B | ||
22 | #define WM8350_FLL_CONTROL_3 0x2C | ||
23 | #define WM8350_FLL_CONTROL_4 0x2D | ||
24 | #define WM8350_DAC_CONTROL 0x30 | ||
25 | #define WM8350_DAC_DIGITAL_VOLUME_L 0x32 | ||
26 | #define WM8350_DAC_DIGITAL_VOLUME_R 0x33 | ||
27 | #define WM8350_DAC_LR_RATE 0x35 | ||
28 | #define WM8350_DAC_CLOCK_CONTROL 0x36 | ||
29 | #define WM8350_DAC_MUTE 0x3A | ||
30 | #define WM8350_DAC_MUTE_VOLUME 0x3B | ||
31 | #define WM8350_DAC_SIDE 0x3C | ||
32 | #define WM8350_ADC_CONTROL 0x40 | ||
33 | #define WM8350_ADC_DIGITAL_VOLUME_L 0x42 | ||
34 | #define WM8350_ADC_DIGITAL_VOLUME_R 0x43 | ||
35 | #define WM8350_ADC_DIVIDER 0x44 | ||
36 | #define WM8350_ADC_LR_RATE 0x46 | ||
37 | #define WM8350_INPUT_CONTROL 0x48 | ||
38 | #define WM8350_IN3_INPUT_CONTROL 0x49 | ||
39 | #define WM8350_MIC_BIAS_CONTROL 0x4A | ||
40 | #define WM8350_OUTPUT_CONTROL 0x4C | ||
41 | #define WM8350_JACK_DETECT 0x4D | ||
42 | #define WM8350_ANTI_POP_CONTROL 0x4E | ||
43 | #define WM8350_LEFT_INPUT_VOLUME 0x50 | ||
44 | #define WM8350_RIGHT_INPUT_VOLUME 0x51 | ||
45 | #define WM8350_LEFT_MIXER_CONTROL 0x58 | ||
46 | #define WM8350_RIGHT_MIXER_CONTROL 0x59 | ||
47 | #define WM8350_OUT3_MIXER_CONTROL 0x5C | ||
48 | #define WM8350_OUT4_MIXER_CONTROL 0x5D | ||
49 | #define WM8350_OUTPUT_LEFT_MIXER_VOLUME 0x60 | ||
50 | #define WM8350_OUTPUT_RIGHT_MIXER_VOLUME 0x61 | ||
51 | #define WM8350_INPUT_MIXER_VOLUME_L 0x62 | ||
52 | #define WM8350_INPUT_MIXER_VOLUME_R 0x63 | ||
53 | #define WM8350_INPUT_MIXER_VOLUME 0x64 | ||
54 | #define WM8350_LOUT1_VOLUME 0x68 | ||
55 | #define WM8350_ROUT1_VOLUME 0x69 | ||
56 | #define WM8350_LOUT2_VOLUME 0x6A | ||
57 | #define WM8350_ROUT2_VOLUME 0x6B | ||
58 | #define WM8350_BEEP_VOLUME 0x6F | ||
59 | #define WM8350_AI_FORMATING 0x70 | ||
60 | #define WM8350_ADC_DAC_COMP 0x71 | ||
61 | #define WM8350_AI_ADC_CONTROL 0x72 | ||
62 | #define WM8350_AI_DAC_CONTROL 0x73 | ||
63 | #define WM8350_AIF_TEST 0x74 | ||
64 | #define WM8350_JACK_PIN_STATUS 0xE7 | ||
65 | |||
66 | /* Bit values for R08 (0x08) */ | ||
67 | #define WM8350_CODEC_ISEL_1_5 0 /* x1.5 */ | ||
68 | #define WM8350_CODEC_ISEL_1_0 1 /* x1.0 */ | ||
69 | #define WM8350_CODEC_ISEL_0_75 2 /* x0.75 */ | ||
70 | #define WM8350_CODEC_ISEL_0_5 3 /* x0.5 */ | ||
71 | |||
72 | #define WM8350_VMID_OFF 0 | ||
73 | #define WM8350_VMID_500K 1 | ||
74 | #define WM8350_VMID_100K 2 | ||
75 | #define WM8350_VMID_10K 3 | ||
76 | |||
77 | /* | ||
78 | * R40 (0x28) - Clock Control 1 | ||
79 | */ | ||
80 | #define WM8350_TOCLK_RATE 0x4000 | ||
81 | #define WM8350_MCLK_SEL 0x0800 | ||
82 | #define WM8350_MCLK_DIV_MASK 0x0100 | ||
83 | #define WM8350_BCLK_DIV_MASK 0x00F0 | ||
84 | #define WM8350_OPCLK_DIV_MASK 0x0007 | ||
85 | |||
86 | /* | ||
87 | * R41 (0x29) - Clock Control 2 | ||
88 | */ | ||
89 | #define WM8350_LRC_ADC_SEL 0x8000 | ||
90 | #define WM8350_MCLK_DIR 0x0001 | ||
91 | |||
92 | /* | ||
93 | * R42 (0x2A) - FLL Control 1 | ||
94 | */ | ||
95 | #define WM8350_FLL_DITHER_WIDTH_MASK 0x3000 | ||
96 | #define WM8350_FLL_DITHER_HP 0x0800 | ||
97 | #define WM8350_FLL_OUTDIV_MASK 0x0700 | ||
98 | #define WM8350_FLL_RSP_RATE_MASK 0x00F0 | ||
99 | #define WM8350_FLL_RATE_MASK 0x0007 | ||
100 | |||
101 | /* | ||
102 | * R43 (0x2B) - FLL Control 2 | ||
103 | */ | ||
104 | #define WM8350_FLL_RATIO_MASK 0xF800 | ||
105 | #define WM8350_FLL_N_MASK 0x03FF | ||
106 | |||
107 | /* | ||
108 | * R44 (0x2C) - FLL Control 3 | ||
109 | */ | ||
110 | #define WM8350_FLL_K_MASK 0xFFFF | ||
111 | |||
112 | /* | ||
113 | * R45 (0x2D) - FLL Control 4 | ||
114 | */ | ||
115 | #define WM8350_FLL_FRAC 0x0020 | ||
116 | #define WM8350_FLL_SLOW_LOCK_REF 0x0010 | ||
117 | #define WM8350_FLL_CLK_SRC_MASK 0x0003 | ||
118 | |||
119 | /* | ||
120 | * R48 (0x30) - DAC Control | ||
121 | */ | ||
122 | #define WM8350_DAC_MONO 0x2000 | ||
123 | #define WM8350_AIF_LRCLKRATE 0x1000 | ||
124 | #define WM8350_DEEMP_MASK 0x0030 | ||
125 | #define WM8350_DACL_DATINV 0x0002 | ||
126 | #define WM8350_DACR_DATINV 0x0001 | ||
127 | |||
128 | /* | ||
129 | * R50 (0x32) - DAC Digital Volume L | ||
130 | */ | ||
131 | #define WM8350_DAC_VU 0x0100 | ||
132 | #define WM8350_DACL_VOL_MASK 0x00FF | ||
133 | |||
134 | /* | ||
135 | * R51 (0x33) - DAC Digital Volume R | ||
136 | */ | ||
137 | #define WM8350_DAC_VU 0x0100 | ||
138 | #define WM8350_DACR_VOL_MASK 0x00FF | ||
139 | |||
140 | /* | ||
141 | * R53 (0x35) - DAC LR Rate | ||
142 | */ | ||
143 | #define WM8350_DACLRC_ENA 0x0800 | ||
144 | #define WM8350_DACLRC_RATE_MASK 0x07FF | ||
145 | |||
146 | /* | ||
147 | * R54 (0x36) - DAC Clock Control | ||
148 | */ | ||
149 | #define WM8350_DACCLK_POL 0x0010 | ||
150 | #define WM8350_DAC_CLKDIV_MASK 0x0007 | ||
151 | |||
152 | /* | ||
153 | * R58 (0x3A) - DAC Mute | ||
154 | */ | ||
155 | #define WM8350_DAC_MUTE_ENA 0x4000 | ||
156 | |||
157 | /* | ||
158 | * R59 (0x3B) - DAC Mute Volume | ||
159 | */ | ||
160 | #define WM8350_DAC_MUTEMODE 0x4000 | ||
161 | #define WM8350_DAC_MUTERATE 0x2000 | ||
162 | #define WM8350_DAC_SB_FILT 0x1000 | ||
163 | |||
164 | /* | ||
165 | * R60 (0x3C) - DAC Side | ||
166 | */ | ||
167 | #define WM8350_ADC_TO_DACL_MASK 0x3000 | ||
168 | #define WM8350_ADC_TO_DACR_MASK 0x0C00 | ||
169 | |||
170 | /* | ||
171 | * R64 (0x40) - ADC Control | ||
172 | */ | ||
173 | #define WM8350_ADC_HPF_CUT_MASK 0x0300 | ||
174 | #define WM8350_ADCL_DATINV 0x0002 | ||
175 | #define WM8350_ADCR_DATINV 0x0001 | ||
176 | |||
177 | /* | ||
178 | * R66 (0x42) - ADC Digital Volume L | ||
179 | */ | ||
180 | #define WM8350_ADC_VU 0x0100 | ||
181 | #define WM8350_ADCL_VOL_MASK 0x00FF | ||
182 | |||
183 | /* | ||
184 | * R67 (0x43) - ADC Digital Volume R | ||
185 | */ | ||
186 | #define WM8350_ADC_VU 0x0100 | ||
187 | #define WM8350_ADCR_VOL_MASK 0x00FF | ||
188 | |||
189 | /* | ||
190 | * R68 (0x44) - ADC Divider | ||
191 | */ | ||
192 | #define WM8350_ADCL_DAC_SVOL_MASK 0x0F00 | ||
193 | #define WM8350_ADCR_DAC_SVOL_MASK 0x00F0 | ||
194 | #define WM8350_ADCCLK_POL 0x0008 | ||
195 | #define WM8350_ADC_CLKDIV_MASK 0x0007 | ||
196 | |||
197 | /* | ||
198 | * R70 (0x46) - ADC LR Rate | ||
199 | */ | ||
200 | #define WM8350_ADCLRC_ENA 0x0800 | ||
201 | #define WM8350_ADCLRC_RATE_MASK 0x07FF | ||
202 | |||
203 | /* | ||
204 | * R72 (0x48) - Input Control | ||
205 | */ | ||
206 | #define WM8350_IN2R_ENA 0x0400 | ||
207 | #define WM8350_IN1RN_ENA 0x0200 | ||
208 | #define WM8350_IN1RP_ENA 0x0100 | ||
209 | #define WM8350_IN2L_ENA 0x0004 | ||
210 | #define WM8350_IN1LN_ENA 0x0002 | ||
211 | #define WM8350_IN1LP_ENA 0x0001 | ||
212 | |||
213 | /* | ||
214 | * R73 (0x49) - IN3 Input Control | ||
215 | */ | ||
216 | #define WM8350_IN3R_SHORT 0x4000 | ||
217 | #define WM8350_IN3L_SHORT 0x0040 | ||
218 | |||
219 | /* | ||
220 | * R74 (0x4A) - Mic Bias Control | ||
221 | */ | ||
222 | #define WM8350_MICBSEL 0x4000 | ||
223 | #define WM8350_MCDTHR_MASK 0x001C | ||
224 | #define WM8350_MCDSCTHR_MASK 0x0003 | ||
225 | |||
226 | /* | ||
227 | * R76 (0x4C) - Output Control | ||
228 | */ | ||
229 | #define WM8350_OUT4_VROI 0x0800 | ||
230 | #define WM8350_OUT3_VROI 0x0400 | ||
231 | #define WM8350_OUT2_VROI 0x0200 | ||
232 | #define WM8350_OUT1_VROI 0x0100 | ||
233 | #define WM8350_OUT2_FB 0x0004 | ||
234 | #define WM8350_OUT1_FB 0x0001 | ||
235 | |||
236 | /* | ||
237 | * R77 (0x4D) - Jack Detect | ||
238 | */ | ||
239 | #define WM8350_JDL_ENA 0x8000 | ||
240 | #define WM8350_JDR_ENA 0x4000 | ||
241 | |||
242 | /* | ||
243 | * R78 (0x4E) - Anti Pop Control | ||
244 | */ | ||
245 | #define WM8350_ANTI_POP_MASK 0x0300 | ||
246 | #define WM8350_DIS_OP_LN4_MASK 0x00C0 | ||
247 | #define WM8350_DIS_OP_LN3_MASK 0x0030 | ||
248 | #define WM8350_DIS_OP_OUT2_MASK 0x000C | ||
249 | #define WM8350_DIS_OP_OUT1_MASK 0x0003 | ||
250 | |||
251 | /* | ||
252 | * R80 (0x50) - Left Input Volume | ||
253 | */ | ||
254 | #define WM8350_INL_MUTE 0x4000 | ||
255 | #define WM8350_INL_ZC 0x2000 | ||
256 | #define WM8350_IN_VU 0x0100 | ||
257 | #define WM8350_INL_VOL_MASK 0x00FC | ||
258 | |||
259 | /* | ||
260 | * R81 (0x51) - Right Input Volume | ||
261 | */ | ||
262 | #define WM8350_INR_MUTE 0x4000 | ||
263 | #define WM8350_INR_ZC 0x2000 | ||
264 | #define WM8350_IN_VU 0x0100 | ||
265 | #define WM8350_INR_VOL_MASK 0x00FC | ||
266 | |||
267 | /* | ||
268 | * R88 (0x58) - Left Mixer Control | ||
269 | */ | ||
270 | #define WM8350_DACR_TO_MIXOUTL 0x1000 | ||
271 | #define WM8350_DACL_TO_MIXOUTL 0x0800 | ||
272 | #define WM8350_IN3L_TO_MIXOUTL 0x0004 | ||
273 | #define WM8350_INR_TO_MIXOUTL 0x0002 | ||
274 | #define WM8350_INL_TO_MIXOUTL 0x0001 | ||
275 | |||
276 | /* | ||
277 | * R89 (0x59) - Right Mixer Control | ||
278 | */ | ||
279 | #define WM8350_DACR_TO_MIXOUTR 0x1000 | ||
280 | #define WM8350_DACL_TO_MIXOUTR 0x0800 | ||
281 | #define WM8350_IN3R_TO_MIXOUTR 0x0008 | ||
282 | #define WM8350_INR_TO_MIXOUTR 0x0002 | ||
283 | #define WM8350_INL_TO_MIXOUTR 0x0001 | ||
284 | |||
285 | /* | ||
286 | * R92 (0x5C) - OUT3 Mixer Control | ||
287 | */ | ||
288 | #define WM8350_DACL_TO_OUT3 0x0800 | ||
289 | #define WM8350_MIXINL_TO_OUT3 0x0100 | ||
290 | #define WM8350_OUT4_TO_OUT3 0x0008 | ||
291 | #define WM8350_MIXOUTL_TO_OUT3 0x0001 | ||
292 | |||
293 | /* | ||
294 | * R93 (0x5D) - OUT4 Mixer Control | ||
295 | */ | ||
296 | #define WM8350_DACR_TO_OUT4 0x1000 | ||
297 | #define WM8350_DACL_TO_OUT4 0x0800 | ||
298 | #define WM8350_OUT4_ATTN 0x0400 | ||
299 | #define WM8350_MIXINR_TO_OUT4 0x0200 | ||
300 | #define WM8350_OUT3_TO_OUT4 0x0004 | ||
301 | #define WM8350_MIXOUTR_TO_OUT4 0x0002 | ||
302 | #define WM8350_MIXOUTL_TO_OUT4 0x0001 | ||
303 | |||
304 | /* | ||
305 | * R96 (0x60) - Output Left Mixer Volume | ||
306 | */ | ||
307 | #define WM8350_IN3L_MIXOUTL_VOL_MASK 0x0E00 | ||
308 | #define WM8350_IN3L_MIXOUTL_VOL_SHIFT 9 | ||
309 | #define WM8350_INR_MIXOUTL_VOL_MASK 0x00E0 | ||
310 | #define WM8350_INR_MIXOUTL_VOL_SHIFT 5 | ||
311 | #define WM8350_INL_MIXOUTL_VOL_MASK 0x000E | ||
312 | #define WM8350_INL_MIXOUTL_VOL_SHIFT 1 | ||
313 | |||
314 | /* Bit values for R96 (0x60) */ | ||
315 | #define WM8350_IN3L_MIXOUTL_VOL_OFF 0 | ||
316 | #define WM8350_IN3L_MIXOUTL_VOL_M12DB 1 | ||
317 | #define WM8350_IN3L_MIXOUTL_VOL_M9DB 2 | ||
318 | #define WM8350_IN3L_MIXOUTL_VOL_M6DB 3 | ||
319 | #define WM8350_IN3L_MIXOUTL_VOL_M3DB 4 | ||
320 | #define WM8350_IN3L_MIXOUTL_VOL_0DB 5 | ||
321 | #define WM8350_IN3L_MIXOUTL_VOL_3DB 6 | ||
322 | #define WM8350_IN3L_MIXOUTL_VOL_6DB 7 | ||
323 | |||
324 | #define WM8350_INR_MIXOUTL_VOL_OFF 0 | ||
325 | #define WM8350_INR_MIXOUTL_VOL_M12DB 1 | ||
326 | #define WM8350_INR_MIXOUTL_VOL_M9DB 2 | ||
327 | #define WM8350_INR_MIXOUTL_VOL_M6DB 3 | ||
328 | #define WM8350_INR_MIXOUTL_VOL_M3DB 4 | ||
329 | #define WM8350_INR_MIXOUTL_VOL_0DB 5 | ||
330 | #define WM8350_INR_MIXOUTL_VOL_3DB 6 | ||
331 | #define WM8350_INR_MIXOUTL_VOL_6DB 7 | ||
332 | |||
333 | #define WM8350_INL_MIXOUTL_VOL_OFF 0 | ||
334 | #define WM8350_INL_MIXOUTL_VOL_M12DB 1 | ||
335 | #define WM8350_INL_MIXOUTL_VOL_M9DB 2 | ||
336 | #define WM8350_INL_MIXOUTL_VOL_M6DB 3 | ||
337 | #define WM8350_INL_MIXOUTL_VOL_M3DB 4 | ||
338 | #define WM8350_INL_MIXOUTL_VOL_0DB 5 | ||
339 | #define WM8350_INL_MIXOUTL_VOL_3DB 6 | ||
340 | #define WM8350_INL_MIXOUTL_VOL_6DB 7 | ||
341 | |||
342 | /* | ||
343 | * R97 (0x61) - Output Right Mixer Volume | ||
344 | */ | ||
345 | #define WM8350_IN3R_MIXOUTR_VOL_MASK 0xE000 | ||
346 | #define WM8350_IN3R_MIXOUTR_VOL_SHIFT 13 | ||
347 | #define WM8350_INR_MIXOUTR_VOL_MASK 0x00E0 | ||
348 | #define WM8350_INR_MIXOUTR_VOL_SHIFT 5 | ||
349 | #define WM8350_INL_MIXOUTR_VOL_MASK 0x000E | ||
350 | #define WM8350_INL_MIXOUTR_VOL_SHIFT 1 | ||
351 | |||
352 | /* Bit values for R96 (0x60) */ | ||
353 | #define WM8350_IN3R_MIXOUTR_VOL_OFF 0 | ||
354 | #define WM8350_IN3R_MIXOUTR_VOL_M12DB 1 | ||
355 | #define WM8350_IN3R_MIXOUTR_VOL_M9DB 2 | ||
356 | #define WM8350_IN3R_MIXOUTR_VOL_M6DB 3 | ||
357 | #define WM8350_IN3R_MIXOUTR_VOL_M3DB 4 | ||
358 | #define WM8350_IN3R_MIXOUTR_VOL_0DB 5 | ||
359 | #define WM8350_IN3R_MIXOUTR_VOL_3DB 6 | ||
360 | #define WM8350_IN3R_MIXOUTR_VOL_6DB 7 | ||
361 | |||
362 | #define WM8350_INR_MIXOUTR_VOL_OFF 0 | ||
363 | #define WM8350_INR_MIXOUTR_VOL_M12DB 1 | ||
364 | #define WM8350_INR_MIXOUTR_VOL_M9DB 2 | ||
365 | #define WM8350_INR_MIXOUTR_VOL_M6DB 3 | ||
366 | #define WM8350_INR_MIXOUTR_VOL_M3DB 4 | ||
367 | #define WM8350_INR_MIXOUTR_VOL_0DB 5 | ||
368 | #define WM8350_INR_MIXOUTR_VOL_3DB 6 | ||
369 | #define WM8350_INR_MIXOUTR_VOL_6DB 7 | ||
370 | |||
371 | #define WM8350_INL_MIXOUTR_VOL_OFF 0 | ||
372 | #define WM8350_INL_MIXOUTR_VOL_M12DB 1 | ||
373 | #define WM8350_INL_MIXOUTR_VOL_M9DB 2 | ||
374 | #define WM8350_INL_MIXOUTR_VOL_M6DB 3 | ||
375 | #define WM8350_INL_MIXOUTR_VOL_M3DB 4 | ||
376 | #define WM8350_INL_MIXOUTR_VOL_0DB 5 | ||
377 | #define WM8350_INL_MIXOUTR_VOL_3DB 6 | ||
378 | #define WM8350_INL_MIXOUTR_VOL_6DB 7 | ||
379 | |||
380 | /* | ||
381 | * R98 (0x62) - Input Mixer Volume L | ||
382 | */ | ||
383 | #define WM8350_IN3L_MIXINL_VOL_MASK 0x0E00 | ||
384 | #define WM8350_IN2L_MIXINL_VOL_MASK 0x000E | ||
385 | #define WM8350_INL_MIXINL_VOL 0x0001 | ||
386 | |||
387 | /* | ||
388 | * R99 (0x63) - Input Mixer Volume R | ||
389 | */ | ||
390 | #define WM8350_IN3R_MIXINR_VOL_MASK 0xE000 | ||
391 | #define WM8350_IN2R_MIXINR_VOL_MASK 0x00E0 | ||
392 | #define WM8350_INR_MIXINR_VOL 0x0001 | ||
393 | |||
394 | /* | ||
395 | * R100 (0x64) - Input Mixer Volume | ||
396 | */ | ||
397 | #define WM8350_OUT4_MIXIN_DST 0x8000 | ||
398 | #define WM8350_OUT4_MIXIN_VOL_MASK 0x000E | ||
399 | |||
400 | /* | ||
401 | * R104 (0x68) - LOUT1 Volume | ||
402 | */ | ||
403 | #define WM8350_OUT1L_MUTE 0x4000 | ||
404 | #define WM8350_OUT1L_ZC 0x2000 | ||
405 | #define WM8350_OUT1_VU 0x0100 | ||
406 | #define WM8350_OUT1L_VOL_MASK 0x00FC | ||
407 | #define WM8350_OUT1L_VOL_SHIFT 2 | ||
408 | |||
409 | /* | ||
410 | * R105 (0x69) - ROUT1 Volume | ||
411 | */ | ||
412 | #define WM8350_OUT1R_MUTE 0x4000 | ||
413 | #define WM8350_OUT1R_ZC 0x2000 | ||
414 | #define WM8350_OUT1_VU 0x0100 | ||
415 | #define WM8350_OUT1R_VOL_MASK 0x00FC | ||
416 | #define WM8350_OUT1R_VOL_SHIFT 2 | ||
417 | |||
418 | /* | ||
419 | * R106 (0x6A) - LOUT2 Volume | ||
420 | */ | ||
421 | #define WM8350_OUT2L_MUTE 0x4000 | ||
422 | #define WM8350_OUT2L_ZC 0x2000 | ||
423 | #define WM8350_OUT2_VU 0x0100 | ||
424 | #define WM8350_OUT2L_VOL_MASK 0x00FC | ||
425 | |||
426 | /* | ||
427 | * R107 (0x6B) - ROUT2 Volume | ||
428 | */ | ||
429 | #define WM8350_OUT2R_MUTE 0x4000 | ||
430 | #define WM8350_OUT2R_ZC 0x2000 | ||
431 | #define WM8350_OUT2R_INV 0x0400 | ||
432 | #define WM8350_OUT2R_INV_MUTE 0x0200 | ||
433 | #define WM8350_OUT2_VU 0x0100 | ||
434 | #define WM8350_OUT2R_VOL_MASK 0x00FC | ||
435 | |||
436 | /* | ||
437 | * R111 (0x6F) - BEEP Volume | ||
438 | */ | ||
439 | #define WM8350_IN3R_OUT2R_VOL_MASK 0x00E0 | ||
440 | |||
441 | /* | ||
442 | * R112 (0x70) - AI Formating | ||
443 | */ | ||
444 | #define WM8350_AIF_BCLK_INV 0x8000 | ||
445 | #define WM8350_AIF_TRI 0x2000 | ||
446 | #define WM8350_AIF_LRCLK_INV 0x1000 | ||
447 | #define WM8350_AIF_WL_MASK 0x0C00 | ||
448 | #define WM8350_AIF_FMT_MASK 0x0300 | ||
449 | |||
450 | /* | ||
451 | * R113 (0x71) - ADC DAC COMP | ||
452 | */ | ||
453 | #define WM8350_DAC_COMP 0x0080 | ||
454 | #define WM8350_DAC_COMPMODE 0x0040 | ||
455 | #define WM8350_ADC_COMP 0x0020 | ||
456 | #define WM8350_ADC_COMPMODE 0x0010 | ||
457 | #define WM8350_LOOPBACK 0x0001 | ||
458 | |||
459 | /* | ||
460 | * R114 (0x72) - AI ADC Control | ||
461 | */ | ||
462 | #define WM8350_AIFADC_PD 0x0080 | ||
463 | #define WM8350_AIFADCL_SRC 0x0040 | ||
464 | #define WM8350_AIFADCR_SRC 0x0020 | ||
465 | #define WM8350_AIFADC_TDM_CHAN 0x0010 | ||
466 | #define WM8350_AIFADC_TDM 0x0008 | ||
467 | |||
468 | /* | ||
469 | * R115 (0x73) - AI DAC Control | ||
470 | */ | ||
471 | #define WM8350_BCLK_MSTR 0x4000 | ||
472 | #define WM8350_AIFDAC_PD 0x0080 | ||
473 | #define WM8350_DACL_SRC 0x0040 | ||
474 | #define WM8350_DACR_SRC 0x0020 | ||
475 | #define WM8350_AIFDAC_TDM_CHAN 0x0010 | ||
476 | #define WM8350_AIFDAC_TDM 0x0008 | ||
477 | #define WM8350_DAC_BOOST_MASK 0x0003 | ||
478 | |||
479 | /* | ||
480 | * R116 (0x74) - AIF Test | ||
481 | */ | ||
482 | #define WM8350_CODEC_BYP 0x4000 | ||
483 | #define WM8350_AIFADC_WR_TST 0x2000 | ||
484 | #define WM8350_AIFADC_RD_TST 0x1000 | ||
485 | #define WM8350_AIFDAC_WR_TST 0x0800 | ||
486 | #define WM8350_AIFDAC_RD_TST 0x0400 | ||
487 | #define WM8350_AIFADC_ASYN 0x0020 | ||
488 | #define WM8350_AIFDAC_ASYN 0x0010 | ||
489 | |||
490 | /* | ||
491 | * R231 (0xE7) - Jack Status | ||
492 | */ | ||
493 | #define WM8350_JACK_R_LVL 0x0400 | ||
494 | |||
495 | /* | ||
496 | * WM8350 Platform setup | ||
497 | */ | ||
498 | #define WM8350_S_CURVE_NONE 0x0 | ||
499 | #define WM8350_S_CURVE_FAST 0x1 | ||
500 | #define WM8350_S_CURVE_MEDIUM 0x2 | ||
501 | #define WM8350_S_CURVE_SLOW 0x3 | ||
502 | |||
503 | #define WM8350_DISCHARGE_OFF 0x0 | ||
504 | #define WM8350_DISCHARGE_FAST 0x1 | ||
505 | #define WM8350_DISCHARGE_MEDIUM 0x2 | ||
506 | #define WM8350_DISCHARGE_SLOW 0x3 | ||
507 | |||
508 | #define WM8350_TIE_OFF_500R 0x0 | ||
509 | #define WM8350_TIE_OFF_30K 0x1 | ||
510 | |||
511 | /* | ||
512 | * Clock sources & directions | ||
513 | */ | ||
514 | #define WM8350_SYSCLK 0 | ||
515 | |||
516 | #define WM8350_MCLK_SEL_PLL_MCLK 0 | ||
517 | #define WM8350_MCLK_SEL_PLL_DAC 1 | ||
518 | #define WM8350_MCLK_SEL_PLL_ADC 2 | ||
519 | #define WM8350_MCLK_SEL_PLL_32K 3 | ||
520 | #define WM8350_MCLK_SEL_MCLK 5 | ||
521 | |||
522 | #define WM8350_MCLK_DIR_OUT 0 | ||
523 | #define WM8350_MCLK_DIR_IN 1 | ||
524 | |||
525 | /* clock divider id's */ | ||
526 | #define WM8350_ADC_CLKDIV 0 | ||
527 | #define WM8350_DAC_CLKDIV 1 | ||
528 | #define WM8350_BCLK_CLKDIV 2 | ||
529 | #define WM8350_OPCLK_CLKDIV 3 | ||
530 | #define WM8350_TO_CLKDIV 4 | ||
531 | #define WM8350_SYS_CLKDIV 5 | ||
532 | #define WM8350_DACLR_CLKDIV 6 | ||
533 | #define WM8350_ADCLR_CLKDIV 7 | ||
534 | |||
535 | /* ADC clock dividers */ | ||
536 | #define WM8350_ADCDIV_1 0x0 | ||
537 | #define WM8350_ADCDIV_1_5 0x1 | ||
538 | #define WM8350_ADCDIV_2 0x2 | ||
539 | #define WM8350_ADCDIV_3 0x3 | ||
540 | #define WM8350_ADCDIV_4 0x4 | ||
541 | #define WM8350_ADCDIV_5_5 0x5 | ||
542 | #define WM8350_ADCDIV_6 0x6 | ||
543 | |||
544 | /* ADC clock dividers */ | ||
545 | #define WM8350_DACDIV_1 0x0 | ||
546 | #define WM8350_DACDIV_1_5 0x1 | ||
547 | #define WM8350_DACDIV_2 0x2 | ||
548 | #define WM8350_DACDIV_3 0x3 | ||
549 | #define WM8350_DACDIV_4 0x4 | ||
550 | #define WM8350_DACDIV_5_5 0x5 | ||
551 | #define WM8350_DACDIV_6 0x6 | ||
552 | |||
553 | /* BCLK clock dividers */ | ||
554 | #define WM8350_BCLK_DIV_1 (0x0 << 4) | ||
555 | #define WM8350_BCLK_DIV_1_5 (0x1 << 4) | ||
556 | #define WM8350_BCLK_DIV_2 (0x2 << 4) | ||
557 | #define WM8350_BCLK_DIV_3 (0x3 << 4) | ||
558 | #define WM8350_BCLK_DIV_4 (0x4 << 4) | ||
559 | #define WM8350_BCLK_DIV_5_5 (0x5 << 4) | ||
560 | #define WM8350_BCLK_DIV_6 (0x6 << 4) | ||
561 | #define WM8350_BCLK_DIV_8 (0x7 << 4) | ||
562 | #define WM8350_BCLK_DIV_11 (0x8 << 4) | ||
563 | #define WM8350_BCLK_DIV_12 (0x9 << 4) | ||
564 | #define WM8350_BCLK_DIV_16 (0xa << 4) | ||
565 | #define WM8350_BCLK_DIV_22 (0xb << 4) | ||
566 | #define WM8350_BCLK_DIV_24 (0xc << 4) | ||
567 | #define WM8350_BCLK_DIV_32 (0xd << 4) | ||
568 | #define WM8350_BCLK_DIV_44 (0xe << 4) | ||
569 | #define WM8350_BCLK_DIV_48 (0xf << 4) | ||
570 | |||
571 | /* Sys (MCLK) clock dividers */ | ||
572 | #define WM8350_MCLK_DIV_1 (0x0 << 8) | ||
573 | #define WM8350_MCLK_DIV_2 (0x1 << 8) | ||
574 | |||
575 | /* OP clock dividers */ | ||
576 | #define WM8350_OPCLK_DIV_1 0x0 | ||
577 | #define WM8350_OPCLK_DIV_2 0x1 | ||
578 | #define WM8350_OPCLK_DIV_3 0x2 | ||
579 | #define WM8350_OPCLK_DIV_4 0x3 | ||
580 | #define WM8350_OPCLK_DIV_5_5 0x4 | ||
581 | #define WM8350_OPCLK_DIV_6 0x5 | ||
582 | |||
583 | /* DAI ID */ | ||
584 | #define WM8350_HIFI_DAI 0 | ||
585 | |||
586 | /* | ||
587 | * Audio interrupts. | ||
588 | */ | ||
589 | #define WM8350_IRQ_CODEC_JCK_DET_L 39 | ||
590 | #define WM8350_IRQ_CODEC_JCK_DET_R 40 | ||
591 | #define WM8350_IRQ_CODEC_MICSCD 41 | ||
592 | #define WM8350_IRQ_CODEC_MICD 42 | ||
593 | |||
594 | struct wm8350_codec { | ||
595 | struct platform_device *pdev; | ||
596 | }; | ||
597 | |||
598 | #endif | ||
diff --git a/include/linux/mfd/wm8350/comparator.h b/include/linux/mfd/wm8350/comparator.h new file mode 100644 index 000000000000..053788649452 --- /dev/null +++ b/include/linux/mfd/wm8350/comparator.h | |||
@@ -0,0 +1,167 @@ | |||
1 | /* | ||
2 | * comparator.h -- Comparator Aux ADC for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __LINUX_MFD_WM8350_COMPARATOR_H_ | ||
13 | #define __LINUX_MFD_WM8350_COMPARATOR_H_ | ||
14 | |||
15 | /* | ||
16 | * Registers | ||
17 | */ | ||
18 | |||
19 | #define WM8350_DIGITISER_CONTROL_1 0x90 | ||
20 | #define WM8350_DIGITISER_CONTROL_2 0x91 | ||
21 | #define WM8350_AUX1_READBACK 0x98 | ||
22 | #define WM8350_AUX2_READBACK 0x99 | ||
23 | #define WM8350_AUX3_READBACK 0x9A | ||
24 | #define WM8350_AUX4_READBACK 0x9B | ||
25 | #define WM8350_CHIP_TEMP_READBACK 0x9F | ||
26 | #define WM8350_GENERIC_COMPARATOR_CONTROL 0xA3 | ||
27 | #define WM8350_GENERIC_COMPARATOR_1 0xA4 | ||
28 | #define WM8350_GENERIC_COMPARATOR_2 0xA5 | ||
29 | #define WM8350_GENERIC_COMPARATOR_3 0xA6 | ||
30 | #define WM8350_GENERIC_COMPARATOR_4 0xA7 | ||
31 | |||
32 | /* | ||
33 | * R144 (0x90) - Digitiser Control (1) | ||
34 | */ | ||
35 | #define WM8350_AUXADC_CTC 0x4000 | ||
36 | #define WM8350_AUXADC_POLL 0x2000 | ||
37 | #define WM8350_AUXADC_HIB_MODE 0x1000 | ||
38 | #define WM8350_AUXADC_SEL8 0x0080 | ||
39 | #define WM8350_AUXADC_SEL7 0x0040 | ||
40 | #define WM8350_AUXADC_SEL6 0x0020 | ||
41 | #define WM8350_AUXADC_SEL5 0x0010 | ||
42 | #define WM8350_AUXADC_SEL4 0x0008 | ||
43 | #define WM8350_AUXADC_SEL3 0x0004 | ||
44 | #define WM8350_AUXADC_SEL2 0x0002 | ||
45 | #define WM8350_AUXADC_SEL1 0x0001 | ||
46 | |||
47 | /* | ||
48 | * R145 (0x91) - Digitiser Control (2) | ||
49 | */ | ||
50 | #define WM8350_AUXADC_MASKMODE_MASK 0x3000 | ||
51 | #define WM8350_AUXADC_CRATE_MASK 0x0700 | ||
52 | #define WM8350_AUXADC_CAL 0x0004 | ||
53 | #define WM8350_AUX_RBMODE 0x0002 | ||
54 | #define WM8350_AUXADC_WAIT 0x0001 | ||
55 | |||
56 | /* | ||
57 | * R152 (0x98) - AUX1 Readback | ||
58 | */ | ||
59 | #define WM8350_AUXADC_SCALE1_MASK 0x6000 | ||
60 | #define WM8350_AUXADC_REF1 0x1000 | ||
61 | #define WM8350_AUXADC_DATA1_MASK 0x0FFF | ||
62 | |||
63 | /* | ||
64 | * R153 (0x99) - AUX2 Readback | ||
65 | */ | ||
66 | #define WM8350_AUXADC_SCALE2_MASK 0x6000 | ||
67 | #define WM8350_AUXADC_REF2 0x1000 | ||
68 | #define WM8350_AUXADC_DATA2_MASK 0x0FFF | ||
69 | |||
70 | /* | ||
71 | * R154 (0x9A) - AUX3 Readback | ||
72 | */ | ||
73 | #define WM8350_AUXADC_SCALE3_MASK 0x6000 | ||
74 | #define WM8350_AUXADC_REF3 0x1000 | ||
75 | #define WM8350_AUXADC_DATA3_MASK 0x0FFF | ||
76 | |||
77 | /* | ||
78 | * R155 (0x9B) - AUX4 Readback | ||
79 | */ | ||
80 | #define WM8350_AUXADC_SCALE4_MASK 0x6000 | ||
81 | #define WM8350_AUXADC_REF4 0x1000 | ||
82 | #define WM8350_AUXADC_DATA4_MASK 0x0FFF | ||
83 | |||
84 | /* | ||
85 | * R156 (0x9C) - USB Voltage Readback | ||
86 | */ | ||
87 | #define WM8350_AUXADC_DATA_USB_MASK 0x0FFF | ||
88 | |||
89 | /* | ||
90 | * R157 (0x9D) - LINE Voltage Readback | ||
91 | */ | ||
92 | #define WM8350_AUXADC_DATA_LINE_MASK 0x0FFF | ||
93 | |||
94 | /* | ||
95 | * R158 (0x9E) - BATT Voltage Readback | ||
96 | */ | ||
97 | #define WM8350_AUXADC_DATA_BATT_MASK 0x0FFF | ||
98 | |||
99 | /* | ||
100 | * R159 (0x9F) - Chip Temp Readback | ||
101 | */ | ||
102 | #define WM8350_AUXADC_DATA_CHIPTEMP_MASK 0x0FFF | ||
103 | |||
104 | /* | ||
105 | * R163 (0xA3) - Generic Comparator Control | ||
106 | */ | ||
107 | #define WM8350_DCMP4_ENA 0x0008 | ||
108 | #define WM8350_DCMP3_ENA 0x0004 | ||
109 | #define WM8350_DCMP2_ENA 0x0002 | ||
110 | #define WM8350_DCMP1_ENA 0x0001 | ||
111 | |||
112 | /* | ||
113 | * R164 (0xA4) - Generic comparator 1 | ||
114 | */ | ||
115 | #define WM8350_DCMP1_SRCSEL_MASK 0xE000 | ||
116 | #define WM8350_DCMP1_GT 0x1000 | ||
117 | #define WM8350_DCMP1_THR_MASK 0x0FFF | ||
118 | |||
119 | /* | ||
120 | * R165 (0xA5) - Generic comparator 2 | ||
121 | */ | ||
122 | #define WM8350_DCMP2_SRCSEL_MASK 0xE000 | ||
123 | #define WM8350_DCMP2_GT 0x1000 | ||
124 | #define WM8350_DCMP2_THR_MASK 0x0FFF | ||
125 | |||
126 | /* | ||
127 | * R166 (0xA6) - Generic comparator 3 | ||
128 | */ | ||
129 | #define WM8350_DCMP3_SRCSEL_MASK 0xE000 | ||
130 | #define WM8350_DCMP3_GT 0x1000 | ||
131 | #define WM8350_DCMP3_THR_MASK 0x0FFF | ||
132 | |||
133 | /* | ||
134 | * R167 (0xA7) - Generic comparator 4 | ||
135 | */ | ||
136 | #define WM8350_DCMP4_SRCSEL_MASK 0xE000 | ||
137 | #define WM8350_DCMP4_GT 0x1000 | ||
138 | #define WM8350_DCMP4_THR_MASK 0x0FFF | ||
139 | |||
140 | /* | ||
141 | * Interrupts. | ||
142 | */ | ||
143 | #define WM8350_IRQ_AUXADC_DATARDY 16 | ||
144 | #define WM8350_IRQ_AUXADC_DCOMP4 17 | ||
145 | #define WM8350_IRQ_AUXADC_DCOMP3 18 | ||
146 | #define WM8350_IRQ_AUXADC_DCOMP2 19 | ||
147 | #define WM8350_IRQ_AUXADC_DCOMP1 20 | ||
148 | #define WM8350_IRQ_SYS_HYST_COMP_FAIL 21 | ||
149 | #define WM8350_IRQ_SYS_CHIP_GT115 22 | ||
150 | #define WM8350_IRQ_SYS_CHIP_GT140 23 | ||
151 | |||
152 | /* | ||
153 | * USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV | ||
154 | * Where VRTC = 2.7 V | ||
155 | */ | ||
156 | #define WM8350_AUX_COEFF 1319 | ||
157 | |||
158 | #define WM8350_AUXADC_AUX1 0 | ||
159 | #define WM8350_AUXADC_AUX2 1 | ||
160 | #define WM8350_AUXADC_AUX3 2 | ||
161 | #define WM8350_AUXADC_AUX4 3 | ||
162 | #define WM8350_AUXADC_USB 4 | ||
163 | #define WM8350_AUXADC_LINE 5 | ||
164 | #define WM8350_AUXADC_BATT 6 | ||
165 | #define WM8350_AUXADC_TEMP 7 | ||
166 | |||
167 | #endif | ||
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h new file mode 100644 index 000000000000..6ebf97f2a475 --- /dev/null +++ b/include/linux/mfd/wm8350/core.h | |||
@@ -0,0 +1,631 @@ | |||
1 | /* | ||
2 | * core.h -- Core Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __LINUX_MFD_WM8350_CORE_H_ | ||
14 | #define __LINUX_MFD_WM8350_CORE_H_ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/mutex.h> | ||
18 | #include <linux/workqueue.h> | ||
19 | |||
20 | #include <linux/mfd/wm8350/audio.h> | ||
21 | #include <linux/mfd/wm8350/gpio.h> | ||
22 | #include <linux/mfd/wm8350/pmic.h> | ||
23 | #include <linux/mfd/wm8350/rtc.h> | ||
24 | #include <linux/mfd/wm8350/supply.h> | ||
25 | #include <linux/mfd/wm8350/wdt.h> | ||
26 | |||
27 | /* | ||
28 | * Register values. | ||
29 | */ | ||
30 | #define WM8350_RESET_ID 0x00 | ||
31 | #define WM8350_ID 0x01 | ||
32 | #define WM8350_SYSTEM_CONTROL_1 0x03 | ||
33 | #define WM8350_SYSTEM_CONTROL_2 0x04 | ||
34 | #define WM8350_SYSTEM_HIBERNATE 0x05 | ||
35 | #define WM8350_INTERFACE_CONTROL 0x06 | ||
36 | #define WM8350_POWER_MGMT_1 0x08 | ||
37 | #define WM8350_POWER_MGMT_2 0x09 | ||
38 | #define WM8350_POWER_MGMT_3 0x0A | ||
39 | #define WM8350_POWER_MGMT_4 0x0B | ||
40 | #define WM8350_POWER_MGMT_5 0x0C | ||
41 | #define WM8350_POWER_MGMT_6 0x0D | ||
42 | #define WM8350_POWER_MGMT_7 0x0E | ||
43 | |||
44 | #define WM8350_SYSTEM_INTERRUPTS 0x18 | ||
45 | #define WM8350_INT_STATUS_1 0x19 | ||
46 | #define WM8350_INT_STATUS_2 0x1A | ||
47 | #define WM8350_POWER_UP_INT_STATUS 0x1B | ||
48 | #define WM8350_UNDER_VOLTAGE_INT_STATUS 0x1C | ||
49 | #define WM8350_OVER_CURRENT_INT_STATUS 0x1D | ||
50 | #define WM8350_GPIO_INT_STATUS 0x1E | ||
51 | #define WM8350_COMPARATOR_INT_STATUS 0x1F | ||
52 | #define WM8350_SYSTEM_INTERRUPTS_MASK 0x20 | ||
53 | #define WM8350_INT_STATUS_1_MASK 0x21 | ||
54 | #define WM8350_INT_STATUS_2_MASK 0x22 | ||
55 | #define WM8350_POWER_UP_INT_STATUS_MASK 0x23 | ||
56 | #define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK 0x24 | ||
57 | #define WM8350_OVER_CURRENT_INT_STATUS_MASK 0x25 | ||
58 | #define WM8350_GPIO_INT_STATUS_MASK 0x26 | ||
59 | #define WM8350_COMPARATOR_INT_STATUS_MASK 0x27 | ||
60 | |||
61 | #define WM8350_MAX_REGISTER 0xFF | ||
62 | |||
63 | /* | ||
64 | * Field Definitions. | ||
65 | */ | ||
66 | |||
67 | /* | ||
68 | * R0 (0x00) - Reset/ID | ||
69 | */ | ||
70 | #define WM8350_SW_RESET_CHIP_ID_MASK 0xFFFF | ||
71 | |||
72 | /* | ||
73 | * R1 (0x01) - ID | ||
74 | */ | ||
75 | #define WM8350_CHIP_REV_MASK 0x7000 | ||
76 | #define WM8350_CONF_STS_MASK 0x0C00 | ||
77 | #define WM8350_CUST_ID_MASK 0x00FF | ||
78 | |||
79 | /* | ||
80 | * R3 (0x03) - System Control 1 | ||
81 | */ | ||
82 | #define WM8350_CHIP_ON 0x8000 | ||
83 | #define WM8350_POWERCYCLE 0x2000 | ||
84 | #define WM8350_VCC_FAULT_OV 0x1000 | ||
85 | #define WM8350_REG_RSTB_TIME_MASK 0x0C00 | ||
86 | #define WM8350_BG_SLEEP 0x0200 | ||
87 | #define WM8350_MEM_VALID 0x0020 | ||
88 | #define WM8350_CHIP_SET_UP 0x0010 | ||
89 | #define WM8350_ON_DEB_T 0x0008 | ||
90 | #define WM8350_ON_POL 0x0002 | ||
91 | #define WM8350_IRQ_POL 0x0001 | ||
92 | |||
93 | /* | ||
94 | * R4 (0x04) - System Control 2 | ||
95 | */ | ||
96 | #define WM8350_USB_SUSPEND_8MA 0x8000 | ||
97 | #define WM8350_USB_SUSPEND 0x4000 | ||
98 | #define WM8350_USB_MSTR 0x2000 | ||
99 | #define WM8350_USB_MSTR_SRC 0x1000 | ||
100 | #define WM8350_USB_500MA 0x0800 | ||
101 | #define WM8350_USB_NOLIM 0x0400 | ||
102 | |||
103 | /* | ||
104 | * R5 (0x05) - System Hibernate | ||
105 | */ | ||
106 | #define WM8350_HIBERNATE 0x8000 | ||
107 | #define WM8350_WDOG_HIB_MODE 0x0080 | ||
108 | #define WM8350_REG_HIB_STARTUP_SEQ 0x0040 | ||
109 | #define WM8350_REG_RESET_HIB_MODE 0x0020 | ||
110 | #define WM8350_RST_HIB_MODE 0x0010 | ||
111 | #define WM8350_IRQ_HIB_MODE 0x0008 | ||
112 | #define WM8350_MEMRST_HIB_MODE 0x0004 | ||
113 | #define WM8350_PCCOMP_HIB_MODE 0x0002 | ||
114 | #define WM8350_TEMPMON_HIB_MODE 0x0001 | ||
115 | |||
116 | /* | ||
117 | * R6 (0x06) - Interface Control | ||
118 | */ | ||
119 | #define WM8350_USE_DEV_PINS 0x8000 | ||
120 | #define WM8350_USE_DEV_PINS_MASK 0x8000 | ||
121 | #define WM8350_USE_DEV_PINS_SHIFT 15 | ||
122 | #define WM8350_DEV_ADDR_MASK 0x6000 | ||
123 | #define WM8350_DEV_ADDR_SHIFT 13 | ||
124 | #define WM8350_CONFIG_DONE 0x1000 | ||
125 | #define WM8350_CONFIG_DONE_MASK 0x1000 | ||
126 | #define WM8350_CONFIG_DONE_SHIFT 12 | ||
127 | #define WM8350_RECONFIG_AT_ON 0x0800 | ||
128 | #define WM8350_RECONFIG_AT_ON_MASK 0x0800 | ||
129 | #define WM8350_RECONFIG_AT_ON_SHIFT 11 | ||
130 | #define WM8350_AUTOINC 0x0200 | ||
131 | #define WM8350_AUTOINC_MASK 0x0200 | ||
132 | #define WM8350_AUTOINC_SHIFT 9 | ||
133 | #define WM8350_ARA 0x0100 | ||
134 | #define WM8350_ARA_MASK 0x0100 | ||
135 | #define WM8350_ARA_SHIFT 8 | ||
136 | #define WM8350_SPI_CFG 0x0008 | ||
137 | #define WM8350_SPI_CFG_MASK 0x0008 | ||
138 | #define WM8350_SPI_CFG_SHIFT 3 | ||
139 | #define WM8350_SPI_4WIRE 0x0004 | ||
140 | #define WM8350_SPI_4WIRE_MASK 0x0004 | ||
141 | #define WM8350_SPI_4WIRE_SHIFT 2 | ||
142 | #define WM8350_SPI_3WIRE 0x0002 | ||
143 | #define WM8350_SPI_3WIRE_MASK 0x0002 | ||
144 | #define WM8350_SPI_3WIRE_SHIFT 1 | ||
145 | |||
146 | /* Bit values for R06 (0x06) */ | ||
147 | #define WM8350_USE_DEV_PINS_PRIMARY 0 | ||
148 | #define WM8350_USE_DEV_PINS_DEV 1 | ||
149 | |||
150 | #define WM8350_DEV_ADDR_34 0 | ||
151 | #define WM8350_DEV_ADDR_36 1 | ||
152 | #define WM8350_DEV_ADDR_3C 2 | ||
153 | #define WM8350_DEV_ADDR_3E 3 | ||
154 | |||
155 | #define WM8350_CONFIG_DONE_OFF 0 | ||
156 | #define WM8350_CONFIG_DONE_DONE 1 | ||
157 | |||
158 | #define WM8350_RECONFIG_AT_ON_OFF 0 | ||
159 | #define WM8350_RECONFIG_AT_ON_ON 1 | ||
160 | |||
161 | #define WM8350_AUTOINC_OFF 0 | ||
162 | #define WM8350_AUTOINC_ON 1 | ||
163 | |||
164 | #define WM8350_ARA_OFF 0 | ||
165 | #define WM8350_ARA_ON 1 | ||
166 | |||
167 | #define WM8350_SPI_CFG_CMOS 0 | ||
168 | #define WM8350_SPI_CFG_OD 1 | ||
169 | |||
170 | #define WM8350_SPI_4WIRE_3WIRE 0 | ||
171 | #define WM8350_SPI_4WIRE_4WIRE 1 | ||
172 | |||
173 | #define WM8350_SPI_3WIRE_I2C 0 | ||
174 | #define WM8350_SPI_3WIRE_SPI 1 | ||
175 | |||
176 | /* | ||
177 | * R8 (0x08) - Power mgmt (1) | ||
178 | */ | ||
179 | #define WM8350_CODEC_ISEL_MASK 0xC000 | ||
180 | #define WM8350_VBUFEN 0x2000 | ||
181 | #define WM8350_OUTPUT_DRAIN_EN 0x0400 | ||
182 | #define WM8350_MIC_DET_ENA 0x0100 | ||
183 | #define WM8350_BIASEN 0x0020 | ||
184 | #define WM8350_MICBEN 0x0010 | ||
185 | #define WM8350_VMIDEN 0x0004 | ||
186 | #define WM8350_VMID_MASK 0x0003 | ||
187 | #define WM8350_VMID_SHIFT 0 | ||
188 | |||
189 | /* | ||
190 | * R9 (0x09) - Power mgmt (2) | ||
191 | */ | ||
192 | #define WM8350_IN3R_ENA 0x0800 | ||
193 | #define WM8350_IN3L_ENA 0x0400 | ||
194 | #define WM8350_INR_ENA 0x0200 | ||
195 | #define WM8350_INL_ENA 0x0100 | ||
196 | #define WM8350_MIXINR_ENA 0x0080 | ||
197 | #define WM8350_MIXINL_ENA 0x0040 | ||
198 | #define WM8350_OUT4_ENA 0x0020 | ||
199 | #define WM8350_OUT3_ENA 0x0010 | ||
200 | #define WM8350_MIXOUTR_ENA 0x0002 | ||
201 | #define WM8350_MIXOUTL_ENA 0x0001 | ||
202 | |||
203 | /* | ||
204 | * R10 (0x0A) - Power mgmt (3) | ||
205 | */ | ||
206 | #define WM8350_IN3R_TO_OUT2R 0x0080 | ||
207 | #define WM8350_OUT2R_ENA 0x0008 | ||
208 | #define WM8350_OUT2L_ENA 0x0004 | ||
209 | #define WM8350_OUT1R_ENA 0x0002 | ||
210 | #define WM8350_OUT1L_ENA 0x0001 | ||
211 | |||
212 | /* | ||
213 | * R11 (0x0B) - Power mgmt (4) | ||
214 | */ | ||
215 | #define WM8350_SYSCLK_ENA 0x4000 | ||
216 | #define WM8350_ADC_HPF_ENA 0x2000 | ||
217 | #define WM8350_FLL_ENA 0x0800 | ||
218 | #define WM8350_FLL_OSC_ENA 0x0400 | ||
219 | #define WM8350_TOCLK_ENA 0x0100 | ||
220 | #define WM8350_DACR_ENA 0x0020 | ||
221 | #define WM8350_DACL_ENA 0x0010 | ||
222 | #define WM8350_ADCR_ENA 0x0008 | ||
223 | #define WM8350_ADCL_ENA 0x0004 | ||
224 | |||
225 | /* | ||
226 | * R12 (0x0C) - Power mgmt (5) | ||
227 | */ | ||
228 | #define WM8350_CODEC_ENA 0x1000 | ||
229 | #define WM8350_RTC_TICK_ENA 0x0800 | ||
230 | #define WM8350_OSC32K_ENA 0x0400 | ||
231 | #define WM8350_CHG_ENA 0x0200 | ||
232 | #define WM8350_ACC_DET_ENA 0x0100 | ||
233 | #define WM8350_AUXADC_ENA 0x0080 | ||
234 | #define WM8350_DCMP4_ENA 0x0008 | ||
235 | #define WM8350_DCMP3_ENA 0x0004 | ||
236 | #define WM8350_DCMP2_ENA 0x0002 | ||
237 | #define WM8350_DCMP1_ENA 0x0001 | ||
238 | |||
239 | /* | ||
240 | * R13 (0x0D) - Power mgmt (6) | ||
241 | */ | ||
242 | #define WM8350_LS_ENA 0x8000 | ||
243 | #define WM8350_LDO4_ENA 0x0800 | ||
244 | #define WM8350_LDO3_ENA 0x0400 | ||
245 | #define WM8350_LDO2_ENA 0x0200 | ||
246 | #define WM8350_LDO1_ENA 0x0100 | ||
247 | #define WM8350_DC6_ENA 0x0020 | ||
248 | #define WM8350_DC5_ENA 0x0010 | ||
249 | #define WM8350_DC4_ENA 0x0008 | ||
250 | #define WM8350_DC3_ENA 0x0004 | ||
251 | #define WM8350_DC2_ENA 0x0002 | ||
252 | #define WM8350_DC1_ENA 0x0001 | ||
253 | |||
254 | /* | ||
255 | * R14 (0x0E) - Power mgmt (7) | ||
256 | */ | ||
257 | #define WM8350_CS2_ENA 0x0002 | ||
258 | #define WM8350_CS1_ENA 0x0001 | ||
259 | |||
260 | /* | ||
261 | * R24 (0x18) - System Interrupts | ||
262 | */ | ||
263 | #define WM8350_OC_INT 0x2000 | ||
264 | #define WM8350_UV_INT 0x1000 | ||
265 | #define WM8350_PUTO_INT 0x0800 | ||
266 | #define WM8350_CS_INT 0x0200 | ||
267 | #define WM8350_EXT_INT 0x0100 | ||
268 | #define WM8350_CODEC_INT 0x0080 | ||
269 | #define WM8350_GP_INT 0x0040 | ||
270 | #define WM8350_AUXADC_INT 0x0020 | ||
271 | #define WM8350_RTC_INT 0x0010 | ||
272 | #define WM8350_SYS_INT 0x0008 | ||
273 | #define WM8350_CHG_INT 0x0004 | ||
274 | #define WM8350_USB_INT 0x0002 | ||
275 | #define WM8350_WKUP_INT 0x0001 | ||
276 | |||
277 | /* | ||
278 | * R25 (0x19) - Interrupt Status 1 | ||
279 | */ | ||
280 | #define WM8350_CHG_BAT_HOT_EINT 0x8000 | ||
281 | #define WM8350_CHG_BAT_COLD_EINT 0x4000 | ||
282 | #define WM8350_CHG_BAT_FAIL_EINT 0x2000 | ||
283 | #define WM8350_CHG_TO_EINT 0x1000 | ||
284 | #define WM8350_CHG_END_EINT 0x0800 | ||
285 | #define WM8350_CHG_START_EINT 0x0400 | ||
286 | #define WM8350_CHG_FAST_RDY_EINT 0x0200 | ||
287 | #define WM8350_RTC_PER_EINT 0x0080 | ||
288 | #define WM8350_RTC_SEC_EINT 0x0040 | ||
289 | #define WM8350_RTC_ALM_EINT 0x0020 | ||
290 | #define WM8350_CHG_VBATT_LT_3P9_EINT 0x0004 | ||
291 | #define WM8350_CHG_VBATT_LT_3P1_EINT 0x0002 | ||
292 | #define WM8350_CHG_VBATT_LT_2P85_EINT 0x0001 | ||
293 | |||
294 | /* | ||
295 | * R26 (0x1A) - Interrupt Status 2 | ||
296 | */ | ||
297 | #define WM8350_CS1_EINT 0x2000 | ||
298 | #define WM8350_CS2_EINT 0x1000 | ||
299 | #define WM8350_USB_LIMIT_EINT 0x0400 | ||
300 | #define WM8350_AUXADC_DATARDY_EINT 0x0100 | ||
301 | #define WM8350_AUXADC_DCOMP4_EINT 0x0080 | ||
302 | #define WM8350_AUXADC_DCOMP3_EINT 0x0040 | ||
303 | #define WM8350_AUXADC_DCOMP2_EINT 0x0020 | ||
304 | #define WM8350_AUXADC_DCOMP1_EINT 0x0010 | ||
305 | #define WM8350_SYS_HYST_COMP_FAIL_EINT 0x0008 | ||
306 | #define WM8350_SYS_CHIP_GT115_EINT 0x0004 | ||
307 | #define WM8350_SYS_CHIP_GT140_EINT 0x0002 | ||
308 | #define WM8350_SYS_WDOG_TO_EINT 0x0001 | ||
309 | |||
310 | /* | ||
311 | * R27 (0x1B) - Power Up Interrupt Status | ||
312 | */ | ||
313 | #define WM8350_PUTO_LDO4_EINT 0x0800 | ||
314 | #define WM8350_PUTO_LDO3_EINT 0x0400 | ||
315 | #define WM8350_PUTO_LDO2_EINT 0x0200 | ||
316 | #define WM8350_PUTO_LDO1_EINT 0x0100 | ||
317 | #define WM8350_PUTO_DC6_EINT 0x0020 | ||
318 | #define WM8350_PUTO_DC5_EINT 0x0010 | ||
319 | #define WM8350_PUTO_DC4_EINT 0x0008 | ||
320 | #define WM8350_PUTO_DC3_EINT 0x0004 | ||
321 | #define WM8350_PUTO_DC2_EINT 0x0002 | ||
322 | #define WM8350_PUTO_DC1_EINT 0x0001 | ||
323 | |||
324 | /* | ||
325 | * R28 (0x1C) - Under Voltage Interrupt status | ||
326 | */ | ||
327 | #define WM8350_UV_LDO4_EINT 0x0800 | ||
328 | #define WM8350_UV_LDO3_EINT 0x0400 | ||
329 | #define WM8350_UV_LDO2_EINT 0x0200 | ||
330 | #define WM8350_UV_LDO1_EINT 0x0100 | ||
331 | #define WM8350_UV_DC6_EINT 0x0020 | ||
332 | #define WM8350_UV_DC5_EINT 0x0010 | ||
333 | #define WM8350_UV_DC4_EINT 0x0008 | ||
334 | #define WM8350_UV_DC3_EINT 0x0004 | ||
335 | #define WM8350_UV_DC2_EINT 0x0002 | ||
336 | #define WM8350_UV_DC1_EINT 0x0001 | ||
337 | |||
338 | /* | ||
339 | * R29 (0x1D) - Over Current Interrupt status | ||
340 | */ | ||
341 | #define WM8350_OC_LS_EINT 0x8000 | ||
342 | |||
343 | /* | ||
344 | * R30 (0x1E) - GPIO Interrupt Status | ||
345 | */ | ||
346 | #define WM8350_GP12_EINT 0x1000 | ||
347 | #define WM8350_GP11_EINT 0x0800 | ||
348 | #define WM8350_GP10_EINT 0x0400 | ||
349 | #define WM8350_GP9_EINT 0x0200 | ||
350 | #define WM8350_GP8_EINT 0x0100 | ||
351 | #define WM8350_GP7_EINT 0x0080 | ||
352 | #define WM8350_GP6_EINT 0x0040 | ||
353 | #define WM8350_GP5_EINT 0x0020 | ||
354 | #define WM8350_GP4_EINT 0x0010 | ||
355 | #define WM8350_GP3_EINT 0x0008 | ||
356 | #define WM8350_GP2_EINT 0x0004 | ||
357 | #define WM8350_GP1_EINT 0x0002 | ||
358 | #define WM8350_GP0_EINT 0x0001 | ||
359 | |||
360 | /* | ||
361 | * R31 (0x1F) - Comparator Interrupt Status | ||
362 | */ | ||
363 | #define WM8350_EXT_USB_FB_EINT 0x8000 | ||
364 | #define WM8350_EXT_WALL_FB_EINT 0x4000 | ||
365 | #define WM8350_EXT_BAT_FB_EINT 0x2000 | ||
366 | #define WM8350_CODEC_JCK_DET_L_EINT 0x0800 | ||
367 | #define WM8350_CODEC_JCK_DET_R_EINT 0x0400 | ||
368 | #define WM8350_CODEC_MICSCD_EINT 0x0200 | ||
369 | #define WM8350_CODEC_MICD_EINT 0x0100 | ||
370 | #define WM8350_WKUP_OFF_STATE_EINT 0x0040 | ||
371 | #define WM8350_WKUP_HIB_STATE_EINT 0x0020 | ||
372 | #define WM8350_WKUP_CONV_FAULT_EINT 0x0010 | ||
373 | #define WM8350_WKUP_WDOG_RST_EINT 0x0008 | ||
374 | #define WM8350_WKUP_GP_PWR_ON_EINT 0x0004 | ||
375 | #define WM8350_WKUP_ONKEY_EINT 0x0002 | ||
376 | #define WM8350_WKUP_GP_WAKEUP_EINT 0x0001 | ||
377 | |||
378 | /* | ||
379 | * R32 (0x20) - System Interrupts Mask | ||
380 | */ | ||
381 | #define WM8350_IM_OC_INT 0x2000 | ||
382 | #define WM8350_IM_UV_INT 0x1000 | ||
383 | #define WM8350_IM_PUTO_INT 0x0800 | ||
384 | #define WM8350_IM_SPARE_INT 0x0400 | ||
385 | #define WM8350_IM_CS_INT 0x0200 | ||
386 | #define WM8350_IM_EXT_INT 0x0100 | ||
387 | #define WM8350_IM_CODEC_INT 0x0080 | ||
388 | #define WM8350_IM_GP_INT 0x0040 | ||
389 | #define WM8350_IM_AUXADC_INT 0x0020 | ||
390 | #define WM8350_IM_RTC_INT 0x0010 | ||
391 | #define WM8350_IM_SYS_INT 0x0008 | ||
392 | #define WM8350_IM_CHG_INT 0x0004 | ||
393 | #define WM8350_IM_USB_INT 0x0002 | ||
394 | #define WM8350_IM_WKUP_INT 0x0001 | ||
395 | |||
396 | /* | ||
397 | * R33 (0x21) - Interrupt Status 1 Mask | ||
398 | */ | ||
399 | #define WM8350_IM_CHG_BAT_HOT_EINT 0x8000 | ||
400 | #define WM8350_IM_CHG_BAT_COLD_EINT 0x4000 | ||
401 | #define WM8350_IM_CHG_BAT_FAIL_EINT 0x2000 | ||
402 | #define WM8350_IM_CHG_TO_EINT 0x1000 | ||
403 | #define WM8350_IM_CHG_END_EINT 0x0800 | ||
404 | #define WM8350_IM_CHG_START_EINT 0x0400 | ||
405 | #define WM8350_IM_CHG_FAST_RDY_EINT 0x0200 | ||
406 | #define WM8350_IM_RTC_PER_EINT 0x0080 | ||
407 | #define WM8350_IM_RTC_SEC_EINT 0x0040 | ||
408 | #define WM8350_IM_RTC_ALM_EINT 0x0020 | ||
409 | #define WM8350_IM_CHG_VBATT_LT_3P9_EINT 0x0004 | ||
410 | #define WM8350_IM_CHG_VBATT_LT_3P1_EINT 0x0002 | ||
411 | #define WM8350_IM_CHG_VBATT_LT_2P85_EINT 0x0001 | ||
412 | |||
413 | /* | ||
414 | * R34 (0x22) - Interrupt Status 2 Mask | ||
415 | */ | ||
416 | #define WM8350_IM_SPARE2_EINT 0x8000 | ||
417 | #define WM8350_IM_SPARE1_EINT 0x4000 | ||
418 | #define WM8350_IM_CS1_EINT 0x2000 | ||
419 | #define WM8350_IM_CS2_EINT 0x1000 | ||
420 | #define WM8350_IM_USB_LIMIT_EINT 0x0400 | ||
421 | #define WM8350_IM_AUXADC_DATARDY_EINT 0x0100 | ||
422 | #define WM8350_IM_AUXADC_DCOMP4_EINT 0x0080 | ||
423 | #define WM8350_IM_AUXADC_DCOMP3_EINT 0x0040 | ||
424 | #define WM8350_IM_AUXADC_DCOMP2_EINT 0x0020 | ||
425 | #define WM8350_IM_AUXADC_DCOMP1_EINT 0x0010 | ||
426 | #define WM8350_IM_SYS_HYST_COMP_FAIL_EINT 0x0008 | ||
427 | #define WM8350_IM_SYS_CHIP_GT115_EINT 0x0004 | ||
428 | #define WM8350_IM_SYS_CHIP_GT140_EINT 0x0002 | ||
429 | #define WM8350_IM_SYS_WDOG_TO_EINT 0x0001 | ||
430 | |||
431 | /* | ||
432 | * R35 (0x23) - Power Up Interrupt Status Mask | ||
433 | */ | ||
434 | #define WM8350_IM_PUTO_LDO4_EINT 0x0800 | ||
435 | #define WM8350_IM_PUTO_LDO3_EINT 0x0400 | ||
436 | #define WM8350_IM_PUTO_LDO2_EINT 0x0200 | ||
437 | #define WM8350_IM_PUTO_LDO1_EINT 0x0100 | ||
438 | #define WM8350_IM_PUTO_DC6_EINT 0x0020 | ||
439 | #define WM8350_IM_PUTO_DC5_EINT 0x0010 | ||
440 | #define WM8350_IM_PUTO_DC4_EINT 0x0008 | ||
441 | #define WM8350_IM_PUTO_DC3_EINT 0x0004 | ||
442 | #define WM8350_IM_PUTO_DC2_EINT 0x0002 | ||
443 | #define WM8350_IM_PUTO_DC1_EINT 0x0001 | ||
444 | |||
445 | /* | ||
446 | * R36 (0x24) - Under Voltage Interrupt status Mask | ||
447 | */ | ||
448 | #define WM8350_IM_UV_LDO4_EINT 0x0800 | ||
449 | #define WM8350_IM_UV_LDO3_EINT 0x0400 | ||
450 | #define WM8350_IM_UV_LDO2_EINT 0x0200 | ||
451 | #define WM8350_IM_UV_LDO1_EINT 0x0100 | ||
452 | #define WM8350_IM_UV_DC6_EINT 0x0020 | ||
453 | #define WM8350_IM_UV_DC5_EINT 0x0010 | ||
454 | #define WM8350_IM_UV_DC4_EINT 0x0008 | ||
455 | #define WM8350_IM_UV_DC3_EINT 0x0004 | ||
456 | #define WM8350_IM_UV_DC2_EINT 0x0002 | ||
457 | #define WM8350_IM_UV_DC1_EINT 0x0001 | ||
458 | |||
459 | /* | ||
460 | * R37 (0x25) - Over Current Interrupt status Mask | ||
461 | */ | ||
462 | #define WM8350_IM_OC_LS_EINT 0x8000 | ||
463 | |||
464 | /* | ||
465 | * R38 (0x26) - GPIO Interrupt Status Mask | ||
466 | */ | ||
467 | #define WM8350_IM_GP12_EINT 0x1000 | ||
468 | #define WM8350_IM_GP11_EINT 0x0800 | ||
469 | #define WM8350_IM_GP10_EINT 0x0400 | ||
470 | #define WM8350_IM_GP9_EINT 0x0200 | ||
471 | #define WM8350_IM_GP8_EINT 0x0100 | ||
472 | #define WM8350_IM_GP7_EINT 0x0080 | ||
473 | #define WM8350_IM_GP6_EINT 0x0040 | ||
474 | #define WM8350_IM_GP5_EINT 0x0020 | ||
475 | #define WM8350_IM_GP4_EINT 0x0010 | ||
476 | #define WM8350_IM_GP3_EINT 0x0008 | ||
477 | #define WM8350_IM_GP2_EINT 0x0004 | ||
478 | #define WM8350_IM_GP1_EINT 0x0002 | ||
479 | #define WM8350_IM_GP0_EINT 0x0001 | ||
480 | |||
481 | /* | ||
482 | * R39 (0x27) - Comparator Interrupt Status Mask | ||
483 | */ | ||
484 | #define WM8350_IM_EXT_USB_FB_EINT 0x8000 | ||
485 | #define WM8350_IM_EXT_WALL_FB_EINT 0x4000 | ||
486 | #define WM8350_IM_EXT_BAT_FB_EINT 0x2000 | ||
487 | #define WM8350_IM_CODEC_JCK_DET_L_EINT 0x0800 | ||
488 | #define WM8350_IM_CODEC_JCK_DET_R_EINT 0x0400 | ||
489 | #define WM8350_IM_CODEC_MICSCD_EINT 0x0200 | ||
490 | #define WM8350_IM_CODEC_MICD_EINT 0x0100 | ||
491 | #define WM8350_IM_WKUP_OFF_STATE_EINT 0x0040 | ||
492 | #define WM8350_IM_WKUP_HIB_STATE_EINT 0x0020 | ||
493 | #define WM8350_IM_WKUP_CONV_FAULT_EINT 0x0010 | ||
494 | #define WM8350_IM_WKUP_WDOG_RST_EINT 0x0008 | ||
495 | #define WM8350_IM_WKUP_GP_PWR_ON_EINT 0x0004 | ||
496 | #define WM8350_IM_WKUP_ONKEY_EINT 0x0002 | ||
497 | #define WM8350_IM_WKUP_GP_WAKEUP_EINT 0x0001 | ||
498 | |||
499 | /* | ||
500 | * R220 (0xDC) - RAM BIST 1 | ||
501 | */ | ||
502 | #define WM8350_READ_STATUS 0x0800 | ||
503 | #define WM8350_TSTRAM_CLK 0x0100 | ||
504 | #define WM8350_TSTRAM_CLK_ENA 0x0080 | ||
505 | #define WM8350_STARTSEQ 0x0040 | ||
506 | #define WM8350_READ_SRC 0x0020 | ||
507 | #define WM8350_COUNT_DIR 0x0010 | ||
508 | #define WM8350_TSTRAM_MODE_MASK 0x000E | ||
509 | #define WM8350_TSTRAM_ENA 0x0001 | ||
510 | |||
511 | /* | ||
512 | * R225 (0xE1) - DCDC/LDO status | ||
513 | */ | ||
514 | #define WM8350_LS_STS 0x8000 | ||
515 | #define WM8350_LDO4_STS 0x0800 | ||
516 | #define WM8350_LDO3_STS 0x0400 | ||
517 | #define WM8350_LDO2_STS 0x0200 | ||
518 | #define WM8350_LDO1_STS 0x0100 | ||
519 | #define WM8350_DC6_STS 0x0020 | ||
520 | #define WM8350_DC5_STS 0x0010 | ||
521 | #define WM8350_DC4_STS 0x0008 | ||
522 | #define WM8350_DC3_STS 0x0004 | ||
523 | #define WM8350_DC2_STS 0x0002 | ||
524 | #define WM8350_DC1_STS 0x0001 | ||
525 | |||
526 | /* WM8350 wake up conditions */ | ||
527 | #define WM8350_IRQ_WKUP_OFF_STATE 43 | ||
528 | #define WM8350_IRQ_WKUP_HIB_STATE 44 | ||
529 | #define WM8350_IRQ_WKUP_CONV_FAULT 45 | ||
530 | #define WM8350_IRQ_WKUP_WDOG_RST 46 | ||
531 | #define WM8350_IRQ_WKUP_GP_PWR_ON 47 | ||
532 | #define WM8350_IRQ_WKUP_ONKEY 48 | ||
533 | #define WM8350_IRQ_WKUP_GP_WAKEUP 49 | ||
534 | |||
535 | /* wm8350 chip revisions */ | ||
536 | #define WM8350_REV_E 0x4 | ||
537 | #define WM8350_REV_F 0x5 | ||
538 | #define WM8350_REV_G 0x6 | ||
539 | |||
540 | #define WM8350_NUM_IRQ 63 | ||
541 | |||
542 | struct wm8350_reg_access { | ||
543 | u16 readable; /* Mask of readable bits */ | ||
544 | u16 writable; /* Mask of writable bits */ | ||
545 | u16 vol; /* Mask of volatile bits */ | ||
546 | }; | ||
547 | extern const struct wm8350_reg_access wm8350_reg_io_map[]; | ||
548 | extern const u16 wm8350_mode0_defaults[]; | ||
549 | extern const u16 wm8350_mode1_defaults[]; | ||
550 | extern const u16 wm8350_mode2_defaults[]; | ||
551 | extern const u16 wm8350_mode3_defaults[]; | ||
552 | |||
553 | struct wm8350; | ||
554 | |||
555 | struct wm8350_irq { | ||
556 | void (*handler) (struct wm8350 *, int, void *); | ||
557 | void *data; | ||
558 | }; | ||
559 | |||
560 | struct wm8350 { | ||
561 | int rev; /* chip revision */ | ||
562 | |||
563 | struct device *dev; | ||
564 | |||
565 | /* device IO */ | ||
566 | union { | ||
567 | struct i2c_client *i2c_client; | ||
568 | struct spi_device *spi_device; | ||
569 | }; | ||
570 | int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest); | ||
571 | int (*write_dev)(struct wm8350 *wm8350, char reg, int size, | ||
572 | void *src); | ||
573 | u16 *reg_cache; | ||
574 | |||
575 | /* Interrupt handling */ | ||
576 | struct work_struct irq_work; | ||
577 | struct mutex irq_mutex; /* IRQ table mutex */ | ||
578 | struct wm8350_irq irq[WM8350_NUM_IRQ]; | ||
579 | int chip_irq; | ||
580 | |||
581 | /* Client devices */ | ||
582 | struct wm8350_codec codec; | ||
583 | struct wm8350_gpio gpio; | ||
584 | struct wm8350_pmic pmic; | ||
585 | struct wm8350_power power; | ||
586 | struct wm8350_rtc rtc; | ||
587 | struct wm8350_wdt wdt; | ||
588 | }; | ||
589 | |||
590 | /** | ||
591 | * Data to be supplied by the platform to initialise the WM8350. | ||
592 | * | ||
593 | * @init: Function called during driver initialisation. Should be | ||
594 | * used by the platform to configure GPIO functions and similar. | ||
595 | */ | ||
596 | struct wm8350_platform_data { | ||
597 | int (*init)(struct wm8350 *wm8350); | ||
598 | }; | ||
599 | |||
600 | |||
601 | /* | ||
602 | * WM8350 device initialisation and exit. | ||
603 | */ | ||
604 | int wm8350_device_init(struct wm8350 *wm8350, int irq, | ||
605 | struct wm8350_platform_data *pdata); | ||
606 | void wm8350_device_exit(struct wm8350 *wm8350); | ||
607 | |||
608 | /* | ||
609 | * WM8350 device IO | ||
610 | */ | ||
611 | int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask); | ||
612 | int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask); | ||
613 | u16 wm8350_reg_read(struct wm8350 *wm8350, int reg); | ||
614 | int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val); | ||
615 | int wm8350_reg_lock(struct wm8350 *wm8350); | ||
616 | int wm8350_reg_unlock(struct wm8350 *wm8350); | ||
617 | int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest); | ||
618 | int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src); | ||
619 | |||
620 | /* | ||
621 | * WM8350 internal interrupts | ||
622 | */ | ||
623 | int wm8350_register_irq(struct wm8350 *wm8350, int irq, | ||
624 | void (*handler) (struct wm8350 *, int, void *), | ||
625 | void *data); | ||
626 | int wm8350_free_irq(struct wm8350 *wm8350, int irq); | ||
627 | int wm8350_mask_irq(struct wm8350 *wm8350, int irq); | ||
628 | int wm8350_unmask_irq(struct wm8350 *wm8350, int irq); | ||
629 | |||
630 | |||
631 | #endif | ||
diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h new file mode 100644 index 000000000000..ed91e8f5d298 --- /dev/null +++ b/include/linux/mfd/wm8350/gpio.h | |||
@@ -0,0 +1,342 @@ | |||
1 | /* | ||
2 | * gpio.h -- GPIO Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __LINUX_MFD_WM8350_GPIO_H_ | ||
14 | #define __LINUX_MFD_WM8350_GPIO_H_ | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | /* | ||
19 | * GPIO Registers. | ||
20 | */ | ||
21 | #define WM8350_GPIO_DEBOUNCE 0x80 | ||
22 | #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81 | ||
23 | #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82 | ||
24 | #define WM8350_GPIO_INT_MODE 0x83 | ||
25 | #define WM8350_GPIO_CONTROL 0x85 | ||
26 | #define WM8350_GPIO_CONFIGURATION_I_O 0x86 | ||
27 | #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87 | ||
28 | #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C | ||
29 | #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D | ||
30 | #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E | ||
31 | #define WM8350_GPIO_FUNCTION_SELECT_4 0x8F | ||
32 | |||
33 | /* | ||
34 | * GPIO Functions | ||
35 | */ | ||
36 | #define WM8350_GPIO0_GPIO_IN 0x0 | ||
37 | #define WM8350_GPIO0_GPIO_OUT 0x0 | ||
38 | #define WM8350_GPIO0_PWR_ON_IN 0x1 | ||
39 | #define WM8350_GPIO0_PWR_ON_OUT 0x1 | ||
40 | #define WM8350_GPIO0_LDO_EN_IN 0x2 | ||
41 | #define WM8350_GPIO0_VRTC_OUT 0x2 | ||
42 | #define WM8350_GPIO0_LPWR1_IN 0x3 | ||
43 | #define WM8350_GPIO0_POR_B_OUT 0x3 | ||
44 | |||
45 | #define WM8350_GPIO1_GPIO_IN 0x0 | ||
46 | #define WM8350_GPIO1_GPIO_OUT 0x0 | ||
47 | #define WM8350_GPIO1_PWR_ON_IN 0x1 | ||
48 | #define WM8350_GPIO1_DO_CONF_OUT 0x1 | ||
49 | #define WM8350_GPIO1_LDO_EN_IN 0x2 | ||
50 | #define WM8350_GPIO1_RESET_OUT 0x2 | ||
51 | #define WM8350_GPIO1_LPWR2_IN 0x3 | ||
52 | #define WM8350_GPIO1_MEMRST_OUT 0x3 | ||
53 | |||
54 | #define WM8350_GPIO2_GPIO_IN 0x0 | ||
55 | #define WM8350_GPIO2_GPIO_OUT 0x0 | ||
56 | #define WM8350_GPIO2_PWR_ON_IN 0x1 | ||
57 | #define WM8350_GPIO2_PWR_ON_OUT 0x1 | ||
58 | #define WM8350_GPIO2_WAKE_UP_IN 0x2 | ||
59 | #define WM8350_GPIO2_VRTC_OUT 0x2 | ||
60 | #define WM8350_GPIO2_32KHZ_IN 0x3 | ||
61 | #define WM8350_GPIO2_32KHZ_OUT 0x3 | ||
62 | |||
63 | #define WM8350_GPIO3_GPIO_IN 0x0 | ||
64 | #define WM8350_GPIO3_GPIO_OUT 0x0 | ||
65 | #define WM8350_GPIO3_PWR_ON_IN 0x1 | ||
66 | #define WM8350_GPIO3_P_CLK_OUT 0x1 | ||
67 | #define WM8350_GPIO3_LDO_EN_IN 0x2 | ||
68 | #define WM8350_GPIO3_VRTC_OUT 0x2 | ||
69 | #define WM8350_GPIO3_PWR_OFF_IN 0x3 | ||
70 | #define WM8350_GPIO3_32KHZ_OUT 0x3 | ||
71 | |||
72 | #define WM8350_GPIO4_GPIO_IN 0x0 | ||
73 | #define WM8350_GPIO4_GPIO_OUT 0x0 | ||
74 | #define WM8350_GPIO4_MR_IN 0x1 | ||
75 | #define WM8350_GPIO4_MEM_RST_OUT 0x1 | ||
76 | #define WM8350_GPIO4_FLASH_IN 0x2 | ||
77 | #define WM8350_GPIO4_ADA_OUT 0x2 | ||
78 | #define WM8350_GPIO4_HIBERNATE_IN 0x3 | ||
79 | #define WM8350_GPIO4_FLASH_OUT 0x3 | ||
80 | #define WM8350_GPIO4_MICDET_OUT 0x4 | ||
81 | #define WM8350_GPIO4_MICSHT_OUT 0x5 | ||
82 | |||
83 | #define WM8350_GPIO5_GPIO_IN 0x0 | ||
84 | #define WM8350_GPIO5_GPIO_OUT 0x0 | ||
85 | #define WM8350_GPIO5_LPWR1_IN 0x1 | ||
86 | #define WM8350_GPIO5_P_CLK_OUT 0x1 | ||
87 | #define WM8350_GPIO5_ADCLRCLK_IN 0x2 | ||
88 | #define WM8350_GPIO5_ADCLRCLK_OUT 0x2 | ||
89 | #define WM8350_GPIO5_HIBERNATE_IN 0x3 | ||
90 | #define WM8350_GPIO5_32KHZ_OUT 0x3 | ||
91 | #define WM8350_GPIO5_MICDET_OUT 0x4 | ||
92 | #define WM8350_GPIO5_MICSHT_OUT 0x5 | ||
93 | #define WM8350_GPIO5_ADA_OUT 0x6 | ||
94 | #define WM8350_GPIO5_OPCLK_OUT 0x7 | ||
95 | |||
96 | #define WM8350_GPIO6_GPIO_IN 0x0 | ||
97 | #define WM8350_GPIO6_GPIO_OUT 0x0 | ||
98 | #define WM8350_GPIO6_LPWR2_IN 0x1 | ||
99 | #define WM8350_GPIO6_MEMRST_OUT 0x1 | ||
100 | #define WM8350_GPIO6_FLASH_IN 0x2 | ||
101 | #define WM8350_GPIO6_ADA_OUT 0x2 | ||
102 | #define WM8350_GPIO6_HIBERNATE_IN 0x3 | ||
103 | #define WM8350_GPIO6_RTC_OUT 0x3 | ||
104 | #define WM8350_GPIO6_MICDET_OUT 0x4 | ||
105 | #define WM8350_GPIO6_MICSHT_OUT 0x5 | ||
106 | #define WM8350_GPIO6_ADCLRCLKB_OUT 0x6 | ||
107 | #define WM8350_GPIO6_SDOUT_OUT 0x7 | ||
108 | |||
109 | #define WM8350_GPIO7_GPIO_IN 0x0 | ||
110 | #define WM8350_GPIO7_GPIO_OUT 0x0 | ||
111 | #define WM8350_GPIO7_LPWR3_IN 0x1 | ||
112 | #define WM8350_GPIO7_P_CLK_OUT 0x1 | ||
113 | #define WM8350_GPIO7_MASK_IN 0x2 | ||
114 | #define WM8350_GPIO7_VCC_FAULT_OUT 0x2 | ||
115 | #define WM8350_GPIO7_HIBERNATE_IN 0x3 | ||
116 | #define WM8350_GPIO7_BATT_FAULT_OUT 0x3 | ||
117 | #define WM8350_GPIO7_MICDET_OUT 0x4 | ||
118 | #define WM8350_GPIO7_MICSHT_OUT 0x5 | ||
119 | #define WM8350_GPIO7_ADA_OUT 0x6 | ||
120 | #define WM8350_GPIO7_CSB_IN 0x7 | ||
121 | |||
122 | #define WM8350_GPIO8_GPIO_IN 0x0 | ||
123 | #define WM8350_GPIO8_GPIO_OUT 0x0 | ||
124 | #define WM8350_GPIO8_MR_IN 0x1 | ||
125 | #define WM8350_GPIO8_VCC_FAULT_OUT 0x1 | ||
126 | #define WM8350_GPIO8_ADCBCLK_IN 0x2 | ||
127 | #define WM8350_GPIO8_ADCBCLK_OUT 0x2 | ||
128 | #define WM8350_GPIO8_PWR_OFF_IN 0x3 | ||
129 | #define WM8350_GPIO8_BATT_FAULT_OUT 0x3 | ||
130 | #define WM8350_GPIO8_ALTSCL_IN 0xf | ||
131 | |||
132 | #define WM8350_GPIO9_GPIO_IN 0x0 | ||
133 | #define WM8350_GPIO9_GPIO_OUT 0x0 | ||
134 | #define WM8350_GPIO9_HEARTBEAT_IN 0x1 | ||
135 | #define WM8350_GPIO9_VCC_FAULT_OUT 0x1 | ||
136 | #define WM8350_GPIO9_MASK_IN 0x2 | ||
137 | #define WM8350_GPIO9_LINE_GT_BATT_OUT 0x2 | ||
138 | #define WM8350_GPIO9_PWR_OFF_IN 0x3 | ||
139 | #define WM8350_GPIO9_BATT_FAULT_OUT 0x3 | ||
140 | #define WM8350_GPIO9_ALTSDA_OUT 0xf | ||
141 | |||
142 | #define WM8350_GPIO10_GPIO_IN 0x0 | ||
143 | #define WM8350_GPIO10_GPIO_OUT 0x0 | ||
144 | #define WM8350_GPIO10_ISINKC_OUT 0x1 | ||
145 | #define WM8350_GPIO10_PWR_OFF_IN 0x2 | ||
146 | #define WM8350_GPIO10_LINE_GT_BATT_OUT 0x2 | ||
147 | #define WM8350_GPIO10_CHD_IND_IN 0x3 | ||
148 | |||
149 | #define WM8350_GPIO11_GPIO_IN 0x0 | ||
150 | #define WM8350_GPIO11_GPIO_OUT 0x0 | ||
151 | #define WM8350_GPIO11_ISINKD_OUT 0x1 | ||
152 | #define WM8350_GPIO11_WAKEUP_IN 0x2 | ||
153 | #define WM8350_GPIO11_LINE_GT_BATT_OUT 0x2 | ||
154 | #define WM8350_GPIO11_CHD_IND_IN 0x3 | ||
155 | |||
156 | #define WM8350_GPIO12_GPIO_IN 0x0 | ||
157 | #define WM8350_GPIO12_GPIO_OUT 0x0 | ||
158 | #define WM8350_GPIO12_ISINKE_OUT 0x1 | ||
159 | #define WM8350_GPIO12_LINE_GT_BATT_OUT 0x2 | ||
160 | #define WM8350_GPIO12_LINE_EN_OUT 0x3 | ||
161 | #define WM8350_GPIO12_32KHZ_OUT 0x4 | ||
162 | |||
163 | #define WM8350_GPIO_DIR_IN 0 | ||
164 | #define WM8350_GPIO_DIR_OUT 1 | ||
165 | #define WM8350_GPIO_ACTIVE_LOW 0 | ||
166 | #define WM8350_GPIO_ACTIVE_HIGH 1 | ||
167 | #define WM8350_GPIO_PULL_NONE 0 | ||
168 | #define WM8350_GPIO_PULL_UP 1 | ||
169 | #define WM8350_GPIO_PULL_DOWN 2 | ||
170 | #define WM8350_GPIO_INVERT_OFF 0 | ||
171 | #define WM8350_GPIO_INVERT_ON 1 | ||
172 | #define WM8350_GPIO_DEBOUNCE_OFF 0 | ||
173 | #define WM8350_GPIO_DEBOUNCE_ON 1 | ||
174 | |||
175 | /* | ||
176 | * R128 (0x80) - GPIO Debounce | ||
177 | */ | ||
178 | #define WM8350_GP12_DB 0x1000 | ||
179 | #define WM8350_GP11_DB 0x0800 | ||
180 | #define WM8350_GP10_DB 0x0400 | ||
181 | #define WM8350_GP9_DB 0x0200 | ||
182 | #define WM8350_GP8_DB 0x0100 | ||
183 | #define WM8350_GP7_DB 0x0080 | ||
184 | #define WM8350_GP6_DB 0x0040 | ||
185 | #define WM8350_GP5_DB 0x0020 | ||
186 | #define WM8350_GP4_DB 0x0010 | ||
187 | #define WM8350_GP3_DB 0x0008 | ||
188 | #define WM8350_GP2_DB 0x0004 | ||
189 | #define WM8350_GP1_DB 0x0002 | ||
190 | #define WM8350_GP0_DB 0x0001 | ||
191 | |||
192 | /* | ||
193 | * R129 (0x81) - GPIO Pin pull up Control | ||
194 | */ | ||
195 | #define WM8350_GP12_PU 0x1000 | ||
196 | #define WM8350_GP11_PU 0x0800 | ||
197 | #define WM8350_GP10_PU 0x0400 | ||
198 | #define WM8350_GP9_PU 0x0200 | ||
199 | #define WM8350_GP8_PU 0x0100 | ||
200 | #define WM8350_GP7_PU 0x0080 | ||
201 | #define WM8350_GP6_PU 0x0040 | ||
202 | #define WM8350_GP5_PU 0x0020 | ||
203 | #define WM8350_GP4_PU 0x0010 | ||
204 | #define WM8350_GP3_PU 0x0008 | ||
205 | #define WM8350_GP2_PU 0x0004 | ||
206 | #define WM8350_GP1_PU 0x0002 | ||
207 | #define WM8350_GP0_PU 0x0001 | ||
208 | |||
209 | /* | ||
210 | * R130 (0x82) - GPIO Pull down Control | ||
211 | */ | ||
212 | #define WM8350_GP12_PD 0x1000 | ||
213 | #define WM8350_GP11_PD 0x0800 | ||
214 | #define WM8350_GP10_PD 0x0400 | ||
215 | #define WM8350_GP9_PD 0x0200 | ||
216 | #define WM8350_GP8_PD 0x0100 | ||
217 | #define WM8350_GP7_PD 0x0080 | ||
218 | #define WM8350_GP6_PD 0x0040 | ||
219 | #define WM8350_GP5_PD 0x0020 | ||
220 | #define WM8350_GP4_PD 0x0010 | ||
221 | #define WM8350_GP3_PD 0x0008 | ||
222 | #define WM8350_GP2_PD 0x0004 | ||
223 | #define WM8350_GP1_PD 0x0002 | ||
224 | #define WM8350_GP0_PD 0x0001 | ||
225 | |||
226 | /* | ||
227 | * R131 (0x83) - GPIO Interrupt Mode | ||
228 | */ | ||
229 | #define WM8350_GP12_INTMODE 0x1000 | ||
230 | #define WM8350_GP11_INTMODE 0x0800 | ||
231 | #define WM8350_GP10_INTMODE 0x0400 | ||
232 | #define WM8350_GP9_INTMODE 0x0200 | ||
233 | #define WM8350_GP8_INTMODE 0x0100 | ||
234 | #define WM8350_GP7_INTMODE 0x0080 | ||
235 | #define WM8350_GP6_INTMODE 0x0040 | ||
236 | #define WM8350_GP5_INTMODE 0x0020 | ||
237 | #define WM8350_GP4_INTMODE 0x0010 | ||
238 | #define WM8350_GP3_INTMODE 0x0008 | ||
239 | #define WM8350_GP2_INTMODE 0x0004 | ||
240 | #define WM8350_GP1_INTMODE 0x0002 | ||
241 | #define WM8350_GP0_INTMODE 0x0001 | ||
242 | |||
243 | /* | ||
244 | * R133 (0x85) - GPIO Control | ||
245 | */ | ||
246 | #define WM8350_GP_DBTIME_MASK 0x00C0 | ||
247 | |||
248 | /* | ||
249 | * R134 (0x86) - GPIO Configuration (i/o) | ||
250 | */ | ||
251 | #define WM8350_GP12_DIR 0x1000 | ||
252 | #define WM8350_GP11_DIR 0x0800 | ||
253 | #define WM8350_GP10_DIR 0x0400 | ||
254 | #define WM8350_GP9_DIR 0x0200 | ||
255 | #define WM8350_GP8_DIR 0x0100 | ||
256 | #define WM8350_GP7_DIR 0x0080 | ||
257 | #define WM8350_GP6_DIR 0x0040 | ||
258 | #define WM8350_GP5_DIR 0x0020 | ||
259 | #define WM8350_GP4_DIR 0x0010 | ||
260 | #define WM8350_GP3_DIR 0x0008 | ||
261 | #define WM8350_GP2_DIR 0x0004 | ||
262 | #define WM8350_GP1_DIR 0x0002 | ||
263 | #define WM8350_GP0_DIR 0x0001 | ||
264 | |||
265 | /* | ||
266 | * R135 (0x87) - GPIO Pin Polarity / Type | ||
267 | */ | ||
268 | #define WM8350_GP12_CFG 0x1000 | ||
269 | #define WM8350_GP11_CFG 0x0800 | ||
270 | #define WM8350_GP10_CFG 0x0400 | ||
271 | #define WM8350_GP9_CFG 0x0200 | ||
272 | #define WM8350_GP8_CFG 0x0100 | ||
273 | #define WM8350_GP7_CFG 0x0080 | ||
274 | #define WM8350_GP6_CFG 0x0040 | ||
275 | #define WM8350_GP5_CFG 0x0020 | ||
276 | #define WM8350_GP4_CFG 0x0010 | ||
277 | #define WM8350_GP3_CFG 0x0008 | ||
278 | #define WM8350_GP2_CFG 0x0004 | ||
279 | #define WM8350_GP1_CFG 0x0002 | ||
280 | #define WM8350_GP0_CFG 0x0001 | ||
281 | |||
282 | /* | ||
283 | * R140 (0x8C) - GPIO Function Select 1 | ||
284 | */ | ||
285 | #define WM8350_GP3_FN_MASK 0xF000 | ||
286 | #define WM8350_GP2_FN_MASK 0x0F00 | ||
287 | #define WM8350_GP1_FN_MASK 0x00F0 | ||
288 | #define WM8350_GP0_FN_MASK 0x000F | ||
289 | |||
290 | /* | ||
291 | * R141 (0x8D) - GPIO Function Select 2 | ||
292 | */ | ||
293 | #define WM8350_GP7_FN_MASK 0xF000 | ||
294 | #define WM8350_GP6_FN_MASK 0x0F00 | ||
295 | #define WM8350_GP5_FN_MASK 0x00F0 | ||
296 | #define WM8350_GP4_FN_MASK 0x000F | ||
297 | |||
298 | /* | ||
299 | * R142 (0x8E) - GPIO Function Select 3 | ||
300 | */ | ||
301 | #define WM8350_GP11_FN_MASK 0xF000 | ||
302 | #define WM8350_GP10_FN_MASK 0x0F00 | ||
303 | #define WM8350_GP9_FN_MASK 0x00F0 | ||
304 | #define WM8350_GP8_FN_MASK 0x000F | ||
305 | |||
306 | /* | ||
307 | * R143 (0x8F) - GPIO Function Select 4 | ||
308 | */ | ||
309 | #define WM8350_GP12_FN_MASK 0x000F | ||
310 | |||
311 | /* | ||
312 | * R230 (0xE6) - GPIO Pin Status | ||
313 | */ | ||
314 | #define WM8350_GP12_LVL 0x1000 | ||
315 | #define WM8350_GP11_LVL 0x0800 | ||
316 | #define WM8350_GP10_LVL 0x0400 | ||
317 | #define WM8350_GP9_LVL 0x0200 | ||
318 | #define WM8350_GP8_LVL 0x0100 | ||
319 | #define WM8350_GP7_LVL 0x0080 | ||
320 | #define WM8350_GP6_LVL 0x0040 | ||
321 | #define WM8350_GP5_LVL 0x0020 | ||
322 | #define WM8350_GP4_LVL 0x0010 | ||
323 | #define WM8350_GP3_LVL 0x0008 | ||
324 | #define WM8350_GP2_LVL 0x0004 | ||
325 | #define WM8350_GP1_LVL 0x0002 | ||
326 | #define WM8350_GP0_LVL 0x0001 | ||
327 | |||
328 | struct wm8350; | ||
329 | |||
330 | int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func, | ||
331 | int pol, int pull, int invert, int debounce); | ||
332 | |||
333 | struct wm8350_gpio { | ||
334 | struct platform_device *pdev; | ||
335 | }; | ||
336 | |||
337 | /* | ||
338 | * GPIO Interrupts | ||
339 | */ | ||
340 | #define WM8350_IRQ_GPIO(x) (50 + x) | ||
341 | |||
342 | #endif | ||
diff --git a/include/linux/mfd/wm8350/pmic.h b/include/linux/mfd/wm8350/pmic.h new file mode 100644 index 000000000000..69b69e07f62f --- /dev/null +++ b/include/linux/mfd/wm8350/pmic.h | |||
@@ -0,0 +1,741 @@ | |||
1 | /* | ||
2 | * pmic.h -- Power Managment Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __LINUX_MFD_WM8350_PMIC_H | ||
14 | #define __LINUX_MFD_WM8350_PMIC_H | ||
15 | |||
16 | /* | ||
17 | * Register values. | ||
18 | */ | ||
19 | |||
20 | #define WM8350_CURRENT_SINK_DRIVER_A 0xAC | ||
21 | #define WM8350_CSA_FLASH_CONTROL 0xAD | ||
22 | #define WM8350_CURRENT_SINK_DRIVER_B 0xAE | ||
23 | #define WM8350_CSB_FLASH_CONTROL 0xAF | ||
24 | #define WM8350_DCDC_LDO_REQUESTED 0xB0 | ||
25 | #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1 | ||
26 | #define WM8350_DCDC_SLEEP_OPTIONS 0xB2 | ||
27 | #define WM8350_POWER_CHECK_COMPARATOR 0xB3 | ||
28 | #define WM8350_DCDC1_CONTROL 0xB4 | ||
29 | #define WM8350_DCDC1_TIMEOUTS 0xB5 | ||
30 | #define WM8350_DCDC1_LOW_POWER 0xB6 | ||
31 | #define WM8350_DCDC2_CONTROL 0xB7 | ||
32 | #define WM8350_DCDC2_TIMEOUTS 0xB8 | ||
33 | #define WM8350_DCDC3_CONTROL 0xBA | ||
34 | #define WM8350_DCDC3_TIMEOUTS 0xBB | ||
35 | #define WM8350_DCDC3_LOW_POWER 0xBC | ||
36 | #define WM8350_DCDC4_CONTROL 0xBD | ||
37 | #define WM8350_DCDC4_TIMEOUTS 0xBE | ||
38 | #define WM8350_DCDC4_LOW_POWER 0xBF | ||
39 | #define WM8350_DCDC5_CONTROL 0xC0 | ||
40 | #define WM8350_DCDC5_TIMEOUTS 0xC1 | ||
41 | #define WM8350_DCDC6_CONTROL 0xC3 | ||
42 | #define WM8350_DCDC6_TIMEOUTS 0xC4 | ||
43 | #define WM8350_DCDC6_LOW_POWER 0xC5 | ||
44 | #define WM8350_LIMIT_SWITCH_CONTROL 0xC7 | ||
45 | #define WM8350_LDO1_CONTROL 0xC8 | ||
46 | #define WM8350_LDO1_TIMEOUTS 0xC9 | ||
47 | #define WM8350_LDO1_LOW_POWER 0xCA | ||
48 | #define WM8350_LDO2_CONTROL 0xCB | ||
49 | #define WM8350_LDO2_TIMEOUTS 0xCC | ||
50 | #define WM8350_LDO2_LOW_POWER 0xCD | ||
51 | #define WM8350_LDO3_CONTROL 0xCE | ||
52 | #define WM8350_LDO3_TIMEOUTS 0xCF | ||
53 | #define WM8350_LDO3_LOW_POWER 0xD0 | ||
54 | #define WM8350_LDO4_CONTROL 0xD1 | ||
55 | #define WM8350_LDO4_TIMEOUTS 0xD2 | ||
56 | #define WM8350_LDO4_LOW_POWER 0xD3 | ||
57 | #define WM8350_VCC_FAULT_MASKS 0xD7 | ||
58 | #define WM8350_MAIN_BANDGAP_CONTROL 0xD8 | ||
59 | #define WM8350_OSC_CONTROL 0xD9 | ||
60 | #define WM8350_RTC_TICK_CONTROL 0xDA | ||
61 | #define WM8350_SECURITY 0xDB | ||
62 | #define WM8350_RAM_BIST_1 0xDC | ||
63 | #define WM8350_DCDC_LDO_STATUS 0xE1 | ||
64 | #define WM8350_GPIO_PIN_STATUS 0xE6 | ||
65 | |||
66 | #define WM8350_DCDC1_FORCE_PWM 0xF8 | ||
67 | #define WM8350_DCDC3_FORCE_PWM 0xFA | ||
68 | #define WM8350_DCDC4_FORCE_PWM 0xFB | ||
69 | #define WM8350_DCDC6_FORCE_PWM 0xFD | ||
70 | |||
71 | /* | ||
72 | * R172 (0xAC) - Current Sink Driver A | ||
73 | */ | ||
74 | #define WM8350_CS1_HIB_MODE 0x1000 | ||
75 | #define WM8350_CS1_HIB_MODE_MASK 0x1000 | ||
76 | #define WM8350_CS1_HIB_MODE_SHIFT 12 | ||
77 | #define WM8350_CS1_ISEL_MASK 0x003F | ||
78 | #define WM8350_CS1_ISEL_SHIFT 0 | ||
79 | |||
80 | /* Bit values for R172 (0xAC) */ | ||
81 | #define WM8350_CS1_HIB_MODE_DISABLE 0 | ||
82 | #define WM8350_CS1_HIB_MODE_LEAVE 1 | ||
83 | |||
84 | #define WM8350_CS1_ISEL_220M 0x3F | ||
85 | |||
86 | /* | ||
87 | * R173 (0xAD) - CSA Flash control | ||
88 | */ | ||
89 | #define WM8350_CS1_FLASH_MODE 0x8000 | ||
90 | #define WM8350_CS1_TRIGSRC 0x4000 | ||
91 | #define WM8350_CS1_DRIVE 0x2000 | ||
92 | #define WM8350_CS1_FLASH_DUR_MASK 0x0300 | ||
93 | #define WM8350_CS1_OFF_RAMP_MASK 0x0030 | ||
94 | #define WM8350_CS1_ON_RAMP_MASK 0x0003 | ||
95 | |||
96 | /* | ||
97 | * R174 (0xAE) - Current Sink Driver B | ||
98 | */ | ||
99 | #define WM8350_CS2_HIB_MODE 0x1000 | ||
100 | #define WM8350_CS2_ISEL_MASK 0x003F | ||
101 | |||
102 | /* | ||
103 | * R175 (0xAF) - CSB Flash control | ||
104 | */ | ||
105 | #define WM8350_CS2_FLASH_MODE 0x8000 | ||
106 | #define WM8350_CS2_TRIGSRC 0x4000 | ||
107 | #define WM8350_CS2_DRIVE 0x2000 | ||
108 | #define WM8350_CS2_FLASH_DUR_MASK 0x0300 | ||
109 | #define WM8350_CS2_OFF_RAMP_MASK 0x0030 | ||
110 | #define WM8350_CS2_ON_RAMP_MASK 0x0003 | ||
111 | |||
112 | /* | ||
113 | * R176 (0xB0) - DCDC/LDO requested | ||
114 | */ | ||
115 | #define WM8350_LS_ENA 0x8000 | ||
116 | #define WM8350_LDO4_ENA 0x0800 | ||
117 | #define WM8350_LDO3_ENA 0x0400 | ||
118 | #define WM8350_LDO2_ENA 0x0200 | ||
119 | #define WM8350_LDO1_ENA 0x0100 | ||
120 | #define WM8350_DC6_ENA 0x0020 | ||
121 | #define WM8350_DC5_ENA 0x0010 | ||
122 | #define WM8350_DC4_ENA 0x0008 | ||
123 | #define WM8350_DC3_ENA 0x0004 | ||
124 | #define WM8350_DC2_ENA 0x0002 | ||
125 | #define WM8350_DC1_ENA 0x0001 | ||
126 | |||
127 | /* | ||
128 | * R177 (0xB1) - DCDC Active options | ||
129 | */ | ||
130 | #define WM8350_PUTO_MASK 0x3000 | ||
131 | #define WM8350_PWRUP_DELAY_MASK 0x0300 | ||
132 | #define WM8350_DC6_ACTIVE 0x0020 | ||
133 | #define WM8350_DC4_ACTIVE 0x0008 | ||
134 | #define WM8350_DC3_ACTIVE 0x0004 | ||
135 | #define WM8350_DC1_ACTIVE 0x0001 | ||
136 | |||
137 | /* | ||
138 | * R178 (0xB2) - DCDC Sleep options | ||
139 | */ | ||
140 | #define WM8350_DC6_SLEEP 0x0020 | ||
141 | #define WM8350_DC4_SLEEP 0x0008 | ||
142 | #define WM8350_DC3_SLEEP 0x0004 | ||
143 | #define WM8350_DC1_SLEEP 0x0001 | ||
144 | |||
145 | /* | ||
146 | * R179 (0xB3) - Power-check comparator | ||
147 | */ | ||
148 | #define WM8350_PCCMP_ERRACT 0x4000 | ||
149 | #define WM8350_PCCMP_RAIL 0x0100 | ||
150 | #define WM8350_PCCMP_OFF_THR_MASK 0x0070 | ||
151 | #define WM8350_PCCMP_ON_THR_MASK 0x0007 | ||
152 | |||
153 | /* | ||
154 | * R180 (0xB4) - DCDC1 Control | ||
155 | */ | ||
156 | #define WM8350_DC1_OPFLT 0x0400 | ||
157 | #define WM8350_DC1_VSEL_MASK 0x007F | ||
158 | #define WM8350_DC1_VSEL_SHIFT 0 | ||
159 | |||
160 | /* | ||
161 | * R181 (0xB5) - DCDC1 Timeouts | ||
162 | */ | ||
163 | #define WM8350_DC1_ERRACT_MASK 0xC000 | ||
164 | #define WM8350_DC1_ERRACT_SHIFT 14 | ||
165 | #define WM8350_DC1_ENSLOT_MASK 0x3C00 | ||
166 | #define WM8350_DC1_ENSLOT_SHIFT 10 | ||
167 | #define WM8350_DC1_SDSLOT_MASK 0x03C0 | ||
168 | #define WM8350_DC1_UVTO_MASK 0x0030 | ||
169 | #define WM8350_DC1_SDSLOT_SHIFT 6 | ||
170 | |||
171 | /* Bit values for R181 (0xB5) */ | ||
172 | #define WM8350_DC1_ERRACT_NONE 0 | ||
173 | #define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1 | ||
174 | #define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2 | ||
175 | |||
176 | /* | ||
177 | * R182 (0xB6) - DCDC1 Low Power | ||
178 | */ | ||
179 | #define WM8350_DC1_HIB_MODE_MASK 0x7000 | ||
180 | #define WM8350_DC1_HIB_TRIG_MASK 0x0300 | ||
181 | #define WM8350_DC1_VIMG_MASK 0x007F | ||
182 | |||
183 | /* | ||
184 | * R183 (0xB7) - DCDC2 Control | ||
185 | */ | ||
186 | #define WM8350_DC2_MODE 0x4000 | ||
187 | #define WM8350_DC2_MODE_MASK 0x4000 | ||
188 | #define WM8350_DC2_MODE_SHIFT 14 | ||
189 | #define WM8350_DC2_HIB_MODE 0x1000 | ||
190 | #define WM8350_DC2_HIB_MODE_MASK 0x1000 | ||
191 | #define WM8350_DC2_HIB_MODE_SHIFT 12 | ||
192 | #define WM8350_DC2_HIB_TRIG_MASK 0x0300 | ||
193 | #define WM8350_DC2_HIB_TRIG_SHIFT 8 | ||
194 | #define WM8350_DC2_ILIM 0x0040 | ||
195 | #define WM8350_DC2_ILIM_MASK 0x0040 | ||
196 | #define WM8350_DC2_ILIM_SHIFT 6 | ||
197 | #define WM8350_DC2_RMP_MASK 0x0018 | ||
198 | #define WM8350_DC2_RMP_SHIFT 3 | ||
199 | #define WM8350_DC2_FBSRC_MASK 0x0003 | ||
200 | #define WM8350_DC2_FBSRC_SHIFT 0 | ||
201 | |||
202 | /* Bit values for R183 (0xB7) */ | ||
203 | #define WM8350_DC2_MODE_BOOST 0 | ||
204 | #define WM8350_DC2_MODE_SWITCH 1 | ||
205 | |||
206 | #define WM8350_DC2_HIB_MODE_ACTIVE 1 | ||
207 | #define WM8350_DC2_HIB_MODE_DISABLE 0 | ||
208 | |||
209 | #define WM8350_DC2_HIB_TRIG_NONE 0 | ||
210 | #define WM8350_DC2_HIB_TRIG_LPWR1 1 | ||
211 | #define WM8350_DC2_HIB_TRIG_LPWR2 2 | ||
212 | #define WM8350_DC2_HIB_TRIG_LPWR3 3 | ||
213 | |||
214 | #define WM8350_DC2_ILIM_HIGH 0 | ||
215 | #define WM8350_DC2_ILIM_LOW 1 | ||
216 | |||
217 | #define WM8350_DC2_RMP_30V 0 | ||
218 | #define WM8350_DC2_RMP_20V 1 | ||
219 | #define WM8350_DC2_RMP_10V 2 | ||
220 | #define WM8350_DC2_RMP_5V 3 | ||
221 | |||
222 | #define WM8350_DC2_FBSRC_FB2 0 | ||
223 | #define WM8350_DC2_FBSRC_ISINKA 1 | ||
224 | #define WM8350_DC2_FBSRC_ISINKB 2 | ||
225 | #define WM8350_DC2_FBSRC_USB 3 | ||
226 | |||
227 | /* | ||
228 | * R184 (0xB8) - DCDC2 Timeouts | ||
229 | */ | ||
230 | #define WM8350_DC2_ERRACT_MASK 0xC000 | ||
231 | #define WM8350_DC2_ERRACT_SHIFT 14 | ||
232 | #define WM8350_DC2_ENSLOT_MASK 0x3C00 | ||
233 | #define WM8350_DC2_ENSLOT_SHIFT 10 | ||
234 | #define WM8350_DC2_SDSLOT_MASK 0x03C0 | ||
235 | #define WM8350_DC2_UVTO_MASK 0x0030 | ||
236 | |||
237 | /* Bit values for R184 (0xB8) */ | ||
238 | #define WM8350_DC2_ERRACT_NONE 0 | ||
239 | #define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1 | ||
240 | #define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2 | ||
241 | |||
242 | /* | ||
243 | * R186 (0xBA) - DCDC3 Control | ||
244 | */ | ||
245 | #define WM8350_DC3_OPFLT 0x0400 | ||
246 | #define WM8350_DC3_VSEL_MASK 0x007F | ||
247 | #define WM8350_DC3_VSEL_SHIFT 0 | ||
248 | |||
249 | /* | ||
250 | * R187 (0xBB) - DCDC3 Timeouts | ||
251 | */ | ||
252 | #define WM8350_DC3_ERRACT_MASK 0xC000 | ||
253 | #define WM8350_DC3_ERRACT_SHIFT 14 | ||
254 | #define WM8350_DC3_ENSLOT_MASK 0x3C00 | ||
255 | #define WM8350_DC3_ENSLOT_SHIFT 10 | ||
256 | #define WM8350_DC3_SDSLOT_MASK 0x03C0 | ||
257 | #define WM8350_DC3_UVTO_MASK 0x0030 | ||
258 | #define WM8350_DC3_SDSLOT_SHIFT 6 | ||
259 | |||
260 | /* Bit values for R187 (0xBB) */ | ||
261 | #define WM8350_DC3_ERRACT_NONE 0 | ||
262 | #define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1 | ||
263 | #define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2 | ||
264 | /* | ||
265 | * R188 (0xBC) - DCDC3 Low Power | ||
266 | */ | ||
267 | #define WM8350_DC3_HIB_MODE_MASK 0x7000 | ||
268 | #define WM8350_DC3_HIB_TRIG_MASK 0x0300 | ||
269 | #define WM8350_DC3_VIMG_MASK 0x007F | ||
270 | |||
271 | /* | ||
272 | * R189 (0xBD) - DCDC4 Control | ||
273 | */ | ||
274 | #define WM8350_DC4_OPFLT 0x0400 | ||
275 | #define WM8350_DC4_VSEL_MASK 0x007F | ||
276 | #define WM8350_DC4_VSEL_SHIFT 0 | ||
277 | |||
278 | /* | ||
279 | * R190 (0xBE) - DCDC4 Timeouts | ||
280 | */ | ||
281 | #define WM8350_DC4_ERRACT_MASK 0xC000 | ||
282 | #define WM8350_DC4_ERRACT_SHIFT 14 | ||
283 | #define WM8350_DC4_ENSLOT_MASK 0x3C00 | ||
284 | #define WM8350_DC4_ENSLOT_SHIFT 10 | ||
285 | #define WM8350_DC4_SDSLOT_MASK 0x03C0 | ||
286 | #define WM8350_DC4_UVTO_MASK 0x0030 | ||
287 | #define WM8350_DC4_SDSLOT_SHIFT 6 | ||
288 | |||
289 | /* Bit values for R190 (0xBE) */ | ||
290 | #define WM8350_DC4_ERRACT_NONE 0 | ||
291 | #define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1 | ||
292 | #define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2 | ||
293 | |||
294 | /* | ||
295 | * R191 (0xBF) - DCDC4 Low Power | ||
296 | */ | ||
297 | #define WM8350_DC4_HIB_MODE_MASK 0x7000 | ||
298 | #define WM8350_DC4_HIB_TRIG_MASK 0x0300 | ||
299 | #define WM8350_DC4_VIMG_MASK 0x007F | ||
300 | |||
301 | /* | ||
302 | * R192 (0xC0) - DCDC5 Control | ||
303 | */ | ||
304 | #define WM8350_DC5_MODE 0x4000 | ||
305 | #define WM8350_DC5_MODE_MASK 0x4000 | ||
306 | #define WM8350_DC5_MODE_SHIFT 14 | ||
307 | #define WM8350_DC5_HIB_MODE 0x1000 | ||
308 | #define WM8350_DC5_HIB_MODE_MASK 0x1000 | ||
309 | #define WM8350_DC5_HIB_MODE_SHIFT 12 | ||
310 | #define WM8350_DC5_HIB_TRIG_MASK 0x0300 | ||
311 | #define WM8350_DC5_HIB_TRIG_SHIFT 8 | ||
312 | #define WM8350_DC5_ILIM 0x0040 | ||
313 | #define WM8350_DC5_ILIM_MASK 0x0040 | ||
314 | #define WM8350_DC5_ILIM_SHIFT 6 | ||
315 | #define WM8350_DC5_RMP_MASK 0x0018 | ||
316 | #define WM8350_DC5_RMP_SHIFT 3 | ||
317 | #define WM8350_DC5_FBSRC_MASK 0x0003 | ||
318 | #define WM8350_DC5_FBSRC_SHIFT 0 | ||
319 | |||
320 | /* Bit values for R192 (0xC0) */ | ||
321 | #define WM8350_DC5_MODE_BOOST 0 | ||
322 | #define WM8350_DC5_MODE_SWITCH 1 | ||
323 | |||
324 | #define WM8350_DC5_HIB_MODE_ACTIVE 1 | ||
325 | #define WM8350_DC5_HIB_MODE_DISABLE 0 | ||
326 | |||
327 | #define WM8350_DC5_HIB_TRIG_NONE 0 | ||
328 | #define WM8350_DC5_HIB_TRIG_LPWR1 1 | ||
329 | #define WM8350_DC5_HIB_TRIG_LPWR2 2 | ||
330 | #define WM8350_DC5_HIB_TRIG_LPWR3 3 | ||
331 | |||
332 | #define WM8350_DC5_ILIM_HIGH 0 | ||
333 | #define WM8350_DC5_ILIM_LOW 1 | ||
334 | |||
335 | #define WM8350_DC5_RMP_30V 0 | ||
336 | #define WM8350_DC5_RMP_20V 1 | ||
337 | #define WM8350_DC5_RMP_10V 2 | ||
338 | #define WM8350_DC5_RMP_5V 3 | ||
339 | |||
340 | #define WM8350_DC5_FBSRC_FB2 0 | ||
341 | #define WM8350_DC5_FBSRC_ISINKA 1 | ||
342 | #define WM8350_DC5_FBSRC_ISINKB 2 | ||
343 | #define WM8350_DC5_FBSRC_USB 3 | ||
344 | |||
345 | /* | ||
346 | * R193 (0xC1) - DCDC5 Timeouts | ||
347 | */ | ||
348 | #define WM8350_DC5_ERRACT_MASK 0xC000 | ||
349 | #define WM8350_DC5_ERRACT_SHIFT 14 | ||
350 | #define WM8350_DC5_ENSLOT_MASK 0x3C00 | ||
351 | #define WM8350_DC5_ENSLOT_SHIFT 10 | ||
352 | #define WM8350_DC5_SDSLOT_MASK 0x03C0 | ||
353 | #define WM8350_DC5_UVTO_MASK 0x0030 | ||
354 | #define WM8350_DC5_SDSLOT_SHIFT 6 | ||
355 | |||
356 | /* Bit values for R193 (0xC1) */ | ||
357 | #define WM8350_DC5_ERRACT_NONE 0 | ||
358 | #define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1 | ||
359 | #define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2 | ||
360 | |||
361 | /* | ||
362 | * R195 (0xC3) - DCDC6 Control | ||
363 | */ | ||
364 | #define WM8350_DC6_OPFLT 0x0400 | ||
365 | #define WM8350_DC6_VSEL_MASK 0x007F | ||
366 | #define WM8350_DC6_VSEL_SHIFT 0 | ||
367 | |||
368 | /* | ||
369 | * R196 (0xC4) - DCDC6 Timeouts | ||
370 | */ | ||
371 | #define WM8350_DC6_ERRACT_MASK 0xC000 | ||
372 | #define WM8350_DC6_ERRACT_SHIFT 14 | ||
373 | #define WM8350_DC6_ENSLOT_MASK 0x3C00 | ||
374 | #define WM8350_DC6_ENSLOT_SHIFT 10 | ||
375 | #define WM8350_DC6_SDSLOT_MASK 0x03C0 | ||
376 | #define WM8350_DC6_UVTO_MASK 0x0030 | ||
377 | #define WM8350_DC6_SDSLOT_SHIFT 6 | ||
378 | |||
379 | /* Bit values for R196 (0xC4) */ | ||
380 | #define WM8350_DC6_ERRACT_NONE 0 | ||
381 | #define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1 | ||
382 | #define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2 | ||
383 | |||
384 | /* | ||
385 | * R197 (0xC5) - DCDC6 Low Power | ||
386 | */ | ||
387 | #define WM8350_DC6_HIB_MODE_MASK 0x7000 | ||
388 | #define WM8350_DC6_HIB_TRIG_MASK 0x0300 | ||
389 | #define WM8350_DC6_VIMG_MASK 0x007F | ||
390 | |||
391 | /* | ||
392 | * R199 (0xC7) - Limit Switch Control | ||
393 | */ | ||
394 | #define WM8350_LS_ERRACT_MASK 0xC000 | ||
395 | #define WM8350_LS_ERRACT_SHIFT 14 | ||
396 | #define WM8350_LS_ENSLOT_MASK 0x3C00 | ||
397 | #define WM8350_LS_ENSLOT_SHIFT 10 | ||
398 | #define WM8350_LS_SDSLOT_MASK 0x03C0 | ||
399 | #define WM8350_LS_SDSLOT_SHIFT 6 | ||
400 | #define WM8350_LS_HIB_MODE 0x0010 | ||
401 | #define WM8350_LS_HIB_MODE_MASK 0x0010 | ||
402 | #define WM8350_LS_HIB_MODE_SHIFT 4 | ||
403 | #define WM8350_LS_HIB_PROT 0x0002 | ||
404 | #define WM8350_LS_HIB_PROT_MASK 0x0002 | ||
405 | #define WM8350_LS_HIB_PROT_SHIFT 1 | ||
406 | #define WM8350_LS_PROT 0x0001 | ||
407 | #define WM8350_LS_PROT_MASK 0x0001 | ||
408 | #define WM8350_LS_PROT_SHIFT 0 | ||
409 | |||
410 | /* Bit values for R199 (0xC7) */ | ||
411 | #define WM8350_LS_ERRACT_NONE 0 | ||
412 | #define WM8350_LS_ERRACT_SHUTDOWN_CONV 1 | ||
413 | #define WM8350_LS_ERRACT_SHUTDOWN_SYS 2 | ||
414 | |||
415 | /* | ||
416 | * R200 (0xC8) - LDO1 Control | ||
417 | */ | ||
418 | #define WM8350_LDO1_SWI 0x4000 | ||
419 | #define WM8350_LDO1_OPFLT 0x0400 | ||
420 | #define WM8350_LDO1_VSEL_MASK 0x001F | ||
421 | #define WM8350_LDO1_VSEL_SHIFT 0 | ||
422 | |||
423 | /* | ||
424 | * R201 (0xC9) - LDO1 Timeouts | ||
425 | */ | ||
426 | #define WM8350_LDO1_ERRACT_MASK 0xC000 | ||
427 | #define WM8350_LDO1_ERRACT_SHIFT 14 | ||
428 | #define WM8350_LDO1_ENSLOT_MASK 0x3C00 | ||
429 | #define WM8350_LDO1_ENSLOT_SHIFT 10 | ||
430 | #define WM8350_LDO1_SDSLOT_MASK 0x03C0 | ||
431 | #define WM8350_LDO1_UVTO_MASK 0x0030 | ||
432 | #define WM8350_LDO1_SDSLOT_SHIFT 6 | ||
433 | |||
434 | /* Bit values for R201 (0xC9) */ | ||
435 | #define WM8350_LDO1_ERRACT_NONE 0 | ||
436 | #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1 | ||
437 | #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2 | ||
438 | |||
439 | /* | ||
440 | * R202 (0xCA) - LDO1 Low Power | ||
441 | */ | ||
442 | #define WM8350_LDO1_HIB_MODE_MASK 0x3000 | ||
443 | #define WM8350_LDO1_HIB_TRIG_MASK 0x0300 | ||
444 | #define WM8350_LDO1_VIMG_MASK 0x001F | ||
445 | #define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12) | ||
446 | |||
447 | |||
448 | /* | ||
449 | * R203 (0xCB) - LDO2 Control | ||
450 | */ | ||
451 | #define WM8350_LDO2_SWI 0x4000 | ||
452 | #define WM8350_LDO2_OPFLT 0x0400 | ||
453 | #define WM8350_LDO2_VSEL_MASK 0x001F | ||
454 | #define WM8350_LDO2_VSEL_SHIFT 0 | ||
455 | |||
456 | /* | ||
457 | * R204 (0xCC) - LDO2 Timeouts | ||
458 | */ | ||
459 | #define WM8350_LDO2_ERRACT_MASK 0xC000 | ||
460 | #define WM8350_LDO2_ERRACT_SHIFT 14 | ||
461 | #define WM8350_LDO2_ENSLOT_MASK 0x3C00 | ||
462 | #define WM8350_LDO2_ENSLOT_SHIFT 10 | ||
463 | #define WM8350_LDO2_SDSLOT_MASK 0x03C0 | ||
464 | #define WM8350_LDO2_SDSLOT_SHIFT 6 | ||
465 | |||
466 | /* Bit values for R204 (0xCC) */ | ||
467 | #define WM8350_LDO2_ERRACT_NONE 0 | ||
468 | #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1 | ||
469 | #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2 | ||
470 | |||
471 | /* | ||
472 | * R205 (0xCD) - LDO2 Low Power | ||
473 | */ | ||
474 | #define WM8350_LDO2_HIB_MODE_MASK 0x3000 | ||
475 | #define WM8350_LDO2_HIB_TRIG_MASK 0x0300 | ||
476 | #define WM8350_LDO2_VIMG_MASK 0x001F | ||
477 | |||
478 | /* | ||
479 | * R206 (0xCE) - LDO3 Control | ||
480 | */ | ||
481 | #define WM8350_LDO3_SWI 0x4000 | ||
482 | #define WM8350_LDO3_OPFLT 0x0400 | ||
483 | #define WM8350_LDO3_VSEL_MASK 0x001F | ||
484 | #define WM8350_LDO3_VSEL_SHIFT 0 | ||
485 | |||
486 | /* | ||
487 | * R207 (0xCF) - LDO3 Timeouts | ||
488 | */ | ||
489 | #define WM8350_LDO3_ERRACT_MASK 0xC000 | ||
490 | #define WM8350_LDO3_ERRACT_SHIFT 14 | ||
491 | #define WM8350_LDO3_ENSLOT_MASK 0x3C00 | ||
492 | #define WM8350_LDO3_ENSLOT_SHIFT 10 | ||
493 | #define WM8350_LDO3_SDSLOT_MASK 0x03C0 | ||
494 | #define WM8350_LDO3_UVTO_MASK 0x0030 | ||
495 | #define WM8350_LDO3_SDSLOT_SHIFT 6 | ||
496 | |||
497 | /* Bit values for R207 (0xCF) */ | ||
498 | #define WM8350_LDO3_ERRACT_NONE 0 | ||
499 | #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1 | ||
500 | #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2 | ||
501 | |||
502 | /* | ||
503 | * R208 (0xD0) - LDO3 Low Power | ||
504 | */ | ||
505 | #define WM8350_LDO3_HIB_MODE_MASK 0x3000 | ||
506 | #define WM8350_LDO3_HIB_TRIG_MASK 0x0300 | ||
507 | #define WM8350_LDO3_VIMG_MASK 0x001F | ||
508 | |||
509 | /* | ||
510 | * R209 (0xD1) - LDO4 Control | ||
511 | */ | ||
512 | #define WM8350_LDO4_SWI 0x4000 | ||
513 | #define WM8350_LDO4_OPFLT 0x0400 | ||
514 | #define WM8350_LDO4_VSEL_MASK 0x001F | ||
515 | #define WM8350_LDO4_VSEL_SHIFT 0 | ||
516 | |||
517 | /* | ||
518 | * R210 (0xD2) - LDO4 Timeouts | ||
519 | */ | ||
520 | #define WM8350_LDO4_ERRACT_MASK 0xC000 | ||
521 | #define WM8350_LDO4_ERRACT_SHIFT 14 | ||
522 | #define WM8350_LDO4_ENSLOT_MASK 0x3C00 | ||
523 | #define WM8350_LDO4_ENSLOT_SHIFT 10 | ||
524 | #define WM8350_LDO4_SDSLOT_MASK 0x03C0 | ||
525 | #define WM8350_LDO4_UVTO_MASK 0x0030 | ||
526 | #define WM8350_LDO4_SDSLOT_SHIFT 6 | ||
527 | |||
528 | /* Bit values for R210 (0xD2) */ | ||
529 | #define WM8350_LDO4_ERRACT_NONE 0 | ||
530 | #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1 | ||
531 | #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2 | ||
532 | |||
533 | /* | ||
534 | * R211 (0xD3) - LDO4 Low Power | ||
535 | */ | ||
536 | #define WM8350_LDO4_HIB_MODE_MASK 0x3000 | ||
537 | #define WM8350_LDO4_HIB_TRIG_MASK 0x0300 | ||
538 | #define WM8350_LDO4_VIMG_MASK 0x001F | ||
539 | |||
540 | /* | ||
541 | * R215 (0xD7) - VCC_FAULT Masks | ||
542 | */ | ||
543 | #define WM8350_LS_FAULT 0x8000 | ||
544 | #define WM8350_LDO4_FAULT 0x0800 | ||
545 | #define WM8350_LDO3_FAULT 0x0400 | ||
546 | #define WM8350_LDO2_FAULT 0x0200 | ||
547 | #define WM8350_LDO1_FAULT 0x0100 | ||
548 | #define WM8350_DC6_FAULT 0x0020 | ||
549 | #define WM8350_DC5_FAULT 0x0010 | ||
550 | #define WM8350_DC4_FAULT 0x0008 | ||
551 | #define WM8350_DC3_FAULT 0x0004 | ||
552 | #define WM8350_DC2_FAULT 0x0002 | ||
553 | #define WM8350_DC1_FAULT 0x0001 | ||
554 | |||
555 | /* | ||
556 | * R216 (0xD8) - Main Bandgap Control | ||
557 | */ | ||
558 | #define WM8350_MBG_LOAD_FUSES 0x8000 | ||
559 | #define WM8350_MBG_FUSE_WPREP 0x4000 | ||
560 | #define WM8350_MBG_FUSE_WRITE 0x2000 | ||
561 | #define WM8350_MBG_FUSE_TRIM_MASK 0x1F00 | ||
562 | #define WM8350_MBG_TRIM_SRC 0x0020 | ||
563 | #define WM8350_MBG_USER_TRIM_MASK 0x001F | ||
564 | |||
565 | /* | ||
566 | * R217 (0xD9) - OSC Control | ||
567 | */ | ||
568 | #define WM8350_OSC_LOAD_FUSES 0x8000 | ||
569 | #define WM8350_OSC_FUSE_WPREP 0x4000 | ||
570 | #define WM8350_OSC_FUSE_WRITE 0x2000 | ||
571 | #define WM8350_OSC_FUSE_TRIM_MASK 0x0F00 | ||
572 | #define WM8350_OSC_TRIM_SRC 0x0020 | ||
573 | #define WM8350_OSC_USER_TRIM_MASK 0x000F | ||
574 | |||
575 | /* | ||
576 | * R248 (0xF8) - DCDC1 Force PWM | ||
577 | */ | ||
578 | #define WM8350_DCDC1_FORCE_PWM_ENA 0x0010 | ||
579 | |||
580 | /* | ||
581 | * R250 (0xFA) - DCDC3 Force PWM | ||
582 | */ | ||
583 | #define WM8350_DCDC3_FORCE_PWM_ENA 0x0010 | ||
584 | |||
585 | /* | ||
586 | * R251 (0xFB) - DCDC4 Force PWM | ||
587 | */ | ||
588 | #define WM8350_DCDC4_FORCE_PWM_ENA 0x0010 | ||
589 | |||
590 | /* | ||
591 | * R253 (0xFD) - DCDC1 Force PWM | ||
592 | */ | ||
593 | #define WM8350_DCDC6_FORCE_PWM_ENA 0x0010 | ||
594 | |||
595 | /* | ||
596 | * DCDC's | ||
597 | */ | ||
598 | #define WM8350_DCDC_1 0 | ||
599 | #define WM8350_DCDC_2 1 | ||
600 | #define WM8350_DCDC_3 2 | ||
601 | #define WM8350_DCDC_4 3 | ||
602 | #define WM8350_DCDC_5 4 | ||
603 | #define WM8350_DCDC_6 5 | ||
604 | |||
605 | /* DCDC modes */ | ||
606 | #define WM8350_DCDC_ACTIVE_STANDBY 0 | ||
607 | #define WM8350_DCDC_ACTIVE_PULSE 1 | ||
608 | #define WM8350_DCDC_SLEEP_NORMAL 0 | ||
609 | #define WM8350_DCDC_SLEEP_LOW 1 | ||
610 | |||
611 | /* DCDC Low power (Hibernate) mode */ | ||
612 | #define WM8350_DCDC_HIB_MODE_CUR (0 << 12) | ||
613 | #define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12) | ||
614 | #define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12) | ||
615 | #define WM8350_DCDC_HIB_MODE_LDO (4 << 12) | ||
616 | #define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12) | ||
617 | #define WM8350_DCDC_HIB_MODE_DIS (7 << 12) | ||
618 | #define WM8350_DCDC_HIB_MODE_MASK (7 << 12) | ||
619 | |||
620 | /* DCDC Low Power (Hibernate) signal */ | ||
621 | #define WM8350_DCDC_HIB_SIG_REG (0 << 8) | ||
622 | #define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8) | ||
623 | #define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8) | ||
624 | #define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8) | ||
625 | |||
626 | /* LDO Low power (Hibernate) mode */ | ||
627 | #define WM8350_LDO_HIB_MODE_IMAGE (0 << 0) | ||
628 | #define WM8350_LDO_HIB_MODE_DIS (1 << 0) | ||
629 | |||
630 | /* LDO Low Power (Hibernate) signal */ | ||
631 | #define WM8350_LDO_HIB_SIG_REG (0 << 8) | ||
632 | #define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8) | ||
633 | #define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8) | ||
634 | #define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8) | ||
635 | |||
636 | /* | ||
637 | * LDOs | ||
638 | */ | ||
639 | #define WM8350_LDO_1 6 | ||
640 | #define WM8350_LDO_2 7 | ||
641 | #define WM8350_LDO_3 8 | ||
642 | #define WM8350_LDO_4 9 | ||
643 | |||
644 | /* | ||
645 | * ISINKs | ||
646 | */ | ||
647 | #define WM8350_ISINK_A 10 | ||
648 | #define WM8350_ISINK_B 11 | ||
649 | |||
650 | #define WM8350_ISINK_MODE_BOOST 0 | ||
651 | #define WM8350_ISINK_MODE_SWITCH 1 | ||
652 | #define WM8350_ISINK_ILIM_NORMAL 0 | ||
653 | #define WM8350_ISINK_ILIM_LOW 1 | ||
654 | |||
655 | #define WM8350_ISINK_FLASH_DISABLE 0 | ||
656 | #define WM8350_ISINK_FLASH_ENABLE 1 | ||
657 | #define WM8350_ISINK_FLASH_TRIG_BIT 0 | ||
658 | #define WM8350_ISINK_FLASH_TRIG_GPIO 1 | ||
659 | #define WM8350_ISINK_FLASH_MODE_EN (1 << 13) | ||
660 | #define WM8350_ISINK_FLASH_MODE_DIS (0 << 13) | ||
661 | #define WM8350_ISINK_FLASH_DUR_32MS (0 << 8) | ||
662 | #define WM8350_ISINK_FLASH_DUR_64MS (1 << 8) | ||
663 | #define WM8350_ISINK_FLASH_DUR_96MS (2 << 8) | ||
664 | #define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8) | ||
665 | #define WM8350_ISINK_FLASH_ON_INSTANT (0 << 4) | ||
666 | #define WM8350_ISINK_FLASH_ON_0_25S (1 << 4) | ||
667 | #define WM8350_ISINK_FLASH_ON_0_50S (2 << 4) | ||
668 | #define WM8350_ISINK_FLASH_ON_1_00S (3 << 4) | ||
669 | #define WM8350_ISINK_FLASH_ON_1_95S (1 << 4) | ||
670 | #define WM8350_ISINK_FLASH_ON_3_91S (2 << 4) | ||
671 | #define WM8350_ISINK_FLASH_ON_7_80S (3 << 4) | ||
672 | #define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 0) | ||
673 | #define WM8350_ISINK_FLASH_OFF_0_25S (1 << 0) | ||
674 | #define WM8350_ISINK_FLASH_OFF_0_50S (2 << 0) | ||
675 | #define WM8350_ISINK_FLASH_OFF_1_00S (3 << 0) | ||
676 | #define WM8350_ISINK_FLASH_OFF_1_95S (1 << 0) | ||
677 | #define WM8350_ISINK_FLASH_OFF_3_91S (2 << 0) | ||
678 | #define WM8350_ISINK_FLASH_OFF_7_80S (3 << 0) | ||
679 | |||
680 | /* | ||
681 | * Regulator Interrupts. | ||
682 | */ | ||
683 | #define WM8350_IRQ_CS1 13 | ||
684 | #define WM8350_IRQ_CS2 14 | ||
685 | #define WM8350_IRQ_UV_LDO4 25 | ||
686 | #define WM8350_IRQ_UV_LDO3 26 | ||
687 | #define WM8350_IRQ_UV_LDO2 27 | ||
688 | #define WM8350_IRQ_UV_LDO1 28 | ||
689 | #define WM8350_IRQ_UV_DC6 29 | ||
690 | #define WM8350_IRQ_UV_DC5 30 | ||
691 | #define WM8350_IRQ_UV_DC4 31 | ||
692 | #define WM8350_IRQ_UV_DC3 32 | ||
693 | #define WM8350_IRQ_UV_DC2 33 | ||
694 | #define WM8350_IRQ_UV_DC1 34 | ||
695 | #define WM8350_IRQ_OC_LS 35 | ||
696 | |||
697 | #define NUM_WM8350_REGULATORS 12 | ||
698 | |||
699 | struct wm8350; | ||
700 | struct platform_device; | ||
701 | struct regulator_init_data; | ||
702 | |||
703 | struct wm8350_pmic { | ||
704 | /* ISINK to DCDC mapping */ | ||
705 | int isink_A_dcdc; | ||
706 | int isink_B_dcdc; | ||
707 | |||
708 | /* hibernate configs */ | ||
709 | u16 dcdc1_hib_mode; | ||
710 | u16 dcdc3_hib_mode; | ||
711 | u16 dcdc4_hib_mode; | ||
712 | u16 dcdc6_hib_mode; | ||
713 | |||
714 | /* regulator devices */ | ||
715 | struct platform_device *pdev[NUM_WM8350_REGULATORS]; | ||
716 | }; | ||
717 | |||
718 | int wm8350_register_regulator(struct wm8350 *wm8350, int reg, | ||
719 | struct regulator_init_data *initdata); | ||
720 | |||
721 | /* | ||
722 | * Additional DCDC control not supported via regulator API | ||
723 | */ | ||
724 | int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start, | ||
725 | u16 stop, u16 fault); | ||
726 | int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode, | ||
727 | u16 ilim, u16 ramp, u16 feedback); | ||
728 | |||
729 | /* | ||
730 | * Additional LDO control not supported via regulator API | ||
731 | */ | ||
732 | int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop); | ||
733 | |||
734 | /* | ||
735 | * Additional ISINK control not supported via regulator API | ||
736 | */ | ||
737 | int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode, | ||
738 | u16 trigger, u16 duration, u16 on_ramp, | ||
739 | u16 off_ramp, u16 drive); | ||
740 | |||
741 | #endif | ||
diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h new file mode 100644 index 000000000000..dfda69e9f440 --- /dev/null +++ b/include/linux/mfd/wm8350/rtc.h | |||
@@ -0,0 +1,266 @@ | |||
1 | /* | ||
2 | * rtc.h -- RTC driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __LINUX_MFD_WM8350_RTC_H | ||
13 | #define __LINUX_MFD_WM8350_RTC_H | ||
14 | |||
15 | #include <linux/platform_device.h> | ||
16 | |||
17 | /* | ||
18 | * Register values. | ||
19 | */ | ||
20 | #define WM8350_RTC_SECONDS_MINUTES 0x10 | ||
21 | #define WM8350_RTC_HOURS_DAY 0x11 | ||
22 | #define WM8350_RTC_DATE_MONTH 0x12 | ||
23 | #define WM8350_RTC_YEAR 0x13 | ||
24 | #define WM8350_ALARM_SECONDS_MINUTES 0x14 | ||
25 | #define WM8350_ALARM_HOURS_DAY 0x15 | ||
26 | #define WM8350_ALARM_DATE_MONTH 0x16 | ||
27 | #define WM8350_RTC_TIME_CONTROL 0x17 | ||
28 | |||
29 | /* | ||
30 | * R16 (0x10) - RTC Seconds/Minutes | ||
31 | */ | ||
32 | #define WM8350_RTC_MINS_MASK 0x7F00 | ||
33 | #define WM8350_RTC_MINS_SHIFT 8 | ||
34 | #define WM8350_RTC_SECS_MASK 0x007F | ||
35 | #define WM8350_RTC_SECS_SHIFT 0 | ||
36 | |||
37 | /* | ||
38 | * R17 (0x11) - RTC Hours/Day | ||
39 | */ | ||
40 | #define WM8350_RTC_DAY_MASK 0x0700 | ||
41 | #define WM8350_RTC_DAY_SHIFT 8 | ||
42 | #define WM8350_RTC_HPM_MASK 0x0020 | ||
43 | #define WM8350_RTC_HPM_SHIFT 5 | ||
44 | #define WM8350_RTC_HRS_MASK 0x001F | ||
45 | #define WM8350_RTC_HRS_SHIFT 0 | ||
46 | |||
47 | /* Bit values for R21 (0x15) */ | ||
48 | #define WM8350_RTC_DAY_SUN 1 | ||
49 | #define WM8350_RTC_DAY_MON 2 | ||
50 | #define WM8350_RTC_DAY_TUE 3 | ||
51 | #define WM8350_RTC_DAY_WED 4 | ||
52 | #define WM8350_RTC_DAY_THU 5 | ||
53 | #define WM8350_RTC_DAY_FRI 6 | ||
54 | #define WM8350_RTC_DAY_SAT 7 | ||
55 | |||
56 | #define WM8350_RTC_HPM_AM 0 | ||
57 | #define WM8350_RTC_HPM_PM 1 | ||
58 | |||
59 | /* | ||
60 | * R18 (0x12) - RTC Date/Month | ||
61 | */ | ||
62 | #define WM8350_RTC_MTH_MASK 0x1F00 | ||
63 | #define WM8350_RTC_MTH_SHIFT 8 | ||
64 | #define WM8350_RTC_DATE_MASK 0x003F | ||
65 | #define WM8350_RTC_DATE_SHIFT 0 | ||
66 | |||
67 | /* Bit values for R22 (0x16) */ | ||
68 | #define WM8350_RTC_MTH_JAN 1 | ||
69 | #define WM8350_RTC_MTH_FEB 2 | ||
70 | #define WM8350_RTC_MTH_MAR 3 | ||
71 | #define WM8350_RTC_MTH_APR 4 | ||
72 | #define WM8350_RTC_MTH_MAY 5 | ||
73 | #define WM8350_RTC_MTH_JUN 6 | ||
74 | #define WM8350_RTC_MTH_JUL 7 | ||
75 | #define WM8350_RTC_MTH_AUG 8 | ||
76 | #define WM8350_RTC_MTH_SEP 9 | ||
77 | #define WM8350_RTC_MTH_OCT 10 | ||
78 | #define WM8350_RTC_MTH_NOV 11 | ||
79 | #define WM8350_RTC_MTH_DEC 12 | ||
80 | #define WM8350_RTC_MTH_JAN_BCD 0x01 | ||
81 | #define WM8350_RTC_MTH_FEB_BCD 0x02 | ||
82 | #define WM8350_RTC_MTH_MAR_BCD 0x03 | ||
83 | #define WM8350_RTC_MTH_APR_BCD 0x04 | ||
84 | #define WM8350_RTC_MTH_MAY_BCD 0x05 | ||
85 | #define WM8350_RTC_MTH_JUN_BCD 0x06 | ||
86 | #define WM8350_RTC_MTH_JUL_BCD 0x07 | ||
87 | #define WM8350_RTC_MTH_AUG_BCD 0x08 | ||
88 | #define WM8350_RTC_MTH_SEP_BCD 0x09 | ||
89 | #define WM8350_RTC_MTH_OCT_BCD 0x10 | ||
90 | #define WM8350_RTC_MTH_NOV_BCD 0x11 | ||
91 | #define WM8350_RTC_MTH_DEC_BCD 0x12 | ||
92 | |||
93 | /* | ||
94 | * R19 (0x13) - RTC Year | ||
95 | */ | ||
96 | #define WM8350_RTC_YHUNDREDS_MASK 0x3F00 | ||
97 | #define WM8350_RTC_YHUNDREDS_SHIFT 8 | ||
98 | #define WM8350_RTC_YUNITS_MASK 0x00FF | ||
99 | #define WM8350_RTC_YUNITS_SHIFT 0 | ||
100 | |||
101 | /* | ||
102 | * R20 (0x14) - Alarm Seconds/Minutes | ||
103 | */ | ||
104 | #define WM8350_RTC_ALMMINS_MASK 0x7F00 | ||
105 | #define WM8350_RTC_ALMMINS_SHIFT 8 | ||
106 | #define WM8350_RTC_ALMSECS_MASK 0x007F | ||
107 | #define WM8350_RTC_ALMSECS_SHIFT 0 | ||
108 | |||
109 | /* Bit values for R20 (0x14) */ | ||
110 | #define WM8350_RTC_ALMMINS_DONT_CARE -1 | ||
111 | #define WM8350_RTC_ALMSECS_DONT_CARE -1 | ||
112 | |||
113 | /* | ||
114 | * R21 (0x15) - Alarm Hours/Day | ||
115 | */ | ||
116 | #define WM8350_RTC_ALMDAY_MASK 0x0F00 | ||
117 | #define WM8350_RTC_ALMDAY_SHIFT 8 | ||
118 | #define WM8350_RTC_ALMHPM_MASK 0x0020 | ||
119 | #define WM8350_RTC_ALMHPM_SHIFT 5 | ||
120 | #define WM8350_RTC_ALMHRS_MASK 0x001F | ||
121 | #define WM8350_RTC_ALMHRS_SHIFT 0 | ||
122 | |||
123 | /* Bit values for R21 (0x15) */ | ||
124 | #define WM8350_RTC_ALMDAY_DONT_CARE -1 | ||
125 | #define WM8350_RTC_ALMDAY_SUN 1 | ||
126 | #define WM8350_RTC_ALMDAY_MON 2 | ||
127 | #define WM8350_RTC_ALMDAY_TUE 3 | ||
128 | #define WM8350_RTC_ALMDAY_WED 4 | ||
129 | #define WM8350_RTC_ALMDAY_THU 5 | ||
130 | #define WM8350_RTC_ALMDAY_FRI 6 | ||
131 | #define WM8350_RTC_ALMDAY_SAT 7 | ||
132 | |||
133 | #define WM8350_RTC_ALMHPM_AM 0 | ||
134 | #define WM8350_RTC_ALMHPM_PM 1 | ||
135 | |||
136 | #define WM8350_RTC_ALMHRS_DONT_CARE -1 | ||
137 | |||
138 | /* | ||
139 | * R22 (0x16) - Alarm Date/Month | ||
140 | */ | ||
141 | #define WM8350_RTC_ALMMTH_MASK 0x1F00 | ||
142 | #define WM8350_RTC_ALMMTH_SHIFT 8 | ||
143 | #define WM8350_RTC_ALMDATE_MASK 0x003F | ||
144 | #define WM8350_RTC_ALMDATE_SHIFT 0 | ||
145 | |||
146 | /* Bit values for R22 (0x16) */ | ||
147 | #define WM8350_RTC_ALMDATE_DONT_CARE -1 | ||
148 | |||
149 | #define WM8350_RTC_ALMMTH_DONT_CARE -1 | ||
150 | #define WM8350_RTC_ALMMTH_JAN 1 | ||
151 | #define WM8350_RTC_ALMMTH_FEB 2 | ||
152 | #define WM8350_RTC_ALMMTH_MAR 3 | ||
153 | #define WM8350_RTC_ALMMTH_APR 4 | ||
154 | #define WM8350_RTC_ALMMTH_MAY 5 | ||
155 | #define WM8350_RTC_ALMMTH_JUN 6 | ||
156 | #define WM8350_RTC_ALMMTH_JUL 7 | ||
157 | #define WM8350_RTC_ALMMTH_AUG 8 | ||
158 | #define WM8350_RTC_ALMMTH_SEP 9 | ||
159 | #define WM8350_RTC_ALMMTH_OCT 10 | ||
160 | #define WM8350_RTC_ALMMTH_NOV 11 | ||
161 | #define WM8350_RTC_ALMMTH_DEC 12 | ||
162 | #define WM8350_RTC_ALMMTH_JAN_BCD 0x01 | ||
163 | #define WM8350_RTC_ALMMTH_FEB_BCD 0x02 | ||
164 | #define WM8350_RTC_ALMMTH_MAR_BCD 0x03 | ||
165 | #define WM8350_RTC_ALMMTH_APR_BCD 0x04 | ||
166 | #define WM8350_RTC_ALMMTH_MAY_BCD 0x05 | ||
167 | #define WM8350_RTC_ALMMTH_JUN_BCD 0x06 | ||
168 | #define WM8350_RTC_ALMMTH_JUL_BCD 0x07 | ||
169 | #define WM8350_RTC_ALMMTH_AUG_BCD 0x08 | ||
170 | #define WM8350_RTC_ALMMTH_SEP_BCD 0x09 | ||
171 | #define WM8350_RTC_ALMMTH_OCT_BCD 0x10 | ||
172 | #define WM8350_RTC_ALMMTH_NOV_BCD 0x11 | ||
173 | #define WM8350_RTC_ALMMTH_DEC_BCD 0x12 | ||
174 | |||
175 | /* | ||
176 | * R23 (0x17) - RTC Time Control | ||
177 | */ | ||
178 | #define WM8350_RTC_BCD 0x8000 | ||
179 | #define WM8350_RTC_BCD_MASK 0x8000 | ||
180 | #define WM8350_RTC_BCD_SHIFT 15 | ||
181 | #define WM8350_RTC_12HR 0x4000 | ||
182 | #define WM8350_RTC_12HR_MASK 0x4000 | ||
183 | #define WM8350_RTC_12HR_SHIFT 14 | ||
184 | #define WM8350_RTC_DST 0x2000 | ||
185 | #define WM8350_RTC_DST_MASK 0x2000 | ||
186 | #define WM8350_RTC_DST_SHIFT 13 | ||
187 | #define WM8350_RTC_SET 0x0800 | ||
188 | #define WM8350_RTC_SET_MASK 0x0800 | ||
189 | #define WM8350_RTC_SET_SHIFT 11 | ||
190 | #define WM8350_RTC_STS 0x0400 | ||
191 | #define WM8350_RTC_STS_MASK 0x0400 | ||
192 | #define WM8350_RTC_STS_SHIFT 10 | ||
193 | #define WM8350_RTC_ALMSET 0x0200 | ||
194 | #define WM8350_RTC_ALMSET_MASK 0x0200 | ||
195 | #define WM8350_RTC_ALMSET_SHIFT 9 | ||
196 | #define WM8350_RTC_ALMSTS 0x0100 | ||
197 | #define WM8350_RTC_ALMSTS_MASK 0x0100 | ||
198 | #define WM8350_RTC_ALMSTS_SHIFT 8 | ||
199 | #define WM8350_RTC_PINT 0x0070 | ||
200 | #define WM8350_RTC_PINT_MASK 0x0070 | ||
201 | #define WM8350_RTC_PINT_SHIFT 4 | ||
202 | #define WM8350_RTC_DSW 0x000F | ||
203 | #define WM8350_RTC_DSW_MASK 0x000F | ||
204 | #define WM8350_RTC_DSW_SHIFT 0 | ||
205 | |||
206 | /* Bit values for R23 (0x17) */ | ||
207 | #define WM8350_RTC_BCD_BINARY 0 | ||
208 | #define WM8350_RTC_BCD_BCD 1 | ||
209 | |||
210 | #define WM8350_RTC_12HR_24HR 0 | ||
211 | #define WM8350_RTC_12HR_12HR 1 | ||
212 | |||
213 | #define WM8350_RTC_DST_DISABLED 0 | ||
214 | #define WM8350_RTC_DST_ENABLED 1 | ||
215 | |||
216 | #define WM8350_RTC_SET_RUN 0 | ||
217 | #define WM8350_RTC_SET_SET 1 | ||
218 | |||
219 | #define WM8350_RTC_STS_RUNNING 0 | ||
220 | #define WM8350_RTC_STS_STOPPED 1 | ||
221 | |||
222 | #define WM8350_RTC_ALMSET_RUN 0 | ||
223 | #define WM8350_RTC_ALMSET_SET 1 | ||
224 | |||
225 | #define WM8350_RTC_ALMSTS_RUNNING 0 | ||
226 | #define WM8350_RTC_ALMSTS_STOPPED 1 | ||
227 | |||
228 | #define WM8350_RTC_PINT_DISABLED 0 | ||
229 | #define WM8350_RTC_PINT_SECS 1 | ||
230 | #define WM8350_RTC_PINT_MINS 2 | ||
231 | #define WM8350_RTC_PINT_HRS 3 | ||
232 | #define WM8350_RTC_PINT_DAYS 4 | ||
233 | #define WM8350_RTC_PINT_MTHS 5 | ||
234 | |||
235 | #define WM8350_RTC_DSW_DISABLED 0 | ||
236 | #define WM8350_RTC_DSW_1HZ 1 | ||
237 | #define WM8350_RTC_DSW_2HZ 2 | ||
238 | #define WM8350_RTC_DSW_4HZ 3 | ||
239 | #define WM8350_RTC_DSW_8HZ 4 | ||
240 | #define WM8350_RTC_DSW_16HZ 5 | ||
241 | #define WM8350_RTC_DSW_32HZ 6 | ||
242 | #define WM8350_RTC_DSW_64HZ 7 | ||
243 | #define WM8350_RTC_DSW_128HZ 8 | ||
244 | #define WM8350_RTC_DSW_256HZ 9 | ||
245 | #define WM8350_RTC_DSW_512HZ 10 | ||
246 | #define WM8350_RTC_DSW_1024HZ 11 | ||
247 | |||
248 | /* | ||
249 | * R218 (0xDA) - RTC Tick Control | ||
250 | */ | ||
251 | #define WM8350_RTC_TICKSTS 0x4000 | ||
252 | #define WM8350_RTC_CLKSRC 0x2000 | ||
253 | #define WM8350_RTC_TRIM_MASK 0x03FF | ||
254 | |||
255 | /* | ||
256 | * RTC Interrupts. | ||
257 | */ | ||
258 | #define WM8350_IRQ_RTC_PER 7 | ||
259 | #define WM8350_IRQ_RTC_SEC 8 | ||
260 | #define WM8350_IRQ_RTC_ALM 9 | ||
261 | |||
262 | struct wm8350_rtc { | ||
263 | struct platform_device *pdev; | ||
264 | }; | ||
265 | |||
266 | #endif | ||
diff --git a/include/linux/mfd/wm8350/supply.h b/include/linux/mfd/wm8350/supply.h new file mode 100644 index 000000000000..1c8f3cde79b0 --- /dev/null +++ b/include/linux/mfd/wm8350/supply.h | |||
@@ -0,0 +1,111 @@ | |||
1 | /* | ||
2 | * supply.h -- Power Supply Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | */ | ||
12 | |||
13 | #ifndef __LINUX_MFD_WM8350_SUPPLY_H_ | ||
14 | #define __LINUX_MFD_WM8350_SUPPLY_H_ | ||
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | /* | ||
19 | * Charger registers | ||
20 | */ | ||
21 | #define WM8350_BATTERY_CHARGER_CONTROL_1 0xA8 | ||
22 | #define WM8350_BATTERY_CHARGER_CONTROL_2 0xA9 | ||
23 | #define WM8350_BATTERY_CHARGER_CONTROL_3 0xAA | ||
24 | |||
25 | /* | ||
26 | * R168 (0xA8) - Battery Charger Control 1 | ||
27 | */ | ||
28 | #define WM8350_CHG_ENA_R168 0x8000 | ||
29 | #define WM8350_CHG_THR 0x2000 | ||
30 | #define WM8350_CHG_EOC_SEL_MASK 0x1C00 | ||
31 | #define WM8350_CHG_TRICKLE_TEMP_CHOKE 0x0200 | ||
32 | #define WM8350_CHG_TRICKLE_USB_CHOKE 0x0100 | ||
33 | #define WM8350_CHG_RECOVER_T 0x0080 | ||
34 | #define WM8350_CHG_END_ACT 0x0040 | ||
35 | #define WM8350_CHG_FAST 0x0020 | ||
36 | #define WM8350_CHG_FAST_USB_THROTTLE 0x0010 | ||
37 | #define WM8350_CHG_NTC_MON 0x0008 | ||
38 | #define WM8350_CHG_BATT_HOT_MON 0x0004 | ||
39 | #define WM8350_CHG_BATT_COLD_MON 0x0002 | ||
40 | #define WM8350_CHG_CHIP_TEMP_MON 0x0001 | ||
41 | |||
42 | /* | ||
43 | * R169 (0xA9) - Battery Charger Control 2 | ||
44 | */ | ||
45 | #define WM8350_CHG_ACTIVE 0x8000 | ||
46 | #define WM8350_CHG_PAUSE 0x4000 | ||
47 | #define WM8350_CHG_STS_MASK 0x3000 | ||
48 | #define WM8350_CHG_TIME_MASK 0x0F00 | ||
49 | #define WM8350_CHG_MASK_WALL_FB 0x0080 | ||
50 | #define WM8350_CHG_TRICKLE_SEL 0x0040 | ||
51 | #define WM8350_CHG_VSEL_MASK 0x0030 | ||
52 | #define WM8350_CHG_ISEL_MASK 0x000F | ||
53 | #define WM8350_CHG_STS_OFF 0x0000 | ||
54 | #define WM8350_CHG_STS_TRICKLE 0x1000 | ||
55 | #define WM8350_CHG_STS_FAST 0x2000 | ||
56 | |||
57 | /* | ||
58 | * R170 (0xAA) - Battery Charger Control 3 | ||
59 | */ | ||
60 | #define WM8350_CHG_THROTTLE_T_MASK 0x0060 | ||
61 | #define WM8350_CHG_SMART 0x0010 | ||
62 | #define WM8350_CHG_TIMER_ADJT_MASK 0x000F | ||
63 | |||
64 | /* | ||
65 | * Charger Interrupts | ||
66 | */ | ||
67 | #define WM8350_IRQ_CHG_BAT_HOT 0 | ||
68 | #define WM8350_IRQ_CHG_BAT_COLD 1 | ||
69 | #define WM8350_IRQ_CHG_BAT_FAIL 2 | ||
70 | #define WM8350_IRQ_CHG_TO 3 | ||
71 | #define WM8350_IRQ_CHG_END 4 | ||
72 | #define WM8350_IRQ_CHG_START 5 | ||
73 | #define WM8350_IRQ_CHG_FAST_RDY 6 | ||
74 | #define WM8350_IRQ_CHG_VBATT_LT_3P9 10 | ||
75 | #define WM8350_IRQ_CHG_VBATT_LT_3P1 11 | ||
76 | #define WM8350_IRQ_CHG_VBATT_LT_2P85 12 | ||
77 | |||
78 | /* | ||
79 | * Charger Policy | ||
80 | */ | ||
81 | #define WM8350_CHG_TRICKLE_50mA (0 << 6) | ||
82 | #define WM8350_CHG_TRICKLE_100mA (1 << 6) | ||
83 | #define WM8350_CHG_4_05V (0 << 4) | ||
84 | #define WM8350_CHG_4_10V (1 << 4) | ||
85 | #define WM8350_CHG_4_15V (2 << 4) | ||
86 | #define WM8350_CHG_4_20V (3 << 4) | ||
87 | #define WM8350_CHG_FAST_LIMIT_mA(x) ((x / 50) & 0xf) | ||
88 | #define WM8350_CHG_EOC_mA(x) (((x - 10) & 0x7) << 10) | ||
89 | #define WM8350_CHG_TRICKLE_3_1V (0 << 13) | ||
90 | #define WM8350_CHG_TRICKLE_3_9V (1 << 13) | ||
91 | |||
92 | /* | ||
93 | * Supply Registers. | ||
94 | */ | ||
95 | #define WM8350_USB_VOLTAGE_READBACK 0x9C | ||
96 | #define WM8350_LINE_VOLTAGE_READBACK 0x9D | ||
97 | #define WM8350_BATT_VOLTAGE_READBACK 0x9E | ||
98 | |||
99 | /* | ||
100 | * Supply Interrupts. | ||
101 | */ | ||
102 | #define WM8350_IRQ_USB_LIMIT 15 | ||
103 | #define WM8350_IRQ_EXT_USB_FB 36 | ||
104 | #define WM8350_IRQ_EXT_WALL_FB 37 | ||
105 | #define WM8350_IRQ_EXT_BAT_FB 38 | ||
106 | |||
107 | struct wm8350_power { | ||
108 | struct platform_device *pdev; | ||
109 | }; | ||
110 | |||
111 | #endif | ||
diff --git a/include/linux/mfd/wm8350/wdt.h b/include/linux/mfd/wm8350/wdt.h new file mode 100644 index 000000000000..f6135b5e5ef4 --- /dev/null +++ b/include/linux/mfd/wm8350/wdt.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * wdt.h -- Watchdog Driver for Wolfson WM8350 PMIC | ||
3 | * | ||
4 | * Copyright 2007, 2008 Wolfson Microelectronics PLC | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __LINUX_MFD_WM8350_WDT_H_ | ||
13 | #define __LINUX_MFD_WM8350_WDT_H_ | ||
14 | |||
15 | #include <linux/platform_device.h> | ||
16 | |||
17 | #define WM8350_WDOG_HIB_MODE 0x0080 | ||
18 | #define WM8350_WDOG_DEBUG 0x0040 | ||
19 | #define WM8350_WDOG_MODE_MASK 0x0030 | ||
20 | #define WM8350_WDOG_TO_MASK 0x0007 | ||
21 | |||
22 | #define WM8350_IRQ_SYS_WDOG_TO 24 | ||
23 | |||
24 | struct wm8350_wdt { | ||
25 | struct platform_device *pdev; | ||
26 | }; | ||
27 | |||
28 | #endif | ||