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Diffstat (limited to 'include/linux/mfd/ti_am335x_tscadc.h')
-rw-r--r--include/linux/mfd/ti_am335x_tscadc.h20
1 files changed, 13 insertions, 7 deletions
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h
index 08cce7f96ab9..d498d98f0c2c 100644
--- a/include/linux/mfd/ti_am335x_tscadc.h
+++ b/include/linux/mfd/ti_am335x_tscadc.h
@@ -134,13 +134,18 @@
134#define FIFO1_THRESHOLD 19 134#define FIFO1_THRESHOLD 19
135 135
136/* 136/*
137* ADC runs at 3MHz, and it takes 137 * time in us for processing a single channel, calculated as follows:
138* 15 cycles to latch one data output. 138 *
139* Hence the idle time for ADC to 139 * num cycles = open delay + (sample delay + conv time) * averaging
140* process one sample data would be 140 *
141* around 5 micro seconds. 141 * num cycles: 152 + (1 + 13) * 16 = 376
142*/ 142 *
143#define IDLE_TIMEOUT 5 /* microsec */ 143 * clock frequency: 26MHz / 8 = 3.25MHz
144 * clock period: 1 / 3.25MHz = 308ns
145 *
146 * processing time: 376 * 308ns = 116us
147 */
148#define IDLE_TIMEOUT 116 /* microsec */
144 149
145#define TSCADC_CELLS 2 150#define TSCADC_CELLS 2
146 151
@@ -155,6 +160,7 @@ struct ti_tscadc_dev {
155 struct mfd_cell cells[TSCADC_CELLS]; 160 struct mfd_cell cells[TSCADC_CELLS];
156 u32 reg_se_cache; 161 u32 reg_se_cache;
157 spinlock_t reg_lock; 162 spinlock_t reg_lock;
163 unsigned int clk_div;
158 164
159 /* tsc device */ 165 /* tsc device */
160 struct titsc *tsc; 166 struct titsc *tsc;