diff options
Diffstat (limited to 'include/linux/mfd/rtsx_pci.h')
-rw-r--r-- | include/linux/mfd/rtsx_pci.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h index 74346d5e7899..0c12628e91c6 100644 --- a/include/linux/mfd/rtsx_pci.h +++ b/include/linux/mfd/rtsx_pci.h | |||
@@ -558,6 +558,7 @@ | |||
558 | #define SD_SAMPLE_POINT_CTL 0xFDA7 | 558 | #define SD_SAMPLE_POINT_CTL 0xFDA7 |
559 | #define SD_PUSH_POINT_CTL 0xFDA8 | 559 | #define SD_PUSH_POINT_CTL 0xFDA8 |
560 | #define SD_CMD0 0xFDA9 | 560 | #define SD_CMD0 0xFDA9 |
561 | #define SD_CMD_START 0x40 | ||
561 | #define SD_CMD1 0xFDAA | 562 | #define SD_CMD1 0xFDAA |
562 | #define SD_CMD2 0xFDAB | 563 | #define SD_CMD2 0xFDAB |
563 | #define SD_CMD3 0xFDAC | 564 | #define SD_CMD3 0xFDAC |
@@ -707,6 +708,14 @@ | |||
707 | #define PM_CTRL1 0xFF44 | 708 | #define PM_CTRL1 0xFF44 |
708 | #define PM_CTRL2 0xFF45 | 709 | #define PM_CTRL2 0xFF45 |
709 | #define PM_CTRL3 0xFF46 | 710 | #define PM_CTRL3 0xFF46 |
711 | #define SDIO_SEND_PME_EN 0x80 | ||
712 | #define FORCE_RC_MODE_ON 0x40 | ||
713 | #define FORCE_RX50_LINK_ON 0x20 | ||
714 | #define D3_DELINK_MODE_EN 0x10 | ||
715 | #define USE_PESRTB_CTL_DELINK 0x08 | ||
716 | #define DELAY_PIN_WAKE 0x04 | ||
717 | #define RESET_PIN_WAKE 0x02 | ||
718 | #define PM_WAKE_EN 0x01 | ||
710 | #define PM_CTRL4 0xFF47 | 719 | #define PM_CTRL4 0xFF47 |
711 | 720 | ||
712 | /* Memory mapping */ | 721 | /* Memory mapping */ |
@@ -752,6 +761,14 @@ | |||
752 | #define PHY_DUM_REG 0x1F | 761 | #define PHY_DUM_REG 0x1F |
753 | 762 | ||
754 | #define LCTLR 0x80 | 763 | #define LCTLR 0x80 |
764 | #define LCTLR_EXT_SYNC 0x80 | ||
765 | #define LCTLR_COMMON_CLOCK_CFG 0x40 | ||
766 | #define LCTLR_RETRAIN_LINK 0x20 | ||
767 | #define LCTLR_LINK_DISABLE 0x10 | ||
768 | #define LCTLR_RCB 0x08 | ||
769 | #define LCTLR_RESERVED 0x04 | ||
770 | #define LCTLR_ASPM_CTL_MASK 0x03 | ||
771 | |||
755 | #define PCR_SETTING_REG1 0x724 | 772 | #define PCR_SETTING_REG1 0x724 |
756 | #define PCR_SETTING_REG2 0x814 | 773 | #define PCR_SETTING_REG2 0x814 |
757 | #define PCR_SETTING_REG3 0x747 | 774 | #define PCR_SETTING_REG3 0x747 |
@@ -967,4 +984,24 @@ static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) | |||
967 | return (u8 *)(pcr->host_cmds_ptr); | 984 | return (u8 *)(pcr->host_cmds_ptr); |
968 | } | 985 | } |
969 | 986 | ||
987 | static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr, | ||
988 | u8 mask, u8 append) | ||
989 | { | ||
990 | int err; | ||
991 | u8 val; | ||
992 | |||
993 | err = pci_read_config_byte(pcr->pci, addr, &val); | ||
994 | if (err < 0) | ||
995 | return err; | ||
996 | return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); | ||
997 | } | ||
998 | |||
999 | static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) | ||
1000 | { | ||
1001 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); | ||
1002 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); | ||
1003 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); | ||
1004 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); | ||
1005 | } | ||
1006 | |||
970 | #endif | 1007 | #endif |