1 files changed, 454 insertions, 0 deletions
diff --git a/include/linux/mfd/max77843-private.h b/include/linux/mfd/max77843-private.h
new file mode 100644
index 000000000000..7178ace8379e
--- /dev/null
+++ b/include/linux/mfd/max77843-private.h
@@ -0,0 +1,454 @@
+/*
+ * Common variables for the Maxim MAX77843 driver
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ * Author: Jaewon Kim <jaewon02.kim@samsung.com>
+ * Author: Beomho Seo <beomho.seo@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __MAX77843_PRIVATE_H_
+#define __MAX77843_PRIVATE_H_
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#define I2C_ADDR_TOPSYS (0xCC >> 1)
+#define I2C_ADDR_CHG    (0xD2 >> 1)
+#define I2C_ADDR_FG     (0x6C >> 1)
+#define I2C_ADDR_MUIC   (0x4A >> 1)
+/* Topsys, Haptic and LED registers */
+enum max77843_sys_reg {
+        MAX77843_SYS_REG_PMICID         = 0x00,
+        MAX77843_SYS_REG_PMICREV        = 0x01,
+        MAX77843_SYS_REG_MAINCTRL1      = 0x02,
+        MAX77843_SYS_REG_INTSRC         = 0x22,
+        MAX77843_SYS_REG_INTSRCMASK     = 0x23,
+        MAX77843_SYS_REG_SYSINTSRC      = 0x24,
+        MAX77843_SYS_REG_SYSINTMASK     = 0x26,
+        MAX77843_SYS_REG_TOPSYS_STAT    = 0x28,
+        MAX77843_SYS_REG_SAFEOUTCTRL    = 0xC6,
+        MAX77843_SYS_REG_END,
+};
+enum max77843_haptic_reg {
+        MAX77843_HAP_REG_MCONFIG        = 0x10,
+        MAX77843_HAP_REG_END,
+};
+enum max77843_led_reg {
+        MAX77843_LED_REG_LEDEN          = 0x30,
+        MAX77843_LED_REG_LED0BRT        = 0x31,
+        MAX77843_LED_REG_LED1BRT        = 0x32,
+        MAX77843_LED_REG_LED2BRT        = 0x33,
+        MAX77843_LED_REG_LED3BRT        = 0x34,
+        MAX77843_LED_REG_LEDBLNK        = 0x38,
+        MAX77843_LED_REG_LEDRAMP        = 0x36,
+        MAX77843_LED_REG_END,
+};
+/* Charger registers */
+enum max77843_charger_reg {
+        MAX77843_CHG_REG_CHG_INT        = 0xB0,
+        MAX77843_CHG_REG_CHG_INT_MASK   = 0xB1,
+        MAX77843_CHG_REG_CHG_INT_OK     = 0xB2,
+        MAX77843_CHG_REG_CHG_DTLS_00    = 0xB3,
+        MAX77843_CHG_REG_CHG_DTLS_01    = 0xB4,
+        MAX77843_CHG_REG_CHG_DTLS_02    = 0xB5,
+        MAX77843_CHG_REG_CHG_CNFG_00    = 0xB7,
+        MAX77843_CHG_REG_CHG_CNFG_01    = 0xB8,
+        MAX77843_CHG_REG_CHG_CNFG_02    = 0xB9,
+        MAX77843_CHG_REG_CHG_CNFG_03    = 0xBA,
+        MAX77843_CHG_REG_CHG_CNFG_04    = 0xBB,
+        MAX77843_CHG_REG_CHG_CNFG_06    = 0xBD,
+        MAX77843_CHG_REG_CHG_CNFG_07    = 0xBE,
+        MAX77843_CHG_REG_CHG_CNFG_09    = 0xC0,
+        MAX77843_CHG_REG_CHG_CNFG_10    = 0xC1,
+        MAX77843_CHG_REG_CHG_CNFG_11    = 0xC2,
+        MAX77843_CHG_REG_CHG_CNFG_12    = 0xC3,
+        MAX77843_CHG_REG_END,
+};
+/* Fuel gauge registers */
+enum max77843_fuelgauge {
+        MAX77843_FG_REG_STATUS          = 0x00,
+        MAX77843_FG_REG_VALRT_TH        = 0x01,
+        MAX77843_FG_REG_TALRT_TH        = 0x02,
+        MAX77843_FG_REG_SALRT_TH        = 0x03,
+        MAX77843_FG_RATE_AT_RATE        = 0x04,
+        MAX77843_FG_REG_REMCAP_REP      = 0x05,
+        MAX77843_FG_REG_SOCREP          = 0x06,
+        MAX77843_FG_REG_AGE             = 0x07,
+        MAX77843_FG_REG_TEMP            = 0x08,
+        MAX77843_FG_REG_VCELL           = 0x09,
+        MAX77843_FG_REG_CURRENT         = 0x0A,
+        MAX77843_FG_REG_AVG_CURRENT     = 0x0B,
+        MAX77843_FG_REG_SOCMIX          = 0x0D,
+        MAX77843_FG_REG_SOCAV           = 0x0E,
+        MAX77843_FG_REG_REMCAP_MIX      = 0x0F,
+        MAX77843_FG_REG_FULLCAP         = 0x10,
+        MAX77843_FG_REG_AVG_TEMP        = 0x16,
+        MAX77843_FG_REG_CYCLES          = 0x17,
+        MAX77843_FG_REG_AVG_VCELL       = 0x19,
+        MAX77843_FG_REG_CONFIG          = 0x1D,
+        MAX77843_FG_REG_REMCAP_AV       = 0x1F,
+        MAX77843_FG_REG_FULLCAP_NOM     = 0x23,
+        MAX77843_FG_REG_MISCCFG         = 0x2B,
+        MAX77843_FG_REG_RCOMP           = 0x38,
+        MAX77843_FG_REG_FSTAT           = 0x3D,
+        MAX77843_FG_REG_DQACC           = 0x45,
+        MAX77843_FG_REG_DPACC           = 0x46,
+        MAX77843_FG_REG_OCV             = 0xEE,
+        MAX77843_FG_REG_VFOCV           = 0xFB,
+        MAX77843_FG_SOCVF               = 0xFF,
+        MAX77843_FG_END,
+};
+/* MUIC registers */
+enum max77843_muic_reg {
+        MAX77843_MUIC_REG_ID            = 0x00,
+        MAX77843_MUIC_REG_INT1          = 0x01,
+        MAX77843_MUIC_REG_INT2          = 0x02,
+        MAX77843_MUIC_REG_INT3          = 0x03,
+        MAX77843_MUIC_REG_STATUS1       = 0x04,
+        MAX77843_MUIC_REG_STATUS2       = 0x05,
+        MAX77843_MUIC_REG_STATUS3       = 0x06,
+        MAX77843_MUIC_REG_INTMASK1      = 0x07,
+        MAX77843_MUIC_REG_INTMASK2      = 0x08,
+        MAX77843_MUIC_REG_INTMASK3      = 0x09,
+        MAX77843_MUIC_REG_CDETCTRL1     = 0x0A,
+        MAX77843_MUIC_REG_CDETCTRL2     = 0x0B,
+        MAX77843_MUIC_REG_CONTROL1      = 0x0C,
+        MAX77843_MUIC_REG_CONTROL2      = 0x0D,
+        MAX77843_MUIC_REG_CONTROL3      = 0x0E,
+        MAX77843_MUIC_REG_CONTROL4      = 0x16,
+        MAX77843_MUIC_REG_HVCONTROL1    = 0x17,
+        MAX77843_MUIC_REG_HVCONTROL2    = 0x18,
+        MAX77843_MUIC_REG_END,
+};
+enum max77843_irq {
+        /* Topsys: SYSTEM */
+        MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
+        MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
+        MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
+        MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
+        /* Charger: CHG_INT */
+        MAX77843_CHG_IRQ_CHG_INT_BYP_I,
+        MAX77843_CHG_IRQ_CHG_INT_BATP_I,
+        MAX77843_CHG_IRQ_CHG_INT_BAT_I,
+        MAX77843_CHG_IRQ_CHG_INT_CHG_I,
+        MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
+        MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
+        MAX77843_CHG_IRQ_CHG_INT_AICL_I,
+        MAX77843_IRQ_NUM,
+};
+enum max77843_irq_muic {
+        /* MUIC: INT1 */
+        MAX77843_MUIC_IRQ_INT1_ADC,
+        MAX77843_MUIC_IRQ_INT1_ADCERROR,
+        MAX77843_MUIC_IRQ_INT1_ADC1K,
+        /* MUIC: INT2 */
+        MAX77843_MUIC_IRQ_INT2_CHGTYP,
+        MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
+        MAX77843_MUIC_IRQ_INT2_DCDTMR,
+        MAX77843_MUIC_IRQ_INT2_DXOVP,
+        MAX77843_MUIC_IRQ_INT2_VBVOLT,
+        /* MUIC: INT3 */
+        MAX77843_MUIC_IRQ_INT3_VBADC,
+        MAX77843_MUIC_IRQ_INT3_VDNMON,
+        MAX77843_MUIC_IRQ_INT3_DNRES,
+        MAX77843_MUIC_IRQ_INT3_MPNACK,
+        MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
+        MAX77843_MUIC_IRQ_INT3_MRXTRF,
+        MAX77843_MUIC_IRQ_INT3_MRXPERR,
+        MAX77843_MUIC_IRQ_INT3_MRXRDY,
+        MAX77843_MUIC_IRQ_NUM,
+};
+/* MAX77843 interrupts */
+#define MAX77843_SYS_IRQ_SYSUVLO_INT            BIT(0)
+#define MAX77843_SYS_IRQ_SYSOVLO_INT            BIT(1)
+#define MAX77843_SYS_IRQ_TSHDN_INT              BIT(2)
+#define MAX77843_SYS_IRQ_TM_INT                 BIT(3)
+/* MAX77843 MAINCTRL1 register */
+#define MAINCTRL1_BIASEN_SHIFT                  7
+#define MAX77843_MAINCTRL1_BIASEN_MASK          BIT(MAINCTRL1_BIASEN_SHIFT)
+/* MAX77843 MCONFIG register */
+#define MCONFIG_MODE_SHIFT                      7
+#define MCONFIG_MEN_SHIFT                       6
+#define MCONFIG_PDIV_SHIFT                      0
+#define MAX77843_MCONFIG_MODE_MASK              BIT(MCONFIG_MODE_SHIFT)
+#define MAX77843_MCONFIG_MEN_MASK               BIT(MCONFIG_MEN_SHIFT)
+#define MAX77843_MCONFIG_PDIV_MASK              (0x3 << MCONFIG_PDIV_SHIFT)
+/* Max77843 charger insterrupts */
+#define MAX77843_CHG_BYP_I                      BIT(0)
+#define MAX77843_CHG_BATP_I                     BIT(2)
+#define MAX77843_CHG_BAT_I                      BIT(3)
+#define MAX77843_CHG_CHG_I                      BIT(4)
+#define MAX77843_CHG_WCIN_I                     BIT(5)
+#define MAX77843_CHG_CHGIN_I                    BIT(6)
+#define MAX77843_CHG_AICL_I                     BIT(7)
+/* MAX77843 CHG_INT_OK register */
+#define MAX77843_CHG_BYP_OK                     BIT(0)
+#define MAX77843_CHG_BATP_OK                    BIT(2)
+#define MAX77843_CHG_BAT_OK                     BIT(3)
+#define MAX77843_CHG_CHG_OK                     BIT(4)
+#define MAX77843_CHG_WCIN_OK                    BIT(5)
+#define MAX77843_CHG_CHGIN_OK                   BIT(6)
+#define MAX77843_CHG_AICL_OK                    BIT(7)
+/* MAX77843 CHG_DETAILS_00 register */
+#define MAX77843_CHG_BAT_DTLS                   BIT(0)
+/* MAX77843 CHG_DETAILS_01 register */
+#define MAX77843_CHG_DTLS_MASK                  0x0f
+#define MAX77843_CHG_PQ_MODE                    0x00
+#define MAX77843_CHG_CC_MODE                    0x01
+#define MAX77843_CHG_CV_MODE                    0x02
+#define MAX77843_CHG_TO_MODE                    0x03
+#define MAX77843_CHG_DO_MODE                    0x04
+#define MAX77843_CHG_HT_MODE                    0x05
+#define MAX77843_CHG_TF_MODE                    0x06
+#define MAX77843_CHG_TS_MODE                    0x07
+#define MAX77843_CHG_OFF_MODE                   0x08
+#define MAX77843_CHG_BAT_DTLS_MASK              0xf0
+#define MAX77843_CHG_NO_BAT                     (0x00 << 4)
+#define MAX77843_CHG_LOW_VOLT_BAT               (0x01 << 4)
+#define MAX77843_CHG_LONG_BAT_TIME              (0x02 << 4)
+#define MAX77843_CHG_OK_BAT                     (0x03 << 4)
+#define MAX77843_CHG_OK_LOW_VOLT_BAT            (0x04 << 4)
+#define MAX77843_CHG_OVER_VOLT_BAT              (0x05 << 4)
+#define MAX77843_CHG_OVER_CURRENT_BAT           (0x06 << 4)
+/* MAX77843 CHG_CNFG_00 register */
+#define MAX77843_CHG_DISABLE                    0x00
+#define MAX77843_CHG_ENABLE                     0x05
+#define MAX77843_CHG_MASK                       0x01
+#define MAX77843_CHG_BUCK_MASK                  0x04
+/* MAX77843 CHG_CNFG_01 register */
+#define MAX77843_CHG_RESTART_THRESHOLD_100      0x00
+#define MAX77843_CHG_RESTART_THRESHOLD_150      0x10
+#define MAX77843_CHG_RESTART_THRESHOLD_200      0x20
+#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE  0x30
+/* MAX77843 CHG_CNFG_02 register */
+#define MAX77843_CHG_FAST_CHG_CURRENT_MIN       100000
+#define MAX77843_CHG_FAST_CHG_CURRENT_MAX       3150000
+#define MAX77843_CHG_FAST_CHG_CURRENT_STEP      50000
+#define MAX77843_CHG_FAST_CHG_CURRENT_MASK      0x3f
+#define MAX77843_CHG_OTG_ILIMIT_500             (0x00 << 6)
+#define MAX77843_CHG_OTG_ILIMIT_900             (0x01 << 6)
+#define MAX77843_CHG_OTG_ILIMIT_1200            (0x02 << 6)
+#define MAX77843_CHG_OTG_ILIMIT_1500            (0x03 << 6)
+#define MAX77843_CHG_OTG_ILIMIT_MASK            0xc0
+/* MAX77843 CHG_CNFG_03 register */
+#define MAX77843_CHG_TOP_OFF_CURRENT_MIN        125000
+#define MAX77843_CHG_TOP_OFF_CURRENT_MAX        650000
+#define MAX77843_CHG_TOP_OFF_CURRENT_STEP       75000
+#define MAX77843_CHG_TOP_OFF_CURRENT_MASK       0x07
+/* MAX77843 CHG_CNFG_06 register */
+#define MAX77843_CHG_WRITE_CAP_BLOCK            0x10
+#define MAX77843_CHG_WRITE_CAP_UNBLOCK          0x0C
+/* MAX77843_CHG_CNFG_09_register */
+#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN    100000
+#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX    4000000
+#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF    3367000
+#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP   33000
+#define MAX77843_MUIC_ADC                       BIT(0)
+#define MAX77843_MUIC_ADCERROR                  BIT(2)
+#define MAX77843_MUIC_ADC1K                     BIT(3)
+#define MAX77843_MUIC_CHGTYP                    BIT(0)
+#define MAX77843_MUIC_CHGDETRUN                 BIT(1)
+#define MAX77843_MUIC_DCDTMR                    BIT(2)
+#define MAX77843_MUIC_DXOVP                     BIT(3)
+#define MAX77843_MUIC_VBVOLT                    BIT(4)
+#define MAX77843_MUIC_VBADC                     BIT(0)
+#define MAX77843_MUIC_VDNMON                    BIT(1)
+#define MAX77843_MUIC_DNRES                     BIT(2)
+#define MAX77843_MUIC_MPNACK                    BIT(3)
+#define MAX77843_MUIC_MRXBUFOW                  BIT(4)
+#define MAX77843_MUIC_MRXTRF                    BIT(5)
+#define MAX77843_MUIC_MRXPERR                   BIT(6)
+#define MAX77843_MUIC_MRXRDY                    BIT(7)
+/* MAX77843 INTSRCMASK register */
+#define MAX77843_INTSRCMASK_CHGR                0
+#define MAX77843_INTSRCMASK_SYS                 1
+#define MAX77843_INTSRCMASK_FG                  2
+#define MAX77843_INTSRCMASK_MUIC                3
+#define MAX77843_INTSRCMASK_CHGR_MASK          BIT(MAX77843_INTSRCMASK_CHGR)
+#define MAX77843_INTSRCMASK_SYS_MASK           BIT(MAX77843_INTSRCMASK_SYS)
+#define MAX77843_INTSRCMASK_FG_MASK            BIT(MAX77843_INTSRCMASK_FG)
+#define MAX77843_INTSRCMASK_MUIC_MASK          BIT(MAX77843_INTSRCMASK_MUIC)
+#define MAX77843_INTSRC_MASK_MASK \
+        (MAX77843_INTSRCMASK_MUIC_MASK | MAX77843_INTSRCMASK_FG_MASK | \
+        MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK)
+/* MAX77843 STATUS register*/
+#define STATUS1_ADC_SHIFT                       0
+#define STATUS1_ADCERROR_SHIFT                  6
+#define STATUS1_ADC1K_SHIFT                     7
+#define STATUS2_CHGTYP_SHIFT                    0
+#define STATUS2_CHGDETRUN_SHIFT                 3
+#define STATUS2_DCDTMR_SHIFT                    4
+#define STATUS2_DXOVP_SHIFT                     5
+#define STATUS2_VBVOLT_SHIFT                    6
+#define STATUS3_VBADC_SHIFT                     0
+#define STATUS3_VDNMON_SHIFT                    4
+#define STATUS3_DNRES_SHIFT                     5
+#define STATUS3_MPNACK_SHIFT                    6
+#define MAX77843_MUIC_STATUS1_ADC_MASK          (0x1f << STATUS1_ADC_SHIFT)
+#define MAX77843_MUIC_STATUS1_ADCERROR_MASK     BIT(STATUS1_ADCERROR_SHIFT)
+#define MAX77843_MUIC_STATUS1_ADC1K_MASK        BIT(STATUS1_ADC1K_SHIFT)
+#define MAX77843_MUIC_STATUS2_CHGTYP_MASK       (0x7 << STATUS2_CHGTYP_SHIFT)
+#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK    BIT(STATUS2_CHGDETRUN_SHIFT)
+#define MAX77843_MUIC_STATUS2_DCDTMR_MASK       BIT(STATUS2_DCDTMR_SHIFT)
+#define MAX77843_MUIC_STATUS2_DXOVP_MASK        BIT(STATUS2_DXOVP_SHIFT)
+#define MAX77843_MUIC_STATUS2_VBVOLT_MASK       BIT(STATUS2_VBVOLT_SHIFT)
+#define MAX77843_MUIC_STATUS3_VBADC_MASK        (0xf << STATUS3_VBADC_SHIFT)
+#define MAX77843_MUIC_STATUS3_VDNMON_MASK       BIT(STATUS3_VDNMON_SHIFT)
+#define MAX77843_MUIC_STATUS3_DNRES_MASK        BIT(STATUS3_DNRES_SHIFT)
+#define MAX77843_MUIC_STATUS3_MPNACK_MASK       BIT(STATUS3_MPNACK_SHIFT)
+/* MAX77843 CONTROL register */
+#define CONTROL1_COMP1SW_SHIFT                  0
+#define CONTROL1_COMP2SW_SHIFT                  3
+#define CONTROL1_IDBEN_SHIFT                    7
+#define CONTROL2_LOWPWR_SHIFT                   0
+#define CONTROL2_ADCEN_SHIFT                    1
+#define CONTROL2_CPEN_SHIFT                     2
+#define CONTROL2_ACC_DET_SHIFT                  5
+#define CONTROL2_USBCPINT_SHIFT                 6
+#define CONTROL2_RCPS_SHIFT                     7
+#define CONTROL3_JIGSET_SHIFT                   0
+#define CONTROL4_ADCDBSET_SHIFT                 0
+#define CONTROL4_USBAUTO_SHIFT                  4
+#define CONTROL4_FCTAUTO_SHIFT                  5
+#define CONTROL4_ADCMODE_SHIFT                  6
+#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK     (0x7 << CONTROL1_COMP1SW_SHIFT)
+#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK     (0x7 << CONTROL1_COMP2SW_SHIFT)
+#define MAX77843_MUIC_CONTROL1_IDBEN_MASK       BIT(CONTROL1_IDBEN_SHIFT)
+#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK      BIT(CONTROL2_LOWPWR_SHIFT)
+#define MAX77843_MUIC_CONTROL2_ADCEN_MASK       BIT(CONTROL2_ADCEN_SHIFT)
+#define MAX77843_MUIC_CONTROL2_CPEN_MASK        BIT(CONTROL2_CPEN_SHIFT)
+#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK     BIT(CONTROL2_ACC_DET_SHIFT)
+#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK    BIT(CONTROL2_USBCPINT_SHIFT)
+#define MAX77843_MUIC_CONTROL2_RCPS_MASK        BIT(CONTROL2_RCPS_SHIFT)
+#define MAX77843_MUIC_CONTROL3_JIGSET_MASK      (0x3 << CONTROL3_JIGSET_SHIFT)
+#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK    (0x3 << CONTROL4_ADCDBSET_SHIFT)
+#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK     BIT(CONTROL4_USBAUTO_SHIFT)
+#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK     BIT(CONTROL4_FCTAUTO_SHIFT)
+#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK     (0x3 << CONTROL4_ADCMODE_SHIFT)
+/* MAX77843 switch port */
+#define COM_OPEN                                0
+#define COM_USB                                 1
+#define COM_AUDIO                               2
+#define COM_UART                                3
+#define COM_AUX_USB                             4
+#define COM_AUX_UART                            5
+#define CONTROL1_COM_SW \
+        ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \
+         MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
+#define CONTROL1_SW_OPEN \
+        ((COM_OPEN << CONTROL1_COMP1SW_SHIFT | \
+         COM_OPEN << CONTROL1_COMP2SW_SHIFT))
+#define CONTROL1_SW_USB \
+        ((COM_USB << CONTROL1_COMP1SW_SHIFT | \
+         COM_USB << CONTROL1_COMP2SW_SHIFT))
+#define CONTROL1_SW_AUDIO \
+        ((COM_AUDIO << CONTROL1_COMP1SW_SHIFT | \
+         COM_AUDIO << CONTROL1_COMP2SW_SHIFT))
+#define CONTROL1_SW_UART \
+        ((COM_UART << CONTROL1_COMP1SW_SHIFT | \
+         COM_UART << CONTROL1_COMP2SW_SHIFT))
+#define CONTROL1_SW_AUX_USB \
+        ((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT | \
+         COM_AUX_USB << CONTROL1_COMP2SW_SHIFT))
+#define CONTROL1_SW_AUX_UART \
+        ((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT | \
+         COM_AUX_UART << CONTROL1_COMP2SW_SHIFT))
+#define MAX77843_DISABLE                        0
+#define MAX77843_ENABLE                         1
+#define CONTROL4_AUTO_DISABLE \
+        ((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) | \
+        (MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT))
+#define CONTROL4_AUTO_ENABLE \
+        ((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) | \
+        (MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT))
+/* MAX77843 SAFEOUT LDO Control register */
+#define SAFEOUTCTRL_SAFEOUT1_SHIFT              0
+#define SAFEOUTCTRL_SAFEOUT2_SHIFT              2
+#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT            6
+#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT            7
+#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
+                BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
+#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
+                BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
+#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
+                (0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
+#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
+                (0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
+struct max77843 {
+        struct device *dev;
+        struct i2c_client *i2c;
+        struct i2c_client *i2c_chg;
+        struct i2c_client *i2c_fuel;
+        struct i2c_client *i2c_muic;
+        struct regmap *regmap;
+        struct regmap *regmap_chg;
+        struct regmap *regmap_fuel;
+        struct regmap *regmap_muic;
+        struct regmap_irq_chip_data *irq_data;
+        struct regmap_irq_chip_data *irq_data_chg;
+        struct regmap_irq_chip_data *irq_data_fuel;
+        struct regmap_irq_chip_data *irq_data_muic;
+        int irq;
+};
+#endif /* __MAX77843_H__ */

diff --git a/include/linux/mfd/max77843-private.h b/include/linux/mfd/max77843-private.h new file mode 100644 index 000000000000..7178ace8379e --- /dev/null +++ b/include/linux/mfd/max77843-private.h
@@ -0,0 +1,454 @@
	1	/*
	2	* Common variables for the Maxim MAX77843 driver
	3	*
	4	* Copyright (C) 2015 Samsung Electronics
	5	* Author: Jaewon Kim <jaewon02.kim@samsung.com>
	6	* Author: Beomho Seo <beomho.seo@samsung.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#ifndef __MAX77843_PRIVATE_H_
	15	#define __MAX77843_PRIVATE_H_
	16
	17	#include <linux/i2c.h>
	18	#include <linux/regmap.h>
	19
	20	#define I2C_ADDR_TOPSYS (0xCC >> 1)
	21	#define I2C_ADDR_CHG (0xD2 >> 1)
	22	#define I2C_ADDR_FG (0x6C >> 1)
	23	#define I2C_ADDR_MUIC (0x4A >> 1)
	24
	25	/* Topsys, Haptic and LED registers */
	26	enum max77843_sys_reg {
	27	MAX77843_SYS_REG_PMICID = 0x00,
	28	MAX77843_SYS_REG_PMICREV = 0x01,
	29	MAX77843_SYS_REG_MAINCTRL1 = 0x02,
	30	MAX77843_SYS_REG_INTSRC = 0x22,
	31	MAX77843_SYS_REG_INTSRCMASK = 0x23,
	32	MAX77843_SYS_REG_SYSINTSRC = 0x24,
	33	MAX77843_SYS_REG_SYSINTMASK = 0x26,
	34	MAX77843_SYS_REG_TOPSYS_STAT = 0x28,
	35	MAX77843_SYS_REG_SAFEOUTCTRL = 0xC6,
	36
	37	MAX77843_SYS_REG_END,
	38	};
	39
	40	enum max77843_haptic_reg {
	41	MAX77843_HAP_REG_MCONFIG = 0x10,
	42
	43	MAX77843_HAP_REG_END,
	44	};
	45
	46	enum max77843_led_reg {
	47	MAX77843_LED_REG_LEDEN = 0x30,
	48	MAX77843_LED_REG_LED0BRT = 0x31,
	49	MAX77843_LED_REG_LED1BRT = 0x32,
	50	MAX77843_LED_REG_LED2BRT = 0x33,
	51	MAX77843_LED_REG_LED3BRT = 0x34,
	52	MAX77843_LED_REG_LEDBLNK = 0x38,
	53	MAX77843_LED_REG_LEDRAMP = 0x36,
	54
	55	MAX77843_LED_REG_END,
	56	};
	57
	58	/* Charger registers */
	59	enum max77843_charger_reg {
	60	MAX77843_CHG_REG_CHG_INT = 0xB0,
	61	MAX77843_CHG_REG_CHG_INT_MASK = 0xB1,
	62	MAX77843_CHG_REG_CHG_INT_OK = 0xB2,
	63	MAX77843_CHG_REG_CHG_DTLS_00 = 0xB3,
	64	MAX77843_CHG_REG_CHG_DTLS_01 = 0xB4,
	65	MAX77843_CHG_REG_CHG_DTLS_02 = 0xB5,
	66	MAX77843_CHG_REG_CHG_CNFG_00 = 0xB7,
	67	MAX77843_CHG_REG_CHG_CNFG_01 = 0xB8,
	68	MAX77843_CHG_REG_CHG_CNFG_02 = 0xB9,
	69	MAX77843_CHG_REG_CHG_CNFG_03 = 0xBA,
	70	MAX77843_CHG_REG_CHG_CNFG_04 = 0xBB,
	71	MAX77843_CHG_REG_CHG_CNFG_06 = 0xBD,
	72	MAX77843_CHG_REG_CHG_CNFG_07 = 0xBE,
	73	MAX77843_CHG_REG_CHG_CNFG_09 = 0xC0,
	74	MAX77843_CHG_REG_CHG_CNFG_10 = 0xC1,
	75	MAX77843_CHG_REG_CHG_CNFG_11 = 0xC2,
	76	MAX77843_CHG_REG_CHG_CNFG_12 = 0xC3,
	77
	78	MAX77843_CHG_REG_END,
	79	};
	80
	81	/* Fuel gauge registers */
	82	enum max77843_fuelgauge {
	83	MAX77843_FG_REG_STATUS = 0x00,
	84	MAX77843_FG_REG_VALRT_TH = 0x01,
	85	MAX77843_FG_REG_TALRT_TH = 0x02,
	86	MAX77843_FG_REG_SALRT_TH = 0x03,
	87	MAX77843_FG_RATE_AT_RATE = 0x04,
	88	MAX77843_FG_REG_REMCAP_REP = 0x05,
	89	MAX77843_FG_REG_SOCREP = 0x06,
	90	MAX77843_FG_REG_AGE = 0x07,
	91	MAX77843_FG_REG_TEMP = 0x08,
	92	MAX77843_FG_REG_VCELL = 0x09,
	93	MAX77843_FG_REG_CURRENT = 0x0A,
	94	MAX77843_FG_REG_AVG_CURRENT = 0x0B,
	95	MAX77843_FG_REG_SOCMIX = 0x0D,
	96	MAX77843_FG_REG_SOCAV = 0x0E,
	97	MAX77843_FG_REG_REMCAP_MIX = 0x0F,
	98	MAX77843_FG_REG_FULLCAP = 0x10,
	99	MAX77843_FG_REG_AVG_TEMP = 0x16,
	100	MAX77843_FG_REG_CYCLES = 0x17,
	101	MAX77843_FG_REG_AVG_VCELL = 0x19,
	102	MAX77843_FG_REG_CONFIG = 0x1D,
	103	MAX77843_FG_REG_REMCAP_AV = 0x1F,
	104	MAX77843_FG_REG_FULLCAP_NOM = 0x23,
	105	MAX77843_FG_REG_MISCCFG = 0x2B,
	106	MAX77843_FG_REG_RCOMP = 0x38,
	107	MAX77843_FG_REG_FSTAT = 0x3D,
	108	MAX77843_FG_REG_DQACC = 0x45,
	109	MAX77843_FG_REG_DPACC = 0x46,
	110	MAX77843_FG_REG_OCV = 0xEE,
	111	MAX77843_FG_REG_VFOCV = 0xFB,
	112	MAX77843_FG_SOCVF = 0xFF,
	113
	114	MAX77843_FG_END,
	115	};
	116
	117	/* MUIC registers */
	118	enum max77843_muic_reg {
	119	MAX77843_MUIC_REG_ID = 0x00,
	120	MAX77843_MUIC_REG_INT1 = 0x01,
	121	MAX77843_MUIC_REG_INT2 = 0x02,
	122	MAX77843_MUIC_REG_INT3 = 0x03,
	123	MAX77843_MUIC_REG_STATUS1 = 0x04,
	124	MAX77843_MUIC_REG_STATUS2 = 0x05,
	125	MAX77843_MUIC_REG_STATUS3 = 0x06,
	126	MAX77843_MUIC_REG_INTMASK1 = 0x07,
	127	MAX77843_MUIC_REG_INTMASK2 = 0x08,
	128	MAX77843_MUIC_REG_INTMASK3 = 0x09,
	129	MAX77843_MUIC_REG_CDETCTRL1 = 0x0A,
	130	MAX77843_MUIC_REG_CDETCTRL2 = 0x0B,
	131	MAX77843_MUIC_REG_CONTROL1 = 0x0C,
	132	MAX77843_MUIC_REG_CONTROL2 = 0x0D,
	133	MAX77843_MUIC_REG_CONTROL3 = 0x0E,
	134	MAX77843_MUIC_REG_CONTROL4 = 0x16,
	135	MAX77843_MUIC_REG_HVCONTROL1 = 0x17,
	136	MAX77843_MUIC_REG_HVCONTROL2 = 0x18,
	137
	138	MAX77843_MUIC_REG_END,
	139	};
	140
	141	enum max77843_irq {
	142	/* Topsys: SYSTEM */
	143	MAX77843_SYS_IRQ_SYSINTSRC_SYSUVLO_INT,
	144	MAX77843_SYS_IRQ_SYSINTSRC_SYSOVLO_INT,
	145	MAX77843_SYS_IRQ_SYSINTSRC_TSHDN_INT,
	146	MAX77843_SYS_IRQ_SYSINTSRC_TM_INT,
	147
	148	/* Charger: CHG_INT */
	149	MAX77843_CHG_IRQ_CHG_INT_BYP_I,
	150	MAX77843_CHG_IRQ_CHG_INT_BATP_I,
	151	MAX77843_CHG_IRQ_CHG_INT_BAT_I,
	152	MAX77843_CHG_IRQ_CHG_INT_CHG_I,
	153	MAX77843_CHG_IRQ_CHG_INT_WCIN_I,
	154	MAX77843_CHG_IRQ_CHG_INT_CHGIN_I,
	155	MAX77843_CHG_IRQ_CHG_INT_AICL_I,
	156
	157	MAX77843_IRQ_NUM,
	158	};
	159
	160	enum max77843_irq_muic {
	161	/* MUIC: INT1 */
	162	MAX77843_MUIC_IRQ_INT1_ADC,
	163	MAX77843_MUIC_IRQ_INT1_ADCERROR,
	164	MAX77843_MUIC_IRQ_INT1_ADC1K,
	165
	166	/* MUIC: INT2 */
	167	MAX77843_MUIC_IRQ_INT2_CHGTYP,
	168	MAX77843_MUIC_IRQ_INT2_CHGDETRUN,
	169	MAX77843_MUIC_IRQ_INT2_DCDTMR,
	170	MAX77843_MUIC_IRQ_INT2_DXOVP,
	171	MAX77843_MUIC_IRQ_INT2_VBVOLT,
	172
	173	/* MUIC: INT3 */
	174	MAX77843_MUIC_IRQ_INT3_VBADC,
	175	MAX77843_MUIC_IRQ_INT3_VDNMON,
	176	MAX77843_MUIC_IRQ_INT3_DNRES,
	177	MAX77843_MUIC_IRQ_INT3_MPNACK,
	178	MAX77843_MUIC_IRQ_INT3_MRXBUFOW,
	179	MAX77843_MUIC_IRQ_INT3_MRXTRF,
	180	MAX77843_MUIC_IRQ_INT3_MRXPERR,
	181	MAX77843_MUIC_IRQ_INT3_MRXRDY,
	182
	183	MAX77843_MUIC_IRQ_NUM,
	184	};
	185
	186	/* MAX77843 interrupts */
	187	#define MAX77843_SYS_IRQ_SYSUVLO_INT BIT(0)
	188	#define MAX77843_SYS_IRQ_SYSOVLO_INT BIT(1)
	189	#define MAX77843_SYS_IRQ_TSHDN_INT BIT(2)
	190	#define MAX77843_SYS_IRQ_TM_INT BIT(3)
	191
	192	/* MAX77843 MAINCTRL1 register */
	193	#define MAINCTRL1_BIASEN_SHIFT 7
	194	#define MAX77843_MAINCTRL1_BIASEN_MASK BIT(MAINCTRL1_BIASEN_SHIFT)
	195
	196	/* MAX77843 MCONFIG register */
	197	#define MCONFIG_MODE_SHIFT 7
	198	#define MCONFIG_MEN_SHIFT 6
	199	#define MCONFIG_PDIV_SHIFT 0
	200
	201	#define MAX77843_MCONFIG_MODE_MASK BIT(MCONFIG_MODE_SHIFT)
	202	#define MAX77843_MCONFIG_MEN_MASK BIT(MCONFIG_MEN_SHIFT)
	203	#define MAX77843_MCONFIG_PDIV_MASK (0x3 << MCONFIG_PDIV_SHIFT)
	204
	205	/* Max77843 charger insterrupts */
	206	#define MAX77843_CHG_BYP_I BIT(0)
	207	#define MAX77843_CHG_BATP_I BIT(2)
	208	#define MAX77843_CHG_BAT_I BIT(3)
	209	#define MAX77843_CHG_CHG_I BIT(4)
	210	#define MAX77843_CHG_WCIN_I BIT(5)
	211	#define MAX77843_CHG_CHGIN_I BIT(6)
	212	#define MAX77843_CHG_AICL_I BIT(7)
	213
	214	/* MAX77843 CHG_INT_OK register */
	215	#define MAX77843_CHG_BYP_OK BIT(0)
	216	#define MAX77843_CHG_BATP_OK BIT(2)
	217	#define MAX77843_CHG_BAT_OK BIT(3)
	218	#define MAX77843_CHG_CHG_OK BIT(4)
	219	#define MAX77843_CHG_WCIN_OK BIT(5)
	220	#define MAX77843_CHG_CHGIN_OK BIT(6)
	221	#define MAX77843_CHG_AICL_OK BIT(7)
	222
	223	/* MAX77843 CHG_DETAILS_00 register */
	224	#define MAX77843_CHG_BAT_DTLS BIT(0)
	225
	226	/* MAX77843 CHG_DETAILS_01 register */
	227	#define MAX77843_CHG_DTLS_MASK 0x0f
	228	#define MAX77843_CHG_PQ_MODE 0x00
	229	#define MAX77843_CHG_CC_MODE 0x01
	230	#define MAX77843_CHG_CV_MODE 0x02
	231	#define MAX77843_CHG_TO_MODE 0x03
	232	#define MAX77843_CHG_DO_MODE 0x04
	233	#define MAX77843_CHG_HT_MODE 0x05
	234	#define MAX77843_CHG_TF_MODE 0x06
	235	#define MAX77843_CHG_TS_MODE 0x07
	236	#define MAX77843_CHG_OFF_MODE 0x08
	237
	238	#define MAX77843_CHG_BAT_DTLS_MASK 0xf0
	239	#define MAX77843_CHG_NO_BAT (0x00 << 4)
	240	#define MAX77843_CHG_LOW_VOLT_BAT (0x01 << 4)
	241	#define MAX77843_CHG_LONG_BAT_TIME (0x02 << 4)
	242	#define MAX77843_CHG_OK_BAT (0x03 << 4)
	243	#define MAX77843_CHG_OK_LOW_VOLT_BAT (0x04 << 4)
	244	#define MAX77843_CHG_OVER_VOLT_BAT (0x05 << 4)
	245	#define MAX77843_CHG_OVER_CURRENT_BAT (0x06 << 4)
	246
	247	/* MAX77843 CHG_CNFG_00 register */
	248	#define MAX77843_CHG_DISABLE 0x00
	249	#define MAX77843_CHG_ENABLE 0x05
	250	#define MAX77843_CHG_MASK 0x01
	251	#define MAX77843_CHG_BUCK_MASK 0x04
	252
	253	/* MAX77843 CHG_CNFG_01 register */
	254	#define MAX77843_CHG_RESTART_THRESHOLD_100 0x00
	255	#define MAX77843_CHG_RESTART_THRESHOLD_150 0x10
	256	#define MAX77843_CHG_RESTART_THRESHOLD_200 0x20
	257	#define MAX77843_CHG_RESTART_THRESHOLD_DISABLE 0x30
	258
	259	/* MAX77843 CHG_CNFG_02 register */
	260	#define MAX77843_CHG_FAST_CHG_CURRENT_MIN 100000
	261	#define MAX77843_CHG_FAST_CHG_CURRENT_MAX 3150000
	262	#define MAX77843_CHG_FAST_CHG_CURRENT_STEP 50000
	263	#define MAX77843_CHG_FAST_CHG_CURRENT_MASK 0x3f
	264	#define MAX77843_CHG_OTG_ILIMIT_500 (0x00 << 6)
	265	#define MAX77843_CHG_OTG_ILIMIT_900 (0x01 << 6)
	266	#define MAX77843_CHG_OTG_ILIMIT_1200 (0x02 << 6)
	267	#define MAX77843_CHG_OTG_ILIMIT_1500 (0x03 << 6)
	268	#define MAX77843_CHG_OTG_ILIMIT_MASK 0xc0
	269
	270	/* MAX77843 CHG_CNFG_03 register */
	271	#define MAX77843_CHG_TOP_OFF_CURRENT_MIN 125000
	272	#define MAX77843_CHG_TOP_OFF_CURRENT_MAX 650000
	273	#define MAX77843_CHG_TOP_OFF_CURRENT_STEP 75000
	274	#define MAX77843_CHG_TOP_OFF_CURRENT_MASK 0x07
	275
	276	/* MAX77843 CHG_CNFG_06 register */
	277	#define MAX77843_CHG_WRITE_CAP_BLOCK 0x10
	278	#define MAX77843_CHG_WRITE_CAP_UNBLOCK 0x0C
	279
	280	/* MAX77843_CHG_CNFG_09_register */
	281	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MIN 100000
	282	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_MAX 4000000
	283	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_REF 3367000
	284	#define MAX77843_CHG_INPUT_CURRENT_LIMIT_STEP 33000
	285
	286	#define MAX77843_MUIC_ADC BIT(0)
	287	#define MAX77843_MUIC_ADCERROR BIT(2)
	288	#define MAX77843_MUIC_ADC1K BIT(3)
	289
	290	#define MAX77843_MUIC_CHGTYP BIT(0)
	291	#define MAX77843_MUIC_CHGDETRUN BIT(1)
	292	#define MAX77843_MUIC_DCDTMR BIT(2)
	293	#define MAX77843_MUIC_DXOVP BIT(3)
	294	#define MAX77843_MUIC_VBVOLT BIT(4)
	295
	296	#define MAX77843_MUIC_VBADC BIT(0)
	297	#define MAX77843_MUIC_VDNMON BIT(1)
	298	#define MAX77843_MUIC_DNRES BIT(2)
	299	#define MAX77843_MUIC_MPNACK BIT(3)
	300	#define MAX77843_MUIC_MRXBUFOW BIT(4)
	301	#define MAX77843_MUIC_MRXTRF BIT(5)
	302	#define MAX77843_MUIC_MRXPERR BIT(6)
	303	#define MAX77843_MUIC_MRXRDY BIT(7)
	304
	305	/* MAX77843 INTSRCMASK register */
	306	#define MAX77843_INTSRCMASK_CHGR 0
	307	#define MAX77843_INTSRCMASK_SYS 1
	308	#define MAX77843_INTSRCMASK_FG 2
	309	#define MAX77843_INTSRCMASK_MUIC 3
	310
	311	#define MAX77843_INTSRCMASK_CHGR_MASK BIT(MAX77843_INTSRCMASK_CHGR)
	312	#define MAX77843_INTSRCMASK_SYS_MASK BIT(MAX77843_INTSRCMASK_SYS)
	313	#define MAX77843_INTSRCMASK_FG_MASK BIT(MAX77843_INTSRCMASK_FG)
	314	#define MAX77843_INTSRCMASK_MUIC_MASK BIT(MAX77843_INTSRCMASK_MUIC)
	315
	316	#define MAX77843_INTSRC_MASK_MASK \
	317	(MAX77843_INTSRCMASK_MUIC_MASK \| MAX77843_INTSRCMASK_FG_MASK \| \
	318	MAX77843_INTSRCMASK_SYS_MASK \| MAX77843_INTSRCMASK_CHGR_MASK)
	319
	320	/* MAX77843 STATUS register*/
	321	#define STATUS1_ADC_SHIFT 0
	322	#define STATUS1_ADCERROR_SHIFT 6
	323	#define STATUS1_ADC1K_SHIFT 7
	324	#define STATUS2_CHGTYP_SHIFT 0
	325	#define STATUS2_CHGDETRUN_SHIFT 3
	326	#define STATUS2_DCDTMR_SHIFT 4
	327	#define STATUS2_DXOVP_SHIFT 5
	328	#define STATUS2_VBVOLT_SHIFT 6
	329	#define STATUS3_VBADC_SHIFT 0
	330	#define STATUS3_VDNMON_SHIFT 4
	331	#define STATUS3_DNRES_SHIFT 5
	332	#define STATUS3_MPNACK_SHIFT 6
	333
	334	#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
	335	#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(STATUS1_ADCERROR_SHIFT)
	336	#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(STATUS1_ADC1K_SHIFT)
	337	#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
	338	#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
	339	#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
	340	#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(STATUS2_DXOVP_SHIFT)
	341	#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
	342	#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT)
	343	#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(STATUS3_VDNMON_SHIFT)
	344	#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(STATUS3_DNRES_SHIFT)
	345	#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(STATUS3_MPNACK_SHIFT)
	346
	347	/* MAX77843 CONTROL register */
	348	#define CONTROL1_COMP1SW_SHIFT 0
	349	#define CONTROL1_COMP2SW_SHIFT 3
	350	#define CONTROL1_IDBEN_SHIFT 7
	351	#define CONTROL2_LOWPWR_SHIFT 0
	352	#define CONTROL2_ADCEN_SHIFT 1
	353	#define CONTROL2_CPEN_SHIFT 2
	354	#define CONTROL2_ACC_DET_SHIFT 5
	355	#define CONTROL2_USBCPINT_SHIFT 6
	356	#define CONTROL2_RCPS_SHIFT 7
	357	#define CONTROL3_JIGSET_SHIFT 0
	358	#define CONTROL4_ADCDBSET_SHIFT 0
	359	#define CONTROL4_USBAUTO_SHIFT 4
	360	#define CONTROL4_FCTAUTO_SHIFT 5
	361	#define CONTROL4_ADCMODE_SHIFT 6
	362
	363	#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << CONTROL1_COMP1SW_SHIFT)
	364	#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << CONTROL1_COMP2SW_SHIFT)
	365	#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(CONTROL1_IDBEN_SHIFT)
	366	#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(CONTROL2_LOWPWR_SHIFT)
	367	#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(CONTROL2_ADCEN_SHIFT)
	368	#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(CONTROL2_CPEN_SHIFT)
	369	#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(CONTROL2_ACC_DET_SHIFT)
	370	#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(CONTROL2_USBCPINT_SHIFT)
	371	#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(CONTROL2_RCPS_SHIFT)
	372	#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
	373	#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << CONTROL4_ADCDBSET_SHIFT)
	374	#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(CONTROL4_USBAUTO_SHIFT)
	375	#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(CONTROL4_FCTAUTO_SHIFT)
	376	#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << CONTROL4_ADCMODE_SHIFT)
	377
	378	/* MAX77843 switch port */
	379	#define COM_OPEN 0
	380	#define COM_USB 1
	381	#define COM_AUDIO 2
	382	#define COM_UART 3
	383	#define COM_AUX_USB 4
	384	#define COM_AUX_UART 5
	385
	386	#define CONTROL1_COM_SW \
	387	((MAX77843_MUIC_CONTROL1_COMP1SW_MASK \| \
	388	MAX77843_MUIC_CONTROL1_COMP2SW_MASK))
	389
	390	#define CONTROL1_SW_OPEN \
	391	((COM_OPEN << CONTROL1_COMP1SW_SHIFT \| \
	392	COM_OPEN << CONTROL1_COMP2SW_SHIFT))
	393	#define CONTROL1_SW_USB \
	394	((COM_USB << CONTROL1_COMP1SW_SHIFT \| \
	395	COM_USB << CONTROL1_COMP2SW_SHIFT))
	396	#define CONTROL1_SW_AUDIO \
	397	((COM_AUDIO << CONTROL1_COMP1SW_SHIFT \| \
	398	COM_AUDIO << CONTROL1_COMP2SW_SHIFT))
	399	#define CONTROL1_SW_UART \
	400	((COM_UART << CONTROL1_COMP1SW_SHIFT \| \
	401	COM_UART << CONTROL1_COMP2SW_SHIFT))
	402	#define CONTROL1_SW_AUX_USB \
	403	((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT \| \
	404	COM_AUX_USB << CONTROL1_COMP2SW_SHIFT))
	405	#define CONTROL1_SW_AUX_UART \
	406	((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT \| \
	407	COM_AUX_UART << CONTROL1_COMP2SW_SHIFT))
	408
	409	#define MAX77843_DISABLE 0
	410	#define MAX77843_ENABLE 1
	411
	412	#define CONTROL4_AUTO_DISABLE \
	413	((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) \| \
	414	(MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT))
	415	#define CONTROL4_AUTO_ENABLE \
	416	((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) \| \
	417	(MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT))
	418
	419	/* MAX77843 SAFEOUT LDO Control register */
	420	#define SAFEOUTCTRL_SAFEOUT1_SHIFT 0
	421	#define SAFEOUTCTRL_SAFEOUT2_SHIFT 2
	422	#define SAFEOUTCTRL_ENSAFEOUT1_SHIFT 6
	423	#define SAFEOUTCTRL_ENSAFEOUT2_SHIFT 7
	424
	425	#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT1 \
	426	BIT(SAFEOUTCTRL_ENSAFEOUT1_SHIFT)
	427	#define MAX77843_REG_SAFEOUTCTRL_ENSAFEOUT2 \
	428	BIT(SAFEOUTCTRL_ENSAFEOUT2_SHIFT)
	429	#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT1_MASK \
	430	(0x3 << SAFEOUTCTRL_SAFEOUT1_SHIFT)
	431	#define MAX77843_REG_SAFEOUTCTRL_SAFEOUT2_MASK \
	432	(0x3 << SAFEOUTCTRL_SAFEOUT2_SHIFT)
	433
	434	struct max77843 {
	435	struct device *dev;
	436
	437	struct i2c_client *i2c;
	438	struct i2c_client *i2c_chg;
	439	struct i2c_client *i2c_fuel;
	440	struct i2c_client *i2c_muic;
	441
	442	struct regmap *regmap;
	443	struct regmap *regmap_chg;
	444	struct regmap *regmap_fuel;
	445	struct regmap *regmap_muic;
	446
	447	struct regmap_irq_chip_data *irq_data;
	448	struct regmap_irq_chip_data *irq_data_chg;
	449	struct regmap_irq_chip_data *irq_data_fuel;
	450	struct regmap_irq_chip_data *irq_data_muic;
	451
	452	int irq;
	453	};
	454	#endif /* __MAX77843_H__ */