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-rw-r--r--include/linux/mfd/asic3.h185
1 files changed, 95 insertions, 90 deletions
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index 4ab2162db13b..322cd6deb9f0 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -8,7 +8,7 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 * 9 *
10 * Copyright 2001 Compaq Computer Corporation. 10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2007 OpendHand. 11 * Copyright 2007-2008 OpenedHand Ltd.
12 */ 12 */
13 13
14#ifndef __ASIC3_H__ 14#ifndef __ASIC3_H__
@@ -16,43 +16,22 @@
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19struct asic3 {
20 void __iomem *mapping;
21 unsigned int bus_shift;
22 unsigned int irq_nr;
23 unsigned int irq_base;
24 spinlock_t lock;
25 u16 irq_bothedge[4];
26 struct device *dev;
27};
28
29struct asic3_platform_data { 19struct asic3_platform_data {
30 struct { 20 u16 *gpio_config;
31 u32 dir; 21 unsigned int gpio_config_num;
32 u32 init;
33 u32 sleep_mask;
34 u32 sleep_out;
35 u32 batt_fault_out;
36 u32 sleep_conf;
37 u32 alt_function;
38 } gpio_a, gpio_b, gpio_c, gpio_d;
39
40 unsigned int bus_shift;
41 22
42 unsigned int irq_base; 23 unsigned int irq_base;
43 24
44 struct platform_device **children; 25 unsigned int gpio_base;
45 unsigned int n_children;
46}; 26};
47 27
48int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
49void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
50
51#define ASIC3_NUM_GPIO_BANKS 4 28#define ASIC3_NUM_GPIO_BANKS 4
52#define ASIC3_GPIOS_PER_BANK 16 29#define ASIC3_GPIOS_PER_BANK 16
53#define ASIC3_NUM_GPIOS 64 30#define ASIC3_NUM_GPIOS 64
54#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 31#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
55 32
33#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
34
56#define ASIC3_GPIO_BANK_A 0 35#define ASIC3_GPIO_BANK_A 0
57#define ASIC3_GPIO_BANK_B 1 36#define ASIC3_GPIO_BANK_B 1
58#define ASIC3_GPIO_BANK_C 2 37#define ASIC3_GPIO_BANK_C 2
@@ -64,32 +43,89 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
64/* All offsets below are specified with this address bus shift */ 43/* All offsets below are specified with this address bus shift */
65#define ASIC3_DEFAULT_ADDR_SHIFT 2 44#define ASIC3_DEFAULT_ADDR_SHIFT 2
66 45
67#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg) 46#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
68#define ASIC3_GPIO_OFFSET(base, reg) \ 47#define ASIC3_GPIO_OFFSET(base, reg) \
69 (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg) 48 (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
70 49
71#define ASIC3_GPIO_A_Base 0x0000 50#define ASIC3_GPIO_A_BASE 0x0000
72#define ASIC3_GPIO_B_Base 0x0100 51#define ASIC3_GPIO_B_BASE 0x0100
73#define ASIC3_GPIO_C_Base 0x0200 52#define ASIC3_GPIO_C_BASE 0x0200
74#define ASIC3_GPIO_D_Base 0x0300 53#define ASIC3_GPIO_D_BASE 0x0300
75 54
76#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */ 55#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
77#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */ 56#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
78#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */ 57 (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
79#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */ 58#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
80#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */ 59#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
81#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */ 60#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
82#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */ 61
83#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */ 62#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
84#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */ 63#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
85#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */ 64#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
86#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */ 65#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
87#define ASIC3_GPIO_SleepConf 0x2c /* 66#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
67#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
68#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
69#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
70#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
71#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
72#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
73#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
88 * R/W bit 1: autosleep 74 * R/W bit 1: autosleep
89 * 0: disable gposlpout in normal mode, 75 * 0: disable gposlpout in normal mode,
90 * enable gposlpout in sleep mode. 76 * enable gposlpout in sleep mode.
91 */ 77 */
92#define ASIC3_GPIO_Status 0x30 /* R Pin status */ 78#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
79
80/*
81 * ASIC3 GPIO config
82 *
83 * Bits 0..6 gpio number
84 * Bits 7..13 Alternate function
85 * Bit 14 Direction
86 * Bit 15 Initial value
87 *
88 */
89#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
90#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
91#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
92#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
93#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
94 | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
95 | (((init) & 0x1) << 15))
96#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
97 ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
98#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
99 ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
100
101/*
102 * Alternate functions
103 */
104#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
105#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
106#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
107#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
108#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
109#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
110#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
111#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
112#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
113#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
114#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
115#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
116#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
117#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
118#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
119#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
120#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
121#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
122#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
123#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
124#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
125#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
126#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
127#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
128
93 129
94#define ASIC3_SPI_Base 0x0400 130#define ASIC3_SPI_Base 0x0400
95#define ASIC3_SPI_Control 0x0000 131#define ASIC3_SPI_Control 0x0000
@@ -128,7 +164,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
128#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ 164#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
129#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ 165#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
130 166
131#define ASIC3_CLOCK_Base 0x0A00 167#define ASIC3_CLOCK_BASE 0x0A00
132#define ASIC3_CLOCK_CDEX 0x00 168#define ASIC3_CLOCK_CDEX 0x00
133#define ASIC3_CLOCK_SEL 0x04 169#define ASIC3_CLOCK_SEL 0x04
134 170
@@ -159,12 +195,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
159#define CLOCK_SEL_CX (1 << 2) 195#define CLOCK_SEL_CX (1 << 2)
160 196
161 197
162#define ASIC3_INTR_Base 0x0B00 198#define ASIC3_INTR_BASE 0x0B00
163 199
164#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */ 200#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
165#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */ 201#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
166#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */ 202#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
167#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */ 203#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
168 204
169#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ 205#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
170#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ 206#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
@@ -227,44 +263,12 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
227#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ 263#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
228 264
229/********************************************* 265/*********************************************
230 * The Onewire interface registers 266 * The Onewire interface (DS1WM) is handled
231 * 267 * by the ds1wm driver.
232 * OWM_CMD
233 * OWM_DAT
234 * OWM_INTR
235 * OWM_INTEN
236 * OWM_CLKDIV
237 * 268 *
238 *********************************************/ 269 *********************************************/
239 270
240#define ASIC3_OWM_Base 0xC00 271#define ASIC3_OWM_BASE 0xC00
241
242#define ASIC3_OWM_CMD 0x00
243#define ASIC3_OWM_DAT 0x04
244#define ASIC3_OWM_INTR 0x08
245#define ASIC3_OWM_INTEN 0x0C
246#define ASIC3_OWM_CLKDIV 0x10
247
248#define ASIC3_OWM_CMD_ONEWR (1 << 0)
249#define ASIC3_OWM_CMD_SRA (1 << 1)
250#define ASIC3_OWM_CMD_DQO (1 << 2)
251#define ASIC3_OWM_CMD_DQI (1 << 3)
252
253#define ASIC3_OWM_INTR_PD (1 << 0)
254#define ASIC3_OWM_INTR_PDR (1 << 1)
255#define ASIC3_OWM_INTR_TBE (1 << 2)
256#define ASIC3_OWM_INTR_TEMP (1 << 3)
257#define ASIC3_OWM_INTR_RBF (1 << 4)
258
259#define ASIC3_OWM_INTEN_EPD (1 << 0)
260#define ASIC3_OWM_INTEN_IAS (1 << 1)
261#define ASIC3_OWM_INTEN_ETBE (1 << 2)
262#define ASIC3_OWM_INTEN_ETMT (1 << 3)
263#define ASIC3_OWM_INTEN_ERBF (1 << 4)
264
265#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
266#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
267
268 272
269/***************************************************************************** 273/*****************************************************************************
270 * The SD configuration registers are at a completely different location 274 * The SD configuration registers are at a completely different location
@@ -492,6 +496,7 @@ void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
492#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C 496#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
493#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0 497#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
494 498
495#define ASIC3_MAP_SIZE 0x2000 499#define ASIC3_MAP_SIZE_32BIT 0x2000
500#define ASIC3_MAP_SIZE_16BIT 0x1000
496 501
497#endif /* __ASIC3_H__ */ 502#endif /* __ASIC3_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 20:07:09 -0500