2 files changed, 44 insertions, 2 deletions

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 1e8b0cf30792..800544bc7bfd 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -33,6 +33,7 @@
 #define GICD_SETSPI_SR                  0x0050
 #define GICD_CLRSPI_SR                  0x0058
 #define GICD_SEIR                       0x0068
+#define GICD_IGROUPR                    0x0080
 #define GICD_ISENABLER                  0x0100
 #define GICD_ICENABLER                  0x0180
 #define GICD_ISPENDR                    0x0200
@@ -41,14 +42,37 @@
 #define GICD_ICACTIVER                  0x0380
 #define GICD_IPRIORITYR                 0x0400
 #define GICD_ICFGR                      0x0C00
+#define GICD_IGRPMODR                   0x0D00
+#define GICD_NSACR                      0x0E00
 #define GICD_IROUTER                    0x6000
+#define GICD_IDREGS                     0xFFD0
 #define GICD_PIDR2                      0xFFE8
 
+/*
+ * Those registers are actually from GICv2, but the spec demands that they
+ * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
+ */
+#define GICD_ITARGETSR                  0x0800
+#define GICD_SGIR                       0x0F00
+#define GICD_CPENDSGIR                  0x0F10
+#define GICD_SPENDSGIR                  0x0F20
+
 #define GICD_CTLR_RWP                   (1U << 31)
+#define GICD_CTLR_DS                    (1U << 6)
 #define GICD_CTLR_ARE_NS                (1U << 4)
 #define GICD_CTLR_ENABLE_G1A            (1U << 1)
 #define GICD_CTLR_ENABLE_G1             (1U << 0)
 
+/*
+ * In systems with a single security state (what we emulate in KVM)
+ * the meaning of the interrupt group enable bits is slightly different
+ */
+#define GICD_CTLR_ENABLE_SS_G1          (1U << 1)
+#define GICD_CTLR_ENABLE_SS_G0          (1U << 0)
+
+#define GICD_TYPER_LPIS                 (1U << 17)
+#define GICD_TYPER_MBIS                 (1U << 16)
+
 #define GICD_TYPER_ID_BITS(typer)       ((((typer) >> 19) & 0x1f) + 1)
 #define GICD_TYPER_IRQS(typer)          ((((typer) & 0x1f) + 1) * 32)
 #define GICD_TYPER_LPIS                 (1U << 17)
@@ -60,6 +84,8 @@
 #define GIC_PIDR2_ARCH_GICv3            0x30
 #define GIC_PIDR2_ARCH_GICv4            0x40
 
+#define GIC_V3_DIST_SIZE                0x10000
+
 /*
  * Re-Distributor registers, offsets from RD_base
  */
@@ -78,6 +104,7 @@
 #define GICR_SYNCR                      0x00C0
 #define GICR_MOVLPIR                    0x0100
 #define GICR_MOVALLR                    0x0110
+#define GICR_IDREGS                     GICD_IDREGS
 #define GICR_PIDR2                      GICD_PIDR2
 
 #define GICR_CTLR_ENABLE_LPIS           (1UL << 0)
@@ -104,6 +131,7 @@
 /*
  * Re-Distributor registers, offsets from SGI_base
  */
+#define GICR_IGROUPR0                   GICD_IGROUPR
 #define GICR_ISENABLER0                 GICD_ISENABLER
 #define GICR_ICENABLER0                 GICD_ICENABLER
 #define GICR_ISPENDR0                   GICD_ISPENDR
@@ -112,11 +140,15 @@
 #define GICR_ICACTIVER0                 GICD_ICACTIVER
 #define GICR_IPRIORITYR0                GICD_IPRIORITYR
 #define GICR_ICFGR0                     GICD_ICFGR
+#define GICR_IGRPMODR0                  GICD_IGRPMODR
+#define GICR_NSACR                      GICD_NSACR
 
 #define GICR_TYPER_PLPIS                (1U << 0)
 #define GICR_TYPER_VLPIS                (1U << 1)
 #define GICR_TYPER_LAST                 (1U << 4)
 
+#define GIC_V3_REDIST_SIZE              0x20000
+
 #define LPI_PROP_GROUP1                 (1 << 1)
 #define LPI_PROP_ENABLED                (1 << 0)
 
@@ -248,6 +280,18 @@
 #define ICC_SRE_EL2_SRE                 (1 << 0)
 #define ICC_SRE_EL2_ENABLE              (1 << 3)
 
+#define ICC_SGI1R_TARGET_LIST_SHIFT     0
+#define ICC_SGI1R_TARGET_LIST_MASK      (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
+#define ICC_SGI1R_AFFINITY_1_SHIFT      16
+#define ICC_SGI1R_AFFINITY_1_MASK       (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
+#define ICC_SGI1R_SGI_ID_SHIFT          24
+#define ICC_SGI1R_SGI_ID_MASK           (0xff << ICC_SGI1R_SGI_ID_SHIFT)
+#define ICC_SGI1R_AFFINITY_2_SHIFT      32
+#define ICC_SGI1R_AFFINITY_2_MASK       (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
+#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT  40
+#define ICC_SGI1R_AFFINITY_3_SHIFT      48
+#define ICC_SGI1R_AFFINITY_3_MASK       (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
+
 /*
  * System register definitions
  */
diff --git a/include/linux/irqchip/irq-omap-intc.h b/include/linux/irqchip/irq-omap-intc.h
index e06b370cfc0d..2e3d1afeb674 100644
--- a/include/linux/irqchip/irq-omap-intc.h
+++ b/include/linux/irqchip/irq-omap-intc.h
@@ -18,9 +18,7 @@
 #ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_OMAP_INTC_H
 #define __INCLUDE_LINUX_IRQCHIP_IRQ_OMAP_INTC_H
 
-void omap2_init_irq(void);
 void omap3_init_irq(void);
-void ti81xx_init_irq(void);
 
 int omap_irq_pending(void);
 void omap_intc_save_context(void);