1 files changed, 53 insertions, 12 deletions

diff --git a/include/linux/irq.h b/include/linux/irq.h
index 03f48d936f66..d09ec7a1243e 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -15,11 +15,13 @@
 #include <linux/spinlock.h>
 #include <linux/cpumask.h>
 #include <linux/gfp.h>
+#include <linux/irqhandler.h>
 #include <linux/irqreturn.h>
 #include <linux/irqnr.h>
 #include <linux/errno.h>
 #include <linux/topology.h>
 #include <linux/wait.h>
+#include <linux/io.h>
 
 #include <asm/irq.h>
 #include <asm/ptrace.h>
@@ -27,11 +29,7 @@
 
 struct seq_file;
 struct module;
-struct irq_desc;
-struct irq_data;
-typedef void (*irq_flow_handler_t)(unsigned int irq,
-                                            struct irq_desc *desc);
-typedef void (*irq_preflow_handler_t)(struct irq_data *data);
+struct msi_msg;
 
 /*
  * IRQ line status.
@@ -113,10 +111,14 @@ enum {
  *
  * IRQ_SET_MASK_OK      - OK, core updates irq_data.affinity
  * IRQ_SET_MASK_NOCPY   - OK, chip did update irq_data.affinity
+ * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
+ *                        support stacked irqchips, which indicates skipping
+ *                        all descendent irqchips.
  */
 enum {
         IRQ_SET_MASK_OK = 0,
         IRQ_SET_MASK_OK_NOCOPY,
+        IRQ_SET_MASK_OK_DONE,
 };
 
 struct msi_desc;
@@ -133,6 +135,8 @@ struct irq_domain;
  * @chip:               low level interrupt hardware access
  * @domain:             Interrupt translation domain; responsible for mapping
  *                      between hwirq number and linux irq number.
+ * @parent_data:        pointer to parent struct irq_data to support hierarchy
+ *                      irq_domain
  * @handler_data:       per-IRQ data for the irq_chip methods
  * @chip_data:          platform-specific per-chip private data for the chip
  *                      methods, to allow shared chip implementations
@@ -151,6 +155,9 @@ struct irq_data {
         unsigned int            state_use_accessors;
         struct irq_chip         *chip;
         struct irq_domain       *domain;
+#ifdef  CONFIG_IRQ_DOMAIN_HIERARCHY
+        struct irq_data         *parent_data;
+#endif
         void                    *handler_data;
         void                    *chip_data;
         struct msi_desc         *msi_desc;
@@ -315,6 +322,8 @@ static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
  *                              any other callback related to this irq
  * @irq_release_resources:      optional to release resources acquired with
  *                              irq_request_resources
+ * @irq_compose_msi_msg:        optional to compose message content for MSI
+ * @irq_write_msi_msg:  optional to write message content for MSI
  * @flags:              chip specific flags
  */
 struct irq_chip {
@@ -351,6 +360,9 @@ struct irq_chip {
         int             (*irq_request_resources)(struct irq_data *data);
         void            (*irq_release_resources)(struct irq_data *data);
 
+        void            (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
+        void            (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
+
         unsigned long   flags;
 };
 
@@ -438,6 +450,18 @@ extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
 extern void handle_nested_irq(unsigned int irq);
 
+extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
+#ifdef  CONFIG_IRQ_DOMAIN_HIERARCHY
+extern void irq_chip_ack_parent(struct irq_data *data);
+extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
+extern void irq_chip_mask_parent(struct irq_data *data);
+extern void irq_chip_unmask_parent(struct irq_data *data);
+extern void irq_chip_eoi_parent(struct irq_data *data);
+extern int irq_chip_set_affinity_parent(struct irq_data *data,
+                                        const struct cpumask *dest,
+                                        bool force);
+#endif
+
 /* Handling of unhandled and spurious interrupts: */
 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
                            irqreturn_t action_ret);
@@ -639,13 +663,6 @@ void arch_teardown_hwirq(unsigned int irq);
 void irq_init_desc(unsigned int irq);
 #endif
 
-#ifndef irq_reg_writel
-# define irq_reg_writel(val, addr)      writel(val, addr)
-#endif
-#ifndef irq_reg_readl
-# define irq_reg_readl(addr)            readl(addr)
-#endif
-
 /**
  * struct irq_chip_regs - register offsets for struct irq_gci
  * @enable:     Enable register offset to reg_base
@@ -692,6 +709,8 @@ struct irq_chip_type {
  * struct irq_chip_generic - Generic irq chip data structure
  * @lock:               Lock to protect register and cache data access
  * @reg_base:           Register base address (virtual)
+ * @reg_readl:          Alternate I/O accessor (defaults to readl if NULL)
+ * @reg_writel:         Alternate I/O accessor (defaults to writel if NULL)
  * @irq_base:           Interrupt base nr for this chip
  * @irq_cnt:            Number of interrupts handled by this chip
  * @mask_cache:         Cached mask register shared between all chip types
@@ -716,6 +735,8 @@ struct irq_chip_type {
 struct irq_chip_generic {
         raw_spinlock_t          lock;
         void __iomem            *reg_base;
+        u32                     (*reg_readl)(void __iomem *addr);
+        void                    (*reg_writel)(u32 val, void __iomem *addr);
         unsigned int            irq_base;
         unsigned int            irq_cnt;
         u32                     mask_cache;
@@ -740,12 +761,14 @@ struct irq_chip_generic {
  *                              the parent irq. Usually GPIO implementations
  * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
  * @IRQ_GC_NO_MASK:             Do not calculate irq_data->mask
+ * @IRQ_GC_BE_IO:               Use big-endian register accesses (default: LE)
  */
 enum irq_gc_flags {
         IRQ_GC_INIT_MASK_CACHE          = 1 << 0,
         IRQ_GC_INIT_NESTED_LOCK         = 1 << 1,
         IRQ_GC_MASK_CACHE_PER_TYPE      = 1 << 2,
         IRQ_GC_NO_MASK                  = 1 << 3,
+        IRQ_GC_BE_IO                    = 1 << 4,
 };
 
 /*
@@ -821,4 +844,22 @@ static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
 #endif
 
+static inline void irq_reg_writel(struct irq_chip_generic *gc,
+                                  u32 val, int reg_offset)
+{
+        if (gc->reg_writel)
+                gc->reg_writel(val, gc->reg_base + reg_offset);
+        else
+                writel(val, gc->reg_base + reg_offset);
+}
+
+static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
+                                int reg_offset)
+{
+        if (gc->reg_readl)
+                return gc->reg_readl(gc->reg_base + reg_offset);
+        else
+                return readl(gc->reg_base + reg_offset);
+}
+
 #endif /* _LINUX_IRQ_H */