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Diffstat (limited to 'include/linux/intel-iommu.h')
-rw-r--r--include/linux/intel-iommu.h25
1 files changed, 1 insertions, 24 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 3d017cfd245b..c4f6c101dbcd 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -23,8 +23,6 @@
23#define _INTEL_IOMMU_H_ 23#define _INTEL_IOMMU_H_
24 24
25#include <linux/types.h> 25#include <linux/types.h>
26#include <linux/msi.h>
27#include <linux/sysdev.h>
28#include <linux/iova.h> 26#include <linux/iova.h>
29#include <linux/io.h> 27#include <linux/io.h>
30#include <linux/dma_remapping.h> 28#include <linux/dma_remapping.h>
@@ -289,10 +287,10 @@ struct intel_iommu {
289 void __iomem *reg; /* Pointer to hardware regs, virtual addr */ 287 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
290 u64 cap; 288 u64 cap;
291 u64 ecap; 289 u64 ecap;
292 int seg;
293 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ 290 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
294 spinlock_t register_lock; /* protect register handling */ 291 spinlock_t register_lock; /* protect register handling */
295 int seq_id; /* sequence id of the iommu */ 292 int seq_id; /* sequence id of the iommu */
293 int agaw; /* agaw of this iommu */
296 294
297#ifdef CONFIG_DMAR 295#ifdef CONFIG_DMAR
298 unsigned long *domain_ids; /* bitmap of domains */ 296 unsigned long *domain_ids; /* bitmap of domains */
@@ -302,8 +300,6 @@ struct intel_iommu {
302 300
303 unsigned int irq; 301 unsigned int irq;
304 unsigned char name[7]; /* Device Name */ 302 unsigned char name[7]; /* Device Name */
305 struct msi_msg saved_msg;
306 struct sys_device sysdev;
307 struct iommu_flush flush; 303 struct iommu_flush flush;
308#endif 304#endif
309 struct q_inval *qi; /* Queued invalidation info */ 305 struct q_inval *qi; /* Queued invalidation info */
@@ -334,25 +330,6 @@ extern int qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
334 330
335extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu); 331extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
336 332
337void intel_iommu_domain_exit(struct dmar_domain *domain);
338struct dmar_domain *intel_iommu_domain_alloc(struct pci_dev *pdev);
339int intel_iommu_context_mapping(struct dmar_domain *domain,
340 struct pci_dev *pdev);
341int intel_iommu_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
342 u64 hpa, size_t size, int prot);
343void intel_iommu_detach_dev(struct dmar_domain *domain, u8 bus, u8 devfn);
344struct dmar_domain *intel_iommu_find_domain(struct pci_dev *pdev);
345u64 intel_iommu_iova_to_pfn(struct dmar_domain *domain, u64 iova);
346
347#ifdef CONFIG_DMAR
348int intel_iommu_found(void);
349#else /* CONFIG_DMAR */
350static inline int intel_iommu_found(void)
351{
352 return 0;
353}
354#endif /* CONFIG_DMAR */
355
356extern void *intel_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t); 333extern void *intel_alloc_coherent(struct device *, size_t, dma_addr_t *, gfp_t);
357extern void intel_free_coherent(struct device *, size_t, void *, dma_addr_t); 334extern void intel_free_coherent(struct device *, size_t, void *, dma_addr_t);
358extern dma_addr_t intel_map_single(struct device *, phys_addr_t, size_t, int); 335extern dma_addr_t intel_map_single(struct device *, phys_addr_t, size_t, int);