litmus-rt.git - The LITMUS^RT kernel.

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Diffstat (limited to 'include/linux/fault-inject.h')

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/* * Initio A100 device driver for Linux. * * Copyright (c) 1994-1998 Initio Corporation * All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, write to * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * Revision History: * 06/18/98 HL, Initial production Version 1.02 * 12/19/98 bv, Use spinlocks for 2.1.95 and up * 06/25/02 Doug Ledford <dledford@redhat.com> * - This and the i60uscsi.h file are almost identical, * merged them into a single header used by both .c files. * 14/06/07 Alan Cox <alan@redhat.com> * - Grand cleanup and Linuxisation */ #define inia100_REVID "Initio INI-A100U2W SCSI device driver; Revision: 1.02d" #if 1 #define ORC_MAXQUEUE 245 #define ORC_MAXTAGS 64 #else #define ORC_MAXQUEUE 25 #define ORC_MAXTAGS 8 #endif #define TOTAL_SG_ENTRY 32 #define MAX_TARGETS 16 #define IMAX_CDB 15 #define SENSE_SIZE 14 /************************************************************************/ /* Scatter-Gather Element Structure */ /************************************************************************/ struct orc_sgent { u32 base; /* Data Pointer */ u32 length; /* Data Length */ }; /* SCSI related definition */ #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */ #define DISC_ALLOW 0xC0 /* Disconnect is allowed */ #define ORC_OFFSET_SCB 16 #define ORC_MAX_SCBS 250 #define MAX_CHANNELS 2 #define MAX_ESCB_ELE 64 #define TCF_DRV_255_63 0x0400 /********************************************************/ /* Orchid Host Command Set */ /********************************************************/ #define ORC_CMD_NOP 0x00 /* Host command - NOP */ #define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */ #define ORC_CMD_ECHO 0x02 /* Host command - ECHO */ #define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */ #define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */ #define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */ #define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */ #define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */ /********************************************************/ /* Orchid Register Set */ /********************************************************/ #define ORC_GINTS 0xA0 /* Global Interrupt Status */ #define QINT 0x04 /* Reply Queue Interrupt */ #define ORC_GIMSK 0xA1 /* Global Interrupt MASK */ #define MQINT 0x04 /* Mask Reply Queue Interrupt */ #define ORC_GCFG 0xA2 /* Global Configure */ #define EEPRG 0x01 /* Enable EEPROM programming */ #define ORC_GSTAT 0xA3 /* Global status */ #define WIDEBUS 0x10 /* Wide SCSI Devices connected */ #define ORC_HDATA 0xA4 /* Host Data */ #define ORC_HCTRL 0xA5 /* Host Control */ #define SCSIRST 0x80 /* SCSI bus reset */ #define HDO 0x40 /* Host data out */ #define HOSTSTOP 0x02 /* Host stop RISC engine */ #define DEVRST 0x01 /* Device reset */ #define ORC_HSTUS 0xA6 /* Host Status */ #define HDI 0x02 /* Host data in */ #define RREADY 0x01 /* RISC engine is ready to receive */ #define ORC_NVRAM 0xA7 /* Nvram port address */ #define SE2CS 0x008 #define SE2CLK 0x004 #define SE2DO 0x002 #define SE2DI 0x001 #define ORC_PQUEUE 0xA8 /* Posting queue FIFO */ #define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */ #define ORC_RQUEUE 0xAA /* Reply queue FIFO */ #define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */ #define ORC_FWBASEADR 0xAC /* Firmware base address */ #define ORC_EBIOSADR0 0xB0 /* External Bios address */ #define ORC_EBIOSADR1 0xB1 /* External Bios address */ #define ORC_EBIOSADR2 0xB2 /* External Bios address */ #define ORC_EBIOSDATA 0xB3 /* External Bios address */ #define ORC_SCBSIZE 0xB7 /* SCB size register */ #define ORC_SCBBASE0 0xB8 /* SCB base address 0 */ #define ORC_SCBBASE1 0xBC /* SCB base address 1 */ #define ORC_RISCCTL 0xE0 /* RISC Control */ #define PRGMRST 0x002 #define DOWNLOAD 0x001


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