aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/dmaengine.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/dmaengine.h')
-rw-r--r--include/linux/dmaengine.h37
1 files changed, 28 insertions, 9 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index f0413845f20e..2e2aa3df170c 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -23,9 +23,6 @@
23 23
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/uio.h> 25#include <linux/uio.h>
26#include <linux/kref.h>
27#include <linux/completion.h>
28#include <linux/rcupdate.h>
29#include <linux/dma-mapping.h> 26#include <linux/dma-mapping.h>
30 27
31/** 28/**
@@ -97,7 +94,6 @@ typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
97 94
98/** 95/**
99 * struct dma_chan_percpu - the per-CPU part of struct dma_chan 96 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
100 * @refcount: local_t used for open-coded "bigref" counting
101 * @memcpy_count: transaction counter 97 * @memcpy_count: transaction counter
102 * @bytes_transferred: byte counter 98 * @bytes_transferred: byte counter
103 */ 99 */
@@ -114,9 +110,6 @@ struct dma_chan_percpu {
114 * @cookie: last cookie value returned to client 110 * @cookie: last cookie value returned to client
115 * @chan_id: channel ID for sysfs 111 * @chan_id: channel ID for sysfs
116 * @dev: class device for sysfs 112 * @dev: class device for sysfs
117 * @refcount: kref, used in "bigref" slow-mode
118 * @slow_ref: indicates that the DMA channel is free
119 * @rcu: the DMA channel's RCU head
120 * @device_node: used to add this to the device chan list 113 * @device_node: used to add this to the device chan list
121 * @local: per-cpu pointer to a struct dma_chan_percpu 114 * @local: per-cpu pointer to a struct dma_chan_percpu
122 * @client-count: how many clients are using this channel 115 * @client-count: how many clients are using this channel
@@ -209,12 +202,11 @@ struct dma_async_tx_descriptor {
209/** 202/**
210 * struct dma_device - info on the entity supplying DMA services 203 * struct dma_device - info on the entity supplying DMA services
211 * @chancnt: how many DMA channels are supported 204 * @chancnt: how many DMA channels are supported
205 * @privatecnt: how many DMA channels are requested by dma_request_channel
212 * @channels: the list of struct dma_chan 206 * @channels: the list of struct dma_chan
213 * @global_node: list_head for global dma_device_list 207 * @global_node: list_head for global dma_device_list
214 * @cap_mask: one or more dma_capability flags 208 * @cap_mask: one or more dma_capability flags
215 * @max_xor: maximum number of xor sources, 0 if no capability 209 * @max_xor: maximum number of xor sources, 0 if no capability
216 * @refcount: reference count
217 * @done: IO completion struct
218 * @dev_id: unique device ID 210 * @dev_id: unique device ID
219 * @dev: struct device reference for dma mapping api 211 * @dev: struct device reference for dma mapping api
220 * @device_alloc_chan_resources: allocate resources and return the 212 * @device_alloc_chan_resources: allocate resources and return the
@@ -227,11 +219,13 @@ struct dma_async_tx_descriptor {
227 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation 219 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
228 * @device_prep_slave_sg: prepares a slave dma operation 220 * @device_prep_slave_sg: prepares a slave dma operation
229 * @device_terminate_all: terminate all pending operations 221 * @device_terminate_all: terminate all pending operations
222 * @device_is_tx_complete: poll for transaction completion
230 * @device_issue_pending: push pending transactions to hardware 223 * @device_issue_pending: push pending transactions to hardware
231 */ 224 */
232struct dma_device { 225struct dma_device {
233 226
234 unsigned int chancnt; 227 unsigned int chancnt;
228 unsigned int privatecnt;
235 struct list_head channels; 229 struct list_head channels;
236 struct list_head global_node; 230 struct list_head global_node;
237 dma_cap_mask_t cap_mask; 231 dma_cap_mask_t cap_mask;
@@ -296,6 +290,24 @@ static inline void net_dmaengine_put(void)
296} 290}
297#endif 291#endif
298 292
293#ifdef CONFIG_ASYNC_TX_DMA
294#define async_dmaengine_get() dmaengine_get()
295#define async_dmaengine_put() dmaengine_put()
296#define async_dma_find_channel(type) dma_find_channel(type)
297#else
298static inline void async_dmaengine_get(void)
299{
300}
301static inline void async_dmaengine_put(void)
302{
303}
304static inline struct dma_chan *
305async_dma_find_channel(enum dma_transaction_type type)
306{
307 return NULL;
308}
309#endif
310
299dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan, 311dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
300 void *dest, void *src, size_t len); 312 void *dest, void *src, size_t len);
301dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan, 313dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
@@ -342,6 +354,13 @@ __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
342 set_bit(tx_type, dstp->bits); 354 set_bit(tx_type, dstp->bits);
343} 355}
344 356
357#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
358static inline void
359__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
360{
361 clear_bit(tx_type, dstp->bits);
362}
363
345#define dma_cap_zero(mask) __dma_cap_zero(&(mask)) 364#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
346static inline void __dma_cap_zero(dma_cap_mask_t *dstp) 365static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
347{ 366{