aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/can
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/can')
-rw-r--r--include/linux/can/dev.h1
-rw-r--r--include/linux/can/platform/mcp251x.h4
-rw-r--r--include/linux/can/platform/sja1000.h2
3 files changed, 4 insertions, 3 deletions
diff --git a/include/linux/can/dev.h b/include/linux/can/dev.h
index 6e5a7f00223d..cc0bb4961669 100644
--- a/include/linux/can/dev.h
+++ b/include/linux/can/dev.h
@@ -14,6 +14,7 @@
14#ifndef CAN_DEV_H 14#ifndef CAN_DEV_H
15#define CAN_DEV_H 15#define CAN_DEV_H
16 16
17#include <linux/can.h>
17#include <linux/can/netlink.h> 18#include <linux/can/netlink.h>
18#include <linux/can/error.h> 19#include <linux/can/error.h>
19 20
diff --git a/include/linux/can/platform/mcp251x.h b/include/linux/can/platform/mcp251x.h
index 1448177d86d5..dba28268e651 100644
--- a/include/linux/can/platform/mcp251x.h
+++ b/include/linux/can/platform/mcp251x.h
@@ -26,8 +26,8 @@
26struct mcp251x_platform_data { 26struct mcp251x_platform_data {
27 unsigned long oscillator_frequency; 27 unsigned long oscillator_frequency;
28 int model; 28 int model;
29#define CAN_MCP251X_MCP2510 0 29#define CAN_MCP251X_MCP2510 0x2510
30#define CAN_MCP251X_MCP2515 1 30#define CAN_MCP251X_MCP2515 0x2515
31 int (*board_specific_setup)(struct spi_device *spi); 31 int (*board_specific_setup)(struct spi_device *spi);
32 int (*transceiver_enable)(int enable); 32 int (*transceiver_enable)(int enable);
33 int (*power_enable) (int enable); 33 int (*power_enable) (int enable);
diff --git a/include/linux/can/platform/sja1000.h b/include/linux/can/platform/sja1000.h
index 01ee2aeb048d..96f8fcc78d78 100644
--- a/include/linux/can/platform/sja1000.h
+++ b/include/linux/can/platform/sja1000.h
@@ -26,7 +26,7 @@
26#define OCR_TX_SHIFT 2 26#define OCR_TX_SHIFT 2
27 27
28struct sja1000_platform_data { 28struct sja1000_platform_data {
29 u32 clock; /* CAN bus oscillator frequency in Hz */ 29 u32 osc_freq; /* CAN bus oscillator frequency in Hz */
30 30
31 u8 ocr; /* output control register */ 31 u8 ocr; /* output control register */
32 u8 cdr; /* clock divider register */ 32 u8 cdr; /* clock divider register */