diff options
Diffstat (limited to 'include/linux/bcma/bcma_driver_chipcommon.h')
-rw-r--r-- | include/linux/bcma/bcma_driver_chipcommon.h | 88 |
1 files changed, 87 insertions, 1 deletions
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h index 8bbfe31fbac8..3c80885fa829 100644 --- a/include/linux/bcma/bcma_driver_chipcommon.h +++ b/include/linux/bcma/bcma_driver_chipcommon.h | |||
@@ -24,7 +24,7 @@ | |||
24 | #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ | 24 | #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ |
25 | #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ | 25 | #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ |
26 | #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ | 26 | #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ |
27 | #define BCMA_CC_FLASHT_NFLASH 0x00000200 | 27 | #define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */ |
28 | #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ | 28 | #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ |
29 | #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ | 29 | #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ |
30 | #define BCMA_PLLTYPE_NONE 0x00000000 | 30 | #define BCMA_PLLTYPE_NONE 0x00000000 |
@@ -45,6 +45,7 @@ | |||
45 | #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ | 45 | #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ |
46 | #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ | 46 | #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ |
47 | #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ | 47 | #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ |
48 | #define BCMA_CC_CAP_NFLASH 0x80000000 /* NAND flash present (rev >= 35 or BCM4706?) */ | ||
48 | #define BCMA_CC_CORECTL 0x0008 | 49 | #define BCMA_CC_CORECTL 0x0008 |
49 | #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ | 50 | #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ |
50 | #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | 51 | #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ |
@@ -88,6 +89,11 @@ | |||
88 | #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 | 89 | #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 |
89 | #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 | 90 | #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 |
90 | #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 | 91 | #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 |
92 | #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */ | ||
93 | #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */ | ||
94 | #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ | ||
95 | #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */ | ||
96 | #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */ | ||
91 | #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ | 97 | #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ |
92 | #define BCMA_CC_JCMD_START 0x80000000 | 98 | #define BCMA_CC_JCMD_START 0x80000000 |
93 | #define BCMA_CC_JCMD_BUSY 0x80000000 | 99 | #define BCMA_CC_JCMD_BUSY 0x80000000 |
@@ -117,10 +123,58 @@ | |||
117 | #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ | 123 | #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ |
118 | #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ | 124 | #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ |
119 | #define BCMA_CC_FLASHCTL 0x0040 | 125 | #define BCMA_CC_FLASHCTL 0x0040 |
126 | /* Start/busy bit in flashcontrol */ | ||
127 | #define BCMA_CC_FLASHCTL_OPCODE 0x000000ff | ||
128 | #define BCMA_CC_FLASHCTL_ACTION 0x00000700 | ||
129 | #define BCMA_CC_FLASHCTL_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ | ||
120 | #define BCMA_CC_FLASHCTL_START 0x80000000 | 130 | #define BCMA_CC_FLASHCTL_START 0x80000000 |
121 | #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START | 131 | #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START |
132 | /* Flashcontrol action + opcodes for ST flashes */ | ||
133 | #define BCMA_CC_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ | ||
134 | #define BCMA_CC_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ | ||
135 | #define BCMA_CC_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ | ||
136 | #define BCMA_CC_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ | ||
137 | #define BCMA_CC_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ | ||
138 | #define BCMA_CC_FLASHCTL_ST_PP 0x0302 /* Page Program */ | ||
139 | #define BCMA_CC_FLASHCTL_ST_SE 0x02d8 /* Sector Erase */ | ||
140 | #define BCMA_CC_FLASHCTL_ST_BE 0x00c7 /* Bulk Erase */ | ||
141 | #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */ | ||
142 | #define BCMA_CC_FLASHCTL_ST_RES 0x03ab /* Read Electronic Signature */ | ||
143 | #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */ | ||
144 | #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */ | ||
145 | /* Flashcontrol action + opcodes for Atmel flashes */ | ||
146 | #define BCMA_CC_FLASHCTL_AT_READ 0x07e8 | ||
147 | #define BCMA_CC_FLASHCTL_AT_PAGE_READ 0x07d2 | ||
148 | #define BCMA_CC_FLASHCTL_AT_STATUS 0x01d7 | ||
149 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE 0x0384 | ||
150 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE 0x0387 | ||
151 | #define BCMA_CC_FLASHCTL_AT_BUF1_ERASE_PROGRAM 0x0283 | ||
152 | #define BCMA_CC_FLASHCTL_AT_BUF2_ERASE_PROGRAM 0x0286 | ||
153 | #define BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM 0x0288 | ||
154 | #define BCMA_CC_FLASHCTL_AT_BUF2_PROGRAM 0x0289 | ||
155 | #define BCMA_CC_FLASHCTL_AT_PAGE_ERASE 0x0281 | ||
156 | #define BCMA_CC_FLASHCTL_AT_BLOCK_ERASE 0x0250 | ||
157 | #define BCMA_CC_FLASHCTL_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 | ||
158 | #define BCMA_CC_FLASHCTL_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 | ||
159 | #define BCMA_CC_FLASHCTL_AT_BUF1_LOAD 0x0253 | ||
160 | #define BCMA_CC_FLASHCTL_AT_BUF2_LOAD 0x0255 | ||
161 | #define BCMA_CC_FLASHCTL_AT_BUF1_COMPARE 0x0260 | ||
162 | #define BCMA_CC_FLASHCTL_AT_BUF2_COMPARE 0x0261 | ||
163 | #define BCMA_CC_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 | ||
164 | #define BCMA_CC_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 | ||
122 | #define BCMA_CC_FLASHADDR 0x0044 | 165 | #define BCMA_CC_FLASHADDR 0x0044 |
123 | #define BCMA_CC_FLASHDATA 0x0048 | 166 | #define BCMA_CC_FLASHDATA 0x0048 |
167 | /* Status register bits for ST flashes */ | ||
168 | #define BCMA_CC_FLASHDATA_ST_WIP 0x01 /* Write In Progress */ | ||
169 | #define BCMA_CC_FLASHDATA_ST_WEL 0x02 /* Write Enable Latch */ | ||
170 | #define BCMA_CC_FLASHDATA_ST_BP_MASK 0x1c /* Block Protect */ | ||
171 | #define BCMA_CC_FLASHDATA_ST_BP_SHIFT 2 | ||
172 | #define BCMA_CC_FLASHDATA_ST_SRWD 0x80 /* Status Register Write Disable */ | ||
173 | /* Status register bits for Atmel flashes */ | ||
174 | #define BCMA_CC_FLASHDATA_AT_READY 0x80 | ||
175 | #define BCMA_CC_FLASHDATA_AT_MISMATCH 0x40 | ||
176 | #define BCMA_CC_FLASHDATA_AT_ID_MASK 0x38 | ||
177 | #define BCMA_CC_FLASHDATA_AT_ID_SHIFT 3 | ||
124 | #define BCMA_CC_BCAST_ADDR 0x0050 | 178 | #define BCMA_CC_BCAST_ADDR 0x0050 |
125 | #define BCMA_CC_BCAST_DATA 0x0054 | 179 | #define BCMA_CC_BCAST_DATA 0x0054 |
126 | #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ | 180 | #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ |
@@ -280,6 +334,15 @@ | |||
280 | 334 | ||
281 | /* 4706 PMU */ | 335 | /* 4706 PMU */ |
282 | #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 | 336 | #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 |
337 | #define BCMA_CC_PMU6_4706_PROCPLL_OFF 4 /* The CPU PLL */ | ||
338 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_MASK 0x000f0000 | ||
339 | #define BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT 16 | ||
340 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_MASK 0x0000f000 | ||
341 | #define BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT 12 | ||
342 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 | ||
343 | #define BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT 3 | ||
344 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 | ||
345 | #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0 | ||
283 | 346 | ||
284 | /* ALP clock on pre-PMU chips */ | 347 | /* ALP clock on pre-PMU chips */ |
285 | #define BCMA_CC_PMU_ALP_CLOCK 20000000 | 348 | #define BCMA_CC_PMU_ALP_CLOCK 20000000 |
@@ -308,6 +371,19 @@ | |||
308 | #define BCMA_CC_PPL_PCHI_OFF 5 | 371 | #define BCMA_CC_PPL_PCHI_OFF 5 |
309 | #define BCMA_CC_PPL_PCHI_MASK 0x0000003f | 372 | #define BCMA_CC_PPL_PCHI_MASK 0x0000003f |
310 | 373 | ||
374 | #define BCMA_CC_PMU_PLL_CTL0 0 | ||
375 | #define BCMA_CC_PMU_PLL_CTL1 1 | ||
376 | #define BCMA_CC_PMU_PLL_CTL2 2 | ||
377 | #define BCMA_CC_PMU_PLL_CTL3 3 | ||
378 | #define BCMA_CC_PMU_PLL_CTL4 4 | ||
379 | #define BCMA_CC_PMU_PLL_CTL5 5 | ||
380 | |||
381 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 | ||
382 | #define BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 | ||
383 | |||
384 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 | ||
385 | #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 | ||
386 | |||
311 | /* BCM4331 ChipControl numbers. */ | 387 | /* BCM4331 ChipControl numbers. */ |
312 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ | 388 | #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ |
313 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ | 389 | #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ |
@@ -321,9 +397,18 @@ | |||
321 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ | 397 | #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ |
322 | #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ | 398 | #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ |
323 | #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ | 399 | #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ |
400 | #define BCMA_CHIPCTL_4331_EXTPA_EN2 BIT(12) /* 0 ext pa disable, 1 ext pa enabled */ | ||
324 | #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ | 401 | #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ |
325 | #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ | 402 | #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ |
326 | 403 | ||
404 | /* 43224 chip-specific ChipControl register bits */ | ||
405 | #define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ | ||
406 | #define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ | ||
407 | #define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ | ||
408 | |||
409 | /* 4313 Chip specific ChipControl register bits */ | ||
410 | #define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ | ||
411 | |||
327 | /* Data for the PMU, if available. | 412 | /* Data for the PMU, if available. |
328 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) | 413 | * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) |
329 | */ | 414 | */ |
@@ -411,5 +496,6 @@ extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, | |||
411 | u32 offset, u32 mask, u32 set); | 496 | u32 offset, u32 mask, u32 set); |
412 | extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, | 497 | extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, |
413 | u32 offset, u32 mask, u32 set); | 498 | u32 offset, u32 mask, u32 set); |
499 | extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid); | ||
414 | 500 | ||
415 | #endif /* LINUX_BCMA_DRIVER_CC_H_ */ | 501 | #endif /* LINUX_BCMA_DRIVER_CC_H_ */ |