2 files changed, 22 insertions, 4 deletions

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index b0c174012436..c6454cca0447 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -20,6 +20,7 @@
 #include <linux/resource.h>
 
 #define AMBA_NR_IRQS    2
+#define AMBA_CID        0xb105f00d
 
 struct clk;
 
@@ -70,9 +71,15 @@ void amba_release_regions(struct amba_device *);
 #define amba_pclk_disable(d)    \
         do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
 
-#define amba_config(d)  (((d)->periphid >> 24) & 0xff)
-#define amba_rev(d)     (((d)->periphid >> 20) & 0x0f)
-#define amba_manf(d)    (((d)->periphid >> 12) & 0xff)
-#define amba_part(d)    ((d)->periphid & 0xfff)
+/* Some drivers don't use the struct amba_device */
+#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
+#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
+#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
+#define AMBA_PART_BITS(a) ((a) & 0xfff)
+
+#define amba_config(d)  AMBA_CONFIG_BITS((d)->periphid)
+#define amba_rev(d)     AMBA_REV_BITS((d)->periphid)
+#define amba_manf(d)    AMBA_MANF_BITS((d)->periphid)
+#define amba_part(d)    AMBA_PART_BITS((d)->periphid)
 
 #endif
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index e1b634b635f2..6021588ba0a8 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -32,7 +32,9 @@
 #define UART01x_RSR             0x04    /* Receive status register (Read). */
 #define UART01x_ECR             0x04    /* Error clear register (Write). */
 #define UART010_LCRH            0x08    /* Line control register, high byte. */
+#define ST_UART011_DMAWM        0x08    /* DMA watermark configure register. */
 #define UART010_LCRM            0x0C    /* Line control register, middle byte. */
+#define ST_UART011_TIMEOUT      0x0C    /* Timeout period register. */
 #define UART010_LCRL            0x10    /* Line control register, low byte. */
 #define UART010_CR              0x14    /* Control register. */
 #define UART01x_FR              0x18    /* Flag register (Read only). */
@@ -51,6 +53,15 @@
 #define UART011_MIS             0x40    /* Masked interrupt status. */
 #define UART011_ICR             0x44    /* Interrupt clear register. */
 #define UART011_DMACR           0x48    /* DMA control register. */
+#define ST_UART011_XFCR         0x50    /* XON/XOFF control register. */
+#define ST_UART011_XON1         0x54    /* XON1 register. */
+#define ST_UART011_XON2         0x58    /* XON2 register. */
+#define ST_UART011_XOFF1        0x5C    /* XON1 register. */
+#define ST_UART011_XOFF2        0x60    /* XON2 register. */
+#define ST_UART011_ITCR         0x80    /* Integration test control register. */
+#define ST_UART011_ITIP         0x84    /* Integration test input register. */
+#define ST_UART011_ABCR         0x100   /* Autobaud control register. */
+#define ST_UART011_ABIMSC       0x15C   /* Autobaud interrupt mask/clear register. */
 
 #define UART011_DR_OE           (1 << 11)
 #define UART011_DR_BE           (1 << 10)