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-rw-r--r--include/linux/amba/bus.h15
-rw-r--r--include/linux/amba/mmci.h2
-rw-r--r--include/linux/amba/serial.h11
3 files changed, 24 insertions, 4 deletions
diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index b0c174012436..c6454cca0447 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -20,6 +20,7 @@
20#include <linux/resource.h> 20#include <linux/resource.h>
21 21
22#define AMBA_NR_IRQS 2 22#define AMBA_NR_IRQS 2
23#define AMBA_CID 0xb105f00d
23 24
24struct clk; 25struct clk;
25 26
@@ -70,9 +71,15 @@ void amba_release_regions(struct amba_device *);
70#define amba_pclk_disable(d) \ 71#define amba_pclk_disable(d) \
71 do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0) 72 do { if (!IS_ERR((d)->pclk)) clk_disable((d)->pclk); } while (0)
72 73
73#define amba_config(d) (((d)->periphid >> 24) & 0xff) 74/* Some drivers don't use the struct amba_device */
74#define amba_rev(d) (((d)->periphid >> 20) & 0x0f) 75#define AMBA_CONFIG_BITS(a) (((a) >> 24) & 0xff)
75#define amba_manf(d) (((d)->periphid >> 12) & 0xff) 76#define AMBA_REV_BITS(a) (((a) >> 20) & 0x0f)
76#define amba_part(d) ((d)->periphid & 0xfff) 77#define AMBA_MANF_BITS(a) (((a) >> 12) & 0xff)
78#define AMBA_PART_BITS(a) ((a) & 0xfff)
79
80#define amba_config(d) AMBA_CONFIG_BITS((d)->periphid)
81#define amba_rev(d) AMBA_REV_BITS((d)->periphid)
82#define amba_manf(d) AMBA_MANF_BITS((d)->periphid)
83#define amba_part(d) AMBA_PART_BITS((d)->periphid)
77 84
78#endif 85#endif
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index ca84ce70d5d5..f4ee9acc9721 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -24,6 +24,7 @@
24 * whether a card is present in the MMC slot or not 24 * whether a card is present in the MMC slot or not
25 * @gpio_wp: read this GPIO pin to see if the card is write protected 25 * @gpio_wp: read this GPIO pin to see if the card is write protected
26 * @gpio_cd: read this GPIO pin to detect card insertion 26 * @gpio_cd: read this GPIO pin to detect card insertion
27 * @cd_invert: true if the gpio_cd pin value is active low
27 * @capabilities: the capabilities of the block as implemented in 28 * @capabilities: the capabilities of the block as implemented in
28 * this platform, signify anything MMC_CAP_* from mmc/host.h 29 * this platform, signify anything MMC_CAP_* from mmc/host.h
29 */ 30 */
@@ -35,6 +36,7 @@ struct mmci_platform_data {
35 unsigned int (*status)(struct device *); 36 unsigned int (*status)(struct device *);
36 int gpio_wp; 37 int gpio_wp;
37 int gpio_cd; 38 int gpio_cd;
39 bool cd_invert;
38 unsigned long capabilities; 40 unsigned long capabilities;
39}; 41};
40 42
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index e1b634b635f2..6021588ba0a8 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -32,7 +32,9 @@
32#define UART01x_RSR 0x04 /* Receive status register (Read). */ 32#define UART01x_RSR 0x04 /* Receive status register (Read). */
33#define UART01x_ECR 0x04 /* Error clear register (Write). */ 33#define UART01x_ECR 0x04 /* Error clear register (Write). */
34#define UART010_LCRH 0x08 /* Line control register, high byte. */ 34#define UART010_LCRH 0x08 /* Line control register, high byte. */
35#define ST_UART011_DMAWM 0x08 /* DMA watermark configure register. */
35#define UART010_LCRM 0x0C /* Line control register, middle byte. */ 36#define UART010_LCRM 0x0C /* Line control register, middle byte. */
37#define ST_UART011_TIMEOUT 0x0C /* Timeout period register. */
36#define UART010_LCRL 0x10 /* Line control register, low byte. */ 38#define UART010_LCRL 0x10 /* Line control register, low byte. */
37#define UART010_CR 0x14 /* Control register. */ 39#define UART010_CR 0x14 /* Control register. */
38#define UART01x_FR 0x18 /* Flag register (Read only). */ 40#define UART01x_FR 0x18 /* Flag register (Read only). */
@@ -51,6 +53,15 @@
51#define UART011_MIS 0x40 /* Masked interrupt status. */ 53#define UART011_MIS 0x40 /* Masked interrupt status. */
52#define UART011_ICR 0x44 /* Interrupt clear register. */ 54#define UART011_ICR 0x44 /* Interrupt clear register. */
53#define UART011_DMACR 0x48 /* DMA control register. */ 55#define UART011_DMACR 0x48 /* DMA control register. */
56#define ST_UART011_XFCR 0x50 /* XON/XOFF control register. */
57#define ST_UART011_XON1 0x54 /* XON1 register. */
58#define ST_UART011_XON2 0x58 /* XON2 register. */
59#define ST_UART011_XOFF1 0x5C /* XON1 register. */
60#define ST_UART011_XOFF2 0x60 /* XON2 register. */
61#define ST_UART011_ITCR 0x80 /* Integration test control register. */
62#define ST_UART011_ITIP 0x84 /* Integration test input register. */
63#define ST_UART011_ABCR 0x100 /* Autobaud control register. */
64#define ST_UART011_ABIMSC 0x15C /* Autobaud interrupt mask/clear register. */
54 65
55#define UART011_DR_OE (1 << 11) 66#define UART011_DR_OE (1 << 11)
56#define UART011_DR_BE (1 << 10) 67#define UART011_DR_BE (1 << 10)