4 files changed, 143 insertions, 73 deletions

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 9e7f259346e1..fcbbe71a3cc1 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -43,12 +43,12 @@ struct amba_id {
 
 struct amba_driver {
         struct device_driver    drv;
-        int                     (*probe)(struct amba_device *, struct amba_id *);
+        int                     (*probe)(struct amba_device *, const struct amba_id *);
         int                     (*remove)(struct amba_device *);
         void                    (*shutdown)(struct amba_device *);
         int                     (*suspend)(struct amba_device *, pm_message_t);
         int                     (*resume)(struct amba_device *);
-        struct amba_id          *id_table;
+        const struct amba_id    *id_table;
 };
 
 enum amba_vendor {
@@ -56,6 +56,10 @@ enum amba_vendor {
         AMBA_VENDOR_ST = 0x80,
 };
 
+extern struct bus_type amba_bustype;
+
+#define to_amba_device(d)       container_of(d, struct amba_device, dev)
+
 #define amba_get_drvdata(d)     dev_get_drvdata(&d->dev)
 #define amba_set_drvdata(d,p)   dev_set_drvdata(&d->dev, p)
 
diff --git a/include/linux/amba/clcd.h b/include/linux/amba/clcd.h
index be33b3affc8a..e82e3ee2c54a 100644
--- a/include/linux/amba/clcd.h
+++ b/include/linux/amba/clcd.h
@@ -53,6 +53,7 @@
 #define CNTL_LCDBPP8            (3 << 1)
 #define CNTL_LCDBPP16           (4 << 1)
 #define CNTL_LCDBPP16_565       (6 << 1)
+#define CNTL_LCDBPP16_444       (7 << 1)
 #define CNTL_LCDBPP24           (5 << 1)
 #define CNTL_LCDBW              (1 << 4)
 #define CNTL_LCDTFT             (1 << 5)
@@ -66,6 +67,32 @@
 #define CNTL_LDMAFIFOTIME       (1 << 15)
 #define CNTL_WATERMARK          (1 << 16)
 
+enum {
+        /* individual formats */
+        CLCD_CAP_RGB444         = (1 << 0),
+        CLCD_CAP_RGB5551        = (1 << 1),
+        CLCD_CAP_RGB565         = (1 << 2),
+        CLCD_CAP_RGB888         = (1 << 3),
+        CLCD_CAP_BGR444         = (1 << 4),
+        CLCD_CAP_BGR5551        = (1 << 5),
+        CLCD_CAP_BGR565         = (1 << 6),
+        CLCD_CAP_BGR888         = (1 << 7),
+
+        /* connection layouts */
+        CLCD_CAP_444            = CLCD_CAP_RGB444 | CLCD_CAP_BGR444,
+        CLCD_CAP_5551           = CLCD_CAP_RGB5551 | CLCD_CAP_BGR5551,
+        CLCD_CAP_565            = CLCD_CAP_RGB565 | CLCD_CAP_BGR565,
+        CLCD_CAP_888            = CLCD_CAP_RGB888 | CLCD_CAP_BGR888,
+
+        /* red/blue ordering */
+        CLCD_CAP_RGB            = CLCD_CAP_RGB444 | CLCD_CAP_RGB5551 |
+                                  CLCD_CAP_RGB565 | CLCD_CAP_RGB888,
+        CLCD_CAP_BGR            = CLCD_CAP_BGR444 | CLCD_CAP_BGR5551 |
+                                  CLCD_CAP_BGR565 | CLCD_CAP_BGR888,
+
+        CLCD_CAP_ALL            = CLCD_CAP_BGR | CLCD_CAP_RGB,
+};
+
 struct clcd_panel {
         struct fb_videomode     mode;
         signed short            width;  /* width in mm */
@@ -73,6 +100,7 @@ struct clcd_panel {
         u32                     tim2;
         u32                     tim3;
         u32                     cntl;
+        u32                     caps;
         unsigned int            bpp:8,
                                 fixedtimings:1,
                                 grayscale:1;
@@ -97,13 +125,18 @@ struct clcd_board {
         const char *name;
 
         /*
+         * Optional.  Hardware capability flags.
+         */
+        u32     caps;
+
+        /*
          * Optional.  Check whether the var structure is acceptable
          * for this display.
          */
         int     (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
 
         /*
-         * Compulsary.  Decode fb->fb.var into regs->*.  In the case of
+         * Compulsory.  Decode fb->fb.var into regs->*.  In the case of
          * fixed timing, set regs->* to the register values required.
          */
         void    (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
@@ -155,34 +188,35 @@ struct clcd_fb {
 
 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 {
+        struct fb_var_screeninfo *var = &fb->fb.var;
         u32 val, cpl;
 
         /*
          * Program the CLCD controller registers and start the CLCD
          */
-        val = ((fb->fb.var.xres / 16) - 1) << 2;
-        val |= (fb->fb.var.hsync_len - 1) << 8;
-        val |= (fb->fb.var.right_margin - 1) << 16;
-        val |= (fb->fb.var.left_margin - 1) << 24;
+        val = ((var->xres / 16) - 1) << 2;
+        val |= (var->hsync_len - 1) << 8;
+        val |= (var->right_margin - 1) << 16;
+        val |= (var->left_margin - 1) << 24;
         regs->tim0 = val;
 
-        val = fb->fb.var.yres;
+        val = var->yres;
         if (fb->panel->cntl & CNTL_LCDDUAL)
                 val /= 2;
         val -= 1;
-        val |= (fb->fb.var.vsync_len - 1) << 10;
-        val |= fb->fb.var.lower_margin << 16;
-        val |= fb->fb.var.upper_margin << 24;
+        val |= (var->vsync_len - 1) << 10;
+        val |= var->lower_margin << 16;
+        val |= var->upper_margin << 24;
         regs->tim1 = val;
 
         val = fb->panel->tim2;
-        val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
-        val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
+        val |= var->sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
+        val |= var->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
 
-        cpl = fb->fb.var.xres_virtual;
+        cpl = var->xres_virtual;
         if (fb->panel->cntl & CNTL_LCDTFT)        /* TFT */
                 /* / 1 */;
-        else if (!fb->fb.var.grayscale)           /* STN color */
+        else if (!var->grayscale)                 /* STN color */
                 cpl = cpl * 8 / 3;
         else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
                 cpl /= 8;
@@ -194,10 +228,22 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
         regs->tim3 = fb->panel->tim3;
 
         val = fb->panel->cntl;
-        if (fb->fb.var.grayscale)
+        if (var->grayscale)
                 val |= CNTL_LCDBW;
 
-        switch (fb->fb.var.bits_per_pixel) {
+        if (fb->panel->caps && fb->board->caps &&
+            var->bits_per_pixel >= 16) {
+                /*
+                 * if board and panel supply capabilities, we can support
+                 * changing BGR/RGB depending on supplied parameters
+                 */
+                if (var->red.offset == 0)
+                        val &= ~CNTL_BGR;
+                else
+                        val |= CNTL_BGR;
+        }
+
+        switch (var->bits_per_pixel) {
         case 1:
                 val |= CNTL_LCDBPP1;
                 break;
@@ -212,15 +258,17 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
                 break;
         case 16:
                 /*
-                 * PL110 cannot choose between 5551 and 565 modes in
-                 * its control register
+                 * PL110 cannot choose between 5551 and 565 modes in its
+                 * control register.  It is possible to use 565 with
+                 * custom external wiring.
                  */
-                if ((fb->dev->periphid & 0x000fffff) == 0x00041110)
+                if (amba_part(fb->dev) == 0x110 ||
+                    var->green.length == 5)
                         val |= CNTL_LCDBPP16;
-                else if (fb->fb.var.green.length == 5)
-                        val |= CNTL_LCDBPP16;
-                else
+                else if (var->green.length == 6)
                         val |= CNTL_LCDBPP16_565;
+                else
+                        val |= CNTL_LCDBPP16_444;
                 break;
         case 32:
                 val |= CNTL_LCDBPP24;
@@ -228,7 +276,7 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
         }
 
         regs->cntl = val;
-        regs->pixclock = fb->fb.var.pixclock;
+        regs->pixclock = var->pixclock;
 }
 
 static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index f4ee9acc9721..21114810c7c0 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -6,6 +6,9 @@
 
 #include <linux/mmc/host.h>
 
+/* Just some dummy forwarding */
+struct dma_chan;
+
 /**
  * struct mmci_platform_data - platform configuration for the MMCI
  * (also known as PL180) block.
@@ -27,6 +30,17 @@
  * @cd_invert: true if the gpio_cd pin value is active low
  * @capabilities: the capabilities of the block as implemented in
  * this platform, signify anything MMC_CAP_* from mmc/host.h
+ * @dma_filter: function used to select an appropriate RX and TX
+ * DMA channel to be used for DMA, if and only if you're deploying the
+ * generic DMA engine
+ * @dma_rx_param: parameter passed to the DMA allocation
+ * filter in order to select an appropriate RX channel. If
+ * there is a bidirectional RX+TX channel, then just specify
+ * this and leave dma_tx_param set to NULL
+ * @dma_tx_param: parameter passed to the DMA allocation
+ * filter in order to select an appropriate TX channel. If this
+ * is NULL the driver will attempt to use the RX channel as a
+ * bidirectional channel
  */
 struct mmci_platform_data {
         unsigned int f_max;
@@ -38,6 +52,9 @@ struct mmci_platform_data {
         int     gpio_cd;
         bool    cd_invert;
         unsigned long capabilities;
+        bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+        void *dma_rx_param;
+        void *dma_tx_param;
 };
 
 #endif
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
index 521a0f8974ac..3111385b8ca7 100644
--- a/include/linux/amba/pl08x.h
+++ b/include/linux/amba/pl08x.h
@@ -12,7 +12,6 @@
  *
  * Please credit ARM.com
  * Documentation: ARM DDI 0196D
- *
  */
 
 #ifndef AMBA_PL08X_H
@@ -22,6 +21,15 @@
 #include <linux/dmaengine.h>
 #include <linux/interrupt.h>
 
+struct pl08x_lli;
+struct pl08x_driver_data;
+
+/* Bitmasks for selecting AHB ports for DMA transfers */
+enum {
+        PL08X_AHB1 = (1 << 0),
+        PL08X_AHB2 = (1 << 1)
+};
+
 /**
  * struct pl08x_channel_data - data structure to pass info between
  * platform and PL08x driver regarding channel configuration
@@ -46,8 +54,10 @@
  * @circular_buffer: whether the buffer passed in is circular and
  * shall simply be looped round round (like a record baby round
  * round round round)
- * @single: the device connected to this channel will request single
- * DMA transfers, not bursts. (Bursts are default.)
+ * @single: the device connected to this channel will request single DMA
+ * transfers, not bursts. (Bursts are default.)
+ * @periph_buses: the device connected to this channel is accessible via
+ * these buses (use PL08X_AHB1 | PL08X_AHB2).
  */
 struct pl08x_channel_data {
         char *bus_id;
@@ -55,10 +65,10 @@ struct pl08x_channel_data {
         int max_signal;
         u32 muxval;
         u32 cctl;
-        u32 ccfg;
         dma_addr_t addr;
         bool circular_buffer;
         bool single;
+        u8 periph_buses;
 };
 
 /**
@@ -67,24 +77,23 @@ struct pl08x_channel_data {
  * @addr: current address
  * @maxwidth: the maximum width of a transfer on this bus
  * @buswidth: the width of this bus in bytes: 1, 2 or 4
- * @fill_bytes: bytes required to fill to the next bus memory
- * boundary
+ * @fill_bytes: bytes required to fill to the next bus memory boundary
  */
 struct pl08x_bus_data {
         dma_addr_t addr;
         u8 maxwidth;
         u8 buswidth;
-        u32 fill_bytes;
+        size_t fill_bytes;
 };
 
 /**
  * struct pl08x_phy_chan - holder for the physical channels
  * @id: physical index to this channel
  * @lock: a lock to use when altering an instance of this struct
- * @signal: the physical signal (aka channel) serving this
- * physical channel right now
- * @serving: the virtual channel currently being served by this
- * physical channel
+ * @signal: the physical signal (aka channel) serving this physical channel
+ * right now
+ * @serving: the virtual channel currently being served by this physical
+ * channel
  */
 struct pl08x_phy_chan {
         unsigned int id;
@@ -92,11 +101,6 @@ struct pl08x_phy_chan {
         spinlock_t lock;
         int signal;
         struct pl08x_dma_chan *serving;
-        u32 csrc;
-        u32 cdst;
-        u32 clli;
-        u32 cctl;
-        u32 ccfg;
 };
 
 /**
@@ -108,26 +112,23 @@ struct pl08x_txd {
         struct dma_async_tx_descriptor tx;
         struct list_head node;
         enum dma_data_direction direction;
-        struct pl08x_bus_data srcbus;
-        struct pl08x_bus_data dstbus;
-        int len;
+        dma_addr_t src_addr;
+        dma_addr_t dst_addr;
+        size_t len;
         dma_addr_t llis_bus;
-        void *llis_va;
-        struct pl08x_channel_data *cd;
-        bool active;
+        struct pl08x_lli *llis_va;
+        /* Default cctl value for LLIs */
+        u32 cctl;
         /*
          * Settings to be put into the physical channel when we
-         * trigger this txd
+         * trigger this txd.  Other registers are in llis_va[0].
          */
-        u32 csrc;
-        u32 cdst;
-        u32 clli;
-        u32 cctl;
+        u32 ccfg;
 };
 
 /**
- * struct pl08x_dma_chan_state - holds the PL08x specific virtual
- * channel states
+ * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
+ * states
  * @PL08X_CHAN_IDLE: the channel is idle
  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
  * channel and is running a transfer on it
@@ -147,6 +148,8 @@ enum pl08x_dma_chan_state {
  * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
  * @chan: wrappped abstract channel
  * @phychan: the physical channel utilized by this channel, if there is one
+ * @phychan_hold: if non-zero, hold on to the physical channel even if we
+ * have no pending entries
  * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
  * @name: name of channel
  * @cd: channel platform data
@@ -154,53 +157,49 @@ enum pl08x_dma_chan_state {
  * @runtime_direction: current direction of this channel according to
  * runtime config
  * @lc: last completed transaction on this channel
- * @desc_list: queued transactions pending on this channel
+ * @pend_list: queued transactions pending on this channel
  * @at: active transaction on this channel
- * @lockflags: sometimes we let a lock last between two function calls,
- * especially prep/submit, and then we need to store the IRQ flags
- * in the channel state, here
  * @lock: a lock for this channel data
  * @host: a pointer to the host (internal use)
  * @state: whether the channel is idle, paused, running etc
  * @slave: whether this channel is a device (slave) or for memcpy
- * @waiting: a TX descriptor on this channel which is waiting for
- * a physical channel to become available
+ * @waiting: a TX descriptor on this channel which is waiting for a physical
+ * channel to become available
  */
 struct pl08x_dma_chan {
         struct dma_chan chan;
         struct pl08x_phy_chan *phychan;
+        int phychan_hold;
         struct tasklet_struct tasklet;
         char *name;
         struct pl08x_channel_data *cd;
         dma_addr_t runtime_addr;
         enum dma_data_direction runtime_direction;
-        atomic_t last_issued;
         dma_cookie_t lc;
-        struct list_head desc_list;
+        struct list_head pend_list;
         struct pl08x_txd *at;
-        unsigned long lockflags;
         spinlock_t lock;
-        void *host;
+        struct pl08x_driver_data *host;
         enum pl08x_dma_chan_state state;
         bool slave;
         struct pl08x_txd *waiting;
 };
 
 /**
- * struct pl08x_platform_data - the platform configuration for the
- * PL08x PrimeCells.
+ * struct pl08x_platform_data - the platform configuration for the PL08x
+ * PrimeCells.
  * @slave_channels: the channels defined for the different devices on the
  * platform, all inclusive, including multiplexed channels. The available
- * physical channels will be multiplexed around these signals as they
- * are requested, just enumerate all possible channels.
- * @get_signal: request a physical signal to be used for a DMA
- * transfer immediately: if there is some multiplexing or similar blocking
- * the use of the channel the transfer can be denied by returning
- * less than zero, else it returns the allocated signal number
+ * physical channels will be multiplexed around these signals as they are
+ * requested, just enumerate all possible channels.
+ * @get_signal: request a physical signal to be used for a DMA transfer
+ * immediately: if there is some multiplexing or similar blocking the use
+ * of the channel the transfer can be denied by returning less than zero,
+ * else it returns the allocated signal number
  * @put_signal: indicate to the platform that this physical signal is not
  * running any DMA transfer and multiplexing can be recycled
- * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
- * LLI addresses are on 0/1 Master 1/2.
+ * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
+ * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
  */
 struct pl08x_platform_data {
         struct pl08x_channel_data *slave_channels;
@@ -208,6 +207,8 @@ struct pl08x_platform_data {
         struct pl08x_channel_data memcpy_channel;
         int (*get_signal)(struct pl08x_dma_chan *);
         void (*put_signal)(struct pl08x_dma_chan *);
+        u8 lli_buses;
+        u8 mem_buses;
 };
 
 #ifdef CONFIG_AMBA_PL08X