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-rw-r--r--include/dt-bindings/clock/alphascale,asm9260.h97
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h88
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h1
-rw-r--r--include/dt-bindings/clock/qcom,lcc-ipq806x.h30
-rw-r--r--include/dt-bindings/clock/qcom,lcc-msm8960.h50
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h4
6 files changed, 265 insertions, 5 deletions
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000000..04e8db27daf0
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_ASM9260_H
15#define _DT_BINDINGS_CLK_ASM9260_H
16
17/* ahb gate */
18#define CLKID_AHB_ROM 0
19#define CLKID_AHB_RAM 1
20#define CLKID_AHB_GPIO 2
21#define CLKID_AHB_MAC 3
22#define CLKID_AHB_EMI 4
23#define CLKID_AHB_USB0 5
24#define CLKID_AHB_USB1 6
25#define CLKID_AHB_DMA0 7
26#define CLKID_AHB_DMA1 8
27#define CLKID_AHB_UART0 9
28#define CLKID_AHB_UART1 10
29#define CLKID_AHB_UART2 11
30#define CLKID_AHB_UART3 12
31#define CLKID_AHB_UART4 13
32#define CLKID_AHB_UART5 14
33#define CLKID_AHB_UART6 15
34#define CLKID_AHB_UART7 16
35#define CLKID_AHB_UART8 17
36#define CLKID_AHB_UART9 18
37#define CLKID_AHB_I2S0 19
38#define CLKID_AHB_I2C0 20
39#define CLKID_AHB_I2C1 21
40#define CLKID_AHB_SSP0 22
41#define CLKID_AHB_IOCONFIG 23
42#define CLKID_AHB_WDT 24
43#define CLKID_AHB_CAN0 25
44#define CLKID_AHB_CAN1 26
45#define CLKID_AHB_MPWM 27
46#define CLKID_AHB_SPI0 28
47#define CLKID_AHB_SPI1 29
48#define CLKID_AHB_QEI 30
49#define CLKID_AHB_QUADSPI0 31
50#define CLKID_AHB_CAMIF 32
51#define CLKID_AHB_LCDIF 33
52#define CLKID_AHB_TIMER0 34
53#define CLKID_AHB_TIMER1 35
54#define CLKID_AHB_TIMER2 36
55#define CLKID_AHB_TIMER3 37
56#define CLKID_AHB_IRQ 38
57#define CLKID_AHB_RTC 39
58#define CLKID_AHB_NAND 40
59#define CLKID_AHB_ADC0 41
60#define CLKID_AHB_LED 42
61#define CLKID_AHB_DAC0 43
62#define CLKID_AHB_LCD 44
63#define CLKID_AHB_I2S1 45
64#define CLKID_AHB_MAC1 46
65
66/* devider */
67#define CLKID_SYS_CPU 47
68#define CLKID_SYS_AHB 48
69#define CLKID_SYS_I2S0M 49
70#define CLKID_SYS_I2S0S 50
71#define CLKID_SYS_I2S1M 51
72#define CLKID_SYS_I2S1S 52
73#define CLKID_SYS_UART0 53
74#define CLKID_SYS_UART1 54
75#define CLKID_SYS_UART2 55
76#define CLKID_SYS_UART3 56
77#define CLKID_SYS_UART4 56
78#define CLKID_SYS_UART5 57
79#define CLKID_SYS_UART6 58
80#define CLKID_SYS_UART7 59
81#define CLKID_SYS_UART8 60
82#define CLKID_SYS_UART9 61
83#define CLKID_SYS_SPI0 62
84#define CLKID_SYS_SPI1 63
85#define CLKID_SYS_QUADSPI 64
86#define CLKID_SYS_SSP0 65
87#define CLKID_SYS_NAND 66
88#define CLKID_SYS_TRACE 67
89#define CLKID_SYS_CAMM 68
90#define CLKID_SYS_WDT 69
91#define CLKID_SYS_CLKOUT 70
92#define CLKID_SYS_MAC 71
93#define CLKID_SYS_LCD 72
94#define CLKID_SYS_ADCANA 73
95
96#define MAX_CLKS 74
97#endif
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
17#define DOUT_SCLK_CC_PLL 4 17#define DOUT_SCLK_CC_PLL 4
18#define DOUT_SCLK_MFC_PLL 5 18#define DOUT_SCLK_MFC_PLL 5
19#define DOUT_ACLK_CCORE_133 6 19#define DOUT_ACLK_CCORE_133 6
20#define TOPC_NR_CLK 7 20#define DOUT_ACLK_MSCL_532 7
21#define ACLK_MSCL_532 8
22#define DOUT_SCLK_AUD_PLL 9
23#define FOUT_AUD_PLL 10
24#define TOPC_NR_CLK 11
21 25
22/* TOP0 */ 26/* TOP0 */
23#define DOUT_ACLK_PERIC1 1 27#define DOUT_ACLK_PERIC1 1
@@ -26,7 +30,15 @@
26#define CLK_SCLK_UART1 4 30#define CLK_SCLK_UART1 4
27#define CLK_SCLK_UART2 5 31#define CLK_SCLK_UART2 5
28#define CLK_SCLK_UART3 6 32#define CLK_SCLK_UART3 6
29#define TOP0_NR_CLK 7 33#define CLK_SCLK_SPI0 7
34#define CLK_SCLK_SPI1 8
35#define CLK_SCLK_SPI2 9
36#define CLK_SCLK_SPI3 10
37#define CLK_SCLK_SPI4 11
38#define CLK_SCLK_SPDIF 12
39#define CLK_SCLK_PCM1 13
40#define CLK_SCLK_I2S1 14
41#define TOP0_NR_CLK 15
30 42
31/* TOP1 */ 43/* TOP1 */
32#define DOUT_ACLK_FSYS1_200 1 44#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +82,23 @@
70#define PCLK_HSI2C6 9 82#define PCLK_HSI2C6 9
71#define PCLK_HSI2C7 10 83#define PCLK_HSI2C7 10
72#define PCLK_HSI2C8 11 84#define PCLK_HSI2C8 11
73#define PERIC1_NR_CLK 12 85#define PCLK_SPI0 12
86#define PCLK_SPI1 13
87#define PCLK_SPI2 14
88#define PCLK_SPI3 15
89#define PCLK_SPI4 16
90#define SCLK_SPI0 17
91#define SCLK_SPI1 18
92#define SCLK_SPI2 19
93#define SCLK_SPI3 20
94#define SCLK_SPI4 21
95#define PCLK_I2S1 22
96#define PCLK_PCM1 23
97#define PCLK_SPDIF 24
98#define SCLK_I2S1 25
99#define SCLK_PCM1 26
100#define SCLK_SPDIF 27
101#define PERIC1_NR_CLK 28
74 102
75/* PERIS */ 103/* PERIS */
76#define PCLK_CHIPID 1 104#define PCLK_CHIPID 1
@@ -82,11 +110,63 @@
82 110
83/* FSYS0 */ 111/* FSYS0 */
84#define ACLK_MMC2 1 112#define ACLK_MMC2 1
85#define FSYS0_NR_CLK 2 113#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
114#define ACLK_USBDRD300 3
115#define SCLK_USBDRD300_SUSPENDCLK 4
116#define SCLK_USBDRD300_REFCLK 5
117#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
118#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
119#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
120#define ACLK_PDMA0 9
121#define ACLK_PDMA1 10
122#define FSYS0_NR_CLK 11
86 123
87/* FSYS1 */ 124/* FSYS1 */
88#define ACLK_MMC1 1 125#define ACLK_MMC1 1
89#define ACLK_MMC0 2 126#define ACLK_MMC0 2
90#define FSYS1_NR_CLK 3 127#define FSYS1_NR_CLK 3
91 128
129/* MSCL */
130#define USERMUX_ACLK_MSCL_532 1
131#define DOUT_PCLK_MSCL 2
132#define ACLK_MSCL_0 3
133#define ACLK_MSCL_1 4
134#define ACLK_JPEG 5
135#define ACLK_G2D 6
136#define ACLK_LH_ASYNC_SI_MSCL_0 7
137#define ACLK_LH_ASYNC_SI_MSCL_1 8
138#define ACLK_AXI2ACEL_BRIDGE 9
139#define ACLK_XIU_MSCLX_0 10
140#define ACLK_XIU_MSCLX_1 11
141#define ACLK_QE_MSCL_0 12
142#define ACLK_QE_MSCL_1 13
143#define ACLK_QE_JPEG 14
144#define ACLK_QE_G2D 15
145#define ACLK_PPMU_MSCL_0 16
146#define ACLK_PPMU_MSCL_1 17
147#define ACLK_MSCLNP_133 18
148#define ACLK_AHB2APB_MSCL0P 19
149#define ACLK_AHB2APB_MSCL1P 20
150
151#define PCLK_MSCL_0 21
152#define PCLK_MSCL_1 22
153#define PCLK_JPEG 23
154#define PCLK_G2D 24
155#define PCLK_QE_MSCL_0 25
156#define PCLK_QE_MSCL_1 26
157#define PCLK_QE_JPEG 27
158#define PCLK_QE_G2D 28
159#define PCLK_PPMU_MSCL_0 29
160#define PCLK_PPMU_MSCL_1 30
161#define PCLK_AXI2ACEL_BRIDGE 31
162#define PCLK_PMU_MSCL 32
163#define MSCL_NR_CLK 33
164
165/* AUD */
166#define SCLK_I2S 1
167#define SCLK_PCM 2
168#define PCLK_I2S 3
169#define PCLK_PCM 4
170#define ACLK_ADMA 5
171#define AUD_NR_CLK 6
92#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 172#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cadb0bd4..04fb29ae30e6 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -238,7 +238,6 @@
238#define PLL0_VOTE 221 238#define PLL0_VOTE 221
239#define PLL3 222 239#define PLL3 222
240#define PLL3_VOTE 223 240#define PLL3_VOTE 223
241#define PLL4 224
242#define PLL4_VOTE 225 241#define PLL4_VOTE 225
243#define PLL8 226 242#define PLL8 226
244#define PLL8_VOTE 227 243#define PLL8_VOTE 227
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000000..4e944b85c56d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
15#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SPDIF_SRC 9
27#define SPDIF_CLK 10
28#define AHBIX_CLK 11
29
30#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000000..4fb2aa64d9fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
15#define _DT_BINDINGS_CLK_LCC_MSM8960_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SLIMBUS_SRC 9
27#define AUDIO_SLIMBUS_CLK 10
28#define SPS_SLIMBUS_CLK 11
29#define CODEC_I2S_MIC_OSR_SRC 12
30#define CODEC_I2S_MIC_OSR_CLK 13
31#define CODEC_I2S_MIC_DIV_CLK 14
32#define CODEC_I2S_MIC_BIT_DIV_CLK 15
33#define CODEC_I2S_MIC_BIT_CLK 16
34#define SPARE_I2S_MIC_OSR_SRC 17
35#define SPARE_I2S_MIC_OSR_CLK 18
36#define SPARE_I2S_MIC_DIV_CLK 19
37#define SPARE_I2S_MIC_BIT_DIV_CLK 20
38#define SPARE_I2S_MIC_BIT_CLK 21
39#define CODEC_I2S_SPKR_OSR_SRC 22
40#define CODEC_I2S_SPKR_OSR_CLK 23
41#define CODEC_I2S_SPKR_DIV_CLK 24
42#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
43#define CODEC_I2S_SPKR_BIT_CLK 26
44#define SPARE_I2S_SPKR_OSR_SRC 27
45#define SPARE_I2S_SPKR_OSR_CLK 28
46#define SPARE_I2S_SPKR_DIV_CLK 29
47#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
48#define SPARE_I2S_SPKR_BIT_CLK 31
49
50#endif
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..1e626335acf3 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,9 @@
80#define SCLK_SDIO0_SAMPLE 119 80#define SCLK_SDIO0_SAMPLE 119
81#define SCLK_SDIO1_SAMPLE 120 81#define SCLK_SDIO1_SAMPLE 120
82#define SCLK_EMMC_SAMPLE 121 82#define SCLK_EMMC_SAMPLE 121
83#define SCLK_USBPHY480M_SRC 122
84#define SCLK_PVTM_CORE 123
85#define SCLK_PVTM_GPU 124
83 86
84#define DCLK_VOP0 190 87#define DCLK_VOP0 190
85#define DCLK_VOP1 191 88#define DCLK_VOP1 191
@@ -154,6 +157,7 @@
154#define PCLK_PUBL0 365 157#define PCLK_PUBL0 365
155#define PCLK_DDRUPCTL1 366 158#define PCLK_DDRUPCTL1 366
156#define PCLK_PUBL1 367 159#define PCLK_PUBL1 367
160#define PCLK_WDT 368
157 161
158/* hclk gates */ 162/* hclk gates */
159#define HCLK_GPS 448 163#define HCLK_GPS 448
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 10:26:01 -0400