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-rw-r--r--include/dt-bindings/clock/alphascale,asm9260.h97
-rw-r--r--include/dt-bindings/clock/exynos5420.h6
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h88
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h1
-rw-r--r--include/dt-bindings/clock/qcom,lcc-ipq806x.h30
-rw-r--r--include/dt-bindings/clock/qcom,lcc-msm8960.h50
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h2
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h17
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h7
-rw-r--r--include/dt-bindings/clock/sh73a0-clock.h79
-rw-r--r--include/dt-bindings/clock/stih418-clks.h34
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h345
-rw-r--r--include/dt-bindings/clock/tegra124-car.h345
-rw-r--r--include/dt-bindings/clock/vf610-clock.h3
-rw-r--r--include/dt-bindings/dma/sun4i-a10.h56
-rw-r--r--include/dt-bindings/gpio/meson8-gpio.h157
-rw-r--r--include/dt-bindings/iio/qcom,spmi-vadc.h119
-rw-r--r--include/dt-bindings/interrupt-controller/arm-gic.h4
-rw-r--r--include/dt-bindings/mfd/qcom-rpm.h154
-rw-r--r--include/dt-bindings/pinctrl/omap.h1
-rw-r--r--include/dt-bindings/pinctrl/sun4i-a10.h62
-rw-r--r--include/dt-bindings/sound/samsung-i2s.h8
-rw-r--r--include/dt-bindings/thermal/thermal.h2
-rw-r--r--include/dt-bindings/thermal/thermal_exynos.h28
25 files changed, 1351 insertions, 345 deletions
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000000..04e8db27daf0
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
1/*
2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_ASM9260_H
15#define _DT_BINDINGS_CLK_ASM9260_H
16
17/* ahb gate */
18#define CLKID_AHB_ROM 0
19#define CLKID_AHB_RAM 1
20#define CLKID_AHB_GPIO 2
21#define CLKID_AHB_MAC 3
22#define CLKID_AHB_EMI 4
23#define CLKID_AHB_USB0 5
24#define CLKID_AHB_USB1 6
25#define CLKID_AHB_DMA0 7
26#define CLKID_AHB_DMA1 8
27#define CLKID_AHB_UART0 9
28#define CLKID_AHB_UART1 10
29#define CLKID_AHB_UART2 11
30#define CLKID_AHB_UART3 12
31#define CLKID_AHB_UART4 13
32#define CLKID_AHB_UART5 14
33#define CLKID_AHB_UART6 15
34#define CLKID_AHB_UART7 16
35#define CLKID_AHB_UART8 17
36#define CLKID_AHB_UART9 18
37#define CLKID_AHB_I2S0 19
38#define CLKID_AHB_I2C0 20
39#define CLKID_AHB_I2C1 21
40#define CLKID_AHB_SSP0 22
41#define CLKID_AHB_IOCONFIG 23
42#define CLKID_AHB_WDT 24
43#define CLKID_AHB_CAN0 25
44#define CLKID_AHB_CAN1 26
45#define CLKID_AHB_MPWM 27
46#define CLKID_AHB_SPI0 28
47#define CLKID_AHB_SPI1 29
48#define CLKID_AHB_QEI 30
49#define CLKID_AHB_QUADSPI0 31
50#define CLKID_AHB_CAMIF 32
51#define CLKID_AHB_LCDIF 33
52#define CLKID_AHB_TIMER0 34
53#define CLKID_AHB_TIMER1 35
54#define CLKID_AHB_TIMER2 36
55#define CLKID_AHB_TIMER3 37
56#define CLKID_AHB_IRQ 38
57#define CLKID_AHB_RTC 39
58#define CLKID_AHB_NAND 40
59#define CLKID_AHB_ADC0 41
60#define CLKID_AHB_LED 42
61#define CLKID_AHB_DAC0 43
62#define CLKID_AHB_LCD 44
63#define CLKID_AHB_I2S1 45
64#define CLKID_AHB_MAC1 46
65
66/* devider */
67#define CLKID_SYS_CPU 47
68#define CLKID_SYS_AHB 48
69#define CLKID_SYS_I2S0M 49
70#define CLKID_SYS_I2S0S 50
71#define CLKID_SYS_I2S1M 51
72#define CLKID_SYS_I2S1S 52
73#define CLKID_SYS_UART0 53
74#define CLKID_SYS_UART1 54
75#define CLKID_SYS_UART2 55
76#define CLKID_SYS_UART3 56
77#define CLKID_SYS_UART4 56
78#define CLKID_SYS_UART5 57
79#define CLKID_SYS_UART6 58
80#define CLKID_SYS_UART7 59
81#define CLKID_SYS_UART8 60
82#define CLKID_SYS_UART9 61
83#define CLKID_SYS_SPI0 62
84#define CLKID_SYS_SPI1 63
85#define CLKID_SYS_QUADSPI 64
86#define CLKID_SYS_SSP0 65
87#define CLKID_SYS_NAND 66
88#define CLKID_SYS_TRACE 67
89#define CLKID_SYS_CAMM 68
90#define CLKID_SYS_WDT 69
91#define CLKID_SYS_CLKOUT 70
92#define CLKID_SYS_MAC 71
93#define CLKID_SYS_LCD 72
94#define CLKID_SYS_ADCANA 73
95
96#define MAX_CLKS 74
97#endif
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 8dc0913f1775..99da0d117a7d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -204,6 +204,12 @@
204#define CLK_MOUT_MAUDIO0 643 204#define CLK_MOUT_MAUDIO0 643
205#define CLK_MOUT_USER_ACLK333 644 205#define CLK_MOUT_USER_ACLK333 644
206#define CLK_MOUT_SW_ACLK333 645 206#define CLK_MOUT_SW_ACLK333 645
207#define CLK_MOUT_USER_ACLK200_DISP1 646
208#define CLK_MOUT_SW_ACLK200 647
209#define CLK_MOUT_USER_ACLK300_DISP1 648
210#define CLK_MOUT_SW_ACLK300 649
211#define CLK_MOUT_USER_ACLK400_DISP1 650
212#define CLK_MOUT_SW_ACLK400 651
207 213
208/* divider clocks */ 214/* divider clocks */
209#define CLK_DOUT_PIXEL 768 215#define CLK_DOUT_PIXEL 768
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
17#define DOUT_SCLK_CC_PLL 4 17#define DOUT_SCLK_CC_PLL 4
18#define DOUT_SCLK_MFC_PLL 5 18#define DOUT_SCLK_MFC_PLL 5
19#define DOUT_ACLK_CCORE_133 6 19#define DOUT_ACLK_CCORE_133 6
20#define TOPC_NR_CLK 7 20#define DOUT_ACLK_MSCL_532 7
21#define ACLK_MSCL_532 8
22#define DOUT_SCLK_AUD_PLL 9
23#define FOUT_AUD_PLL 10
24#define TOPC_NR_CLK 11
21 25
22/* TOP0 */ 26/* TOP0 */
23#define DOUT_ACLK_PERIC1 1 27#define DOUT_ACLK_PERIC1 1
@@ -26,7 +30,15 @@
26#define CLK_SCLK_UART1 4 30#define CLK_SCLK_UART1 4
27#define CLK_SCLK_UART2 5 31#define CLK_SCLK_UART2 5
28#define CLK_SCLK_UART3 6 32#define CLK_SCLK_UART3 6
29#define TOP0_NR_CLK 7 33#define CLK_SCLK_SPI0 7
34#define CLK_SCLK_SPI1 8
35#define CLK_SCLK_SPI2 9
36#define CLK_SCLK_SPI3 10
37#define CLK_SCLK_SPI4 11
38#define CLK_SCLK_SPDIF 12
39#define CLK_SCLK_PCM1 13
40#define CLK_SCLK_I2S1 14
41#define TOP0_NR_CLK 15
30 42
31/* TOP1 */ 43/* TOP1 */
32#define DOUT_ACLK_FSYS1_200 1 44#define DOUT_ACLK_FSYS1_200 1
@@ -70,7 +82,23 @@
70#define PCLK_HSI2C6 9 82#define PCLK_HSI2C6 9
71#define PCLK_HSI2C7 10 83#define PCLK_HSI2C7 10
72#define PCLK_HSI2C8 11 84#define PCLK_HSI2C8 11
73#define PERIC1_NR_CLK 12 85#define PCLK_SPI0 12
86#define PCLK_SPI1 13
87#define PCLK_SPI2 14
88#define PCLK_SPI3 15
89#define PCLK_SPI4 16
90#define SCLK_SPI0 17
91#define SCLK_SPI1 18
92#define SCLK_SPI2 19
93#define SCLK_SPI3 20
94#define SCLK_SPI4 21
95#define PCLK_I2S1 22
96#define PCLK_PCM1 23
97#define PCLK_SPDIF 24
98#define SCLK_I2S1 25
99#define SCLK_PCM1 26
100#define SCLK_SPDIF 27
101#define PERIC1_NR_CLK 28
74 102
75/* PERIS */ 103/* PERIS */
76#define PCLK_CHIPID 1 104#define PCLK_CHIPID 1
@@ -82,11 +110,63 @@
82 110
83/* FSYS0 */ 111/* FSYS0 */
84#define ACLK_MMC2 1 112#define ACLK_MMC2 1
85#define FSYS0_NR_CLK 2 113#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
114#define ACLK_USBDRD300 3
115#define SCLK_USBDRD300_SUSPENDCLK 4
116#define SCLK_USBDRD300_REFCLK 5
117#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
118#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
119#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
120#define ACLK_PDMA0 9
121#define ACLK_PDMA1 10
122#define FSYS0_NR_CLK 11
86 123
87/* FSYS1 */ 124/* FSYS1 */
88#define ACLK_MMC1 1 125#define ACLK_MMC1 1
89#define ACLK_MMC0 2 126#define ACLK_MMC0 2
90#define FSYS1_NR_CLK 3 127#define FSYS1_NR_CLK 3
91 128
129/* MSCL */
130#define USERMUX_ACLK_MSCL_532 1
131#define DOUT_PCLK_MSCL 2
132#define ACLK_MSCL_0 3
133#define ACLK_MSCL_1 4
134#define ACLK_JPEG 5
135#define ACLK_G2D 6
136#define ACLK_LH_ASYNC_SI_MSCL_0 7
137#define ACLK_LH_ASYNC_SI_MSCL_1 8
138#define ACLK_AXI2ACEL_BRIDGE 9
139#define ACLK_XIU_MSCLX_0 10
140#define ACLK_XIU_MSCLX_1 11
141#define ACLK_QE_MSCL_0 12
142#define ACLK_QE_MSCL_1 13
143#define ACLK_QE_JPEG 14
144#define ACLK_QE_G2D 15
145#define ACLK_PPMU_MSCL_0 16
146#define ACLK_PPMU_MSCL_1 17
147#define ACLK_MSCLNP_133 18
148#define ACLK_AHB2APB_MSCL0P 19
149#define ACLK_AHB2APB_MSCL1P 20
150
151#define PCLK_MSCL_0 21
152#define PCLK_MSCL_1 22
153#define PCLK_JPEG 23
154#define PCLK_G2D 24
155#define PCLK_QE_MSCL_0 25
156#define PCLK_QE_MSCL_1 26
157#define PCLK_QE_JPEG 27
158#define PCLK_QE_G2D 28
159#define PCLK_PPMU_MSCL_0 29
160#define PCLK_PPMU_MSCL_1 30
161#define PCLK_AXI2ACEL_BRIDGE 31
162#define PCLK_PMU_MSCL 32
163#define MSCL_NR_CLK 33
164
165/* AUD */
166#define SCLK_I2S 1
167#define SCLK_PCM 2
168#define PCLK_I2S 3
169#define PCLK_PCM 4
170#define ACLK_ADMA 5
171#define AUD_NR_CLK 6
92#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 172#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
index b857cadb0bd4..04fb29ae30e6 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -238,7 +238,6 @@
238#define PLL0_VOTE 221 238#define PLL0_VOTE 221
239#define PLL3 222 239#define PLL3 222
240#define PLL3_VOTE 223 240#define PLL3_VOTE 223
241#define PLL4 224
242#define PLL4_VOTE 225 241#define PLL4_VOTE 225
243#define PLL8 226 242#define PLL8 226
244#define PLL8_VOTE 227 243#define PLL8_VOTE 227
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000000..4e944b85c56d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
15#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SPDIF_SRC 9
27#define SPDIF_CLK 10
28#define AHBIX_CLK 11
29
30#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000000..4fb2aa64d9fe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
15#define _DT_BINDINGS_CLK_LCC_MSM8960_H
16
17#define PLL4 0
18#define MI2S_OSR_SRC 1
19#define MI2S_OSR_CLK 2
20#define MI2S_DIV_CLK 3
21#define MI2S_BIT_DIV_CLK 4
22#define MI2S_BIT_CLK 5
23#define PCM_SRC 6
24#define PCM_CLK_OUT 7
25#define PCM_CLK 8
26#define SLIMBUS_SRC 9
27#define AUDIO_SLIMBUS_CLK 10
28#define SPS_SLIMBUS_CLK 11
29#define CODEC_I2S_MIC_OSR_SRC 12
30#define CODEC_I2S_MIC_OSR_CLK 13
31#define CODEC_I2S_MIC_DIV_CLK 14
32#define CODEC_I2S_MIC_BIT_DIV_CLK 15
33#define CODEC_I2S_MIC_BIT_CLK 16
34#define SPARE_I2S_MIC_OSR_SRC 17
35#define SPARE_I2S_MIC_OSR_CLK 18
36#define SPARE_I2S_MIC_DIV_CLK 19
37#define SPARE_I2S_MIC_BIT_DIV_CLK 20
38#define SPARE_I2S_MIC_BIT_CLK 21
39#define CODEC_I2S_SPKR_OSR_SRC 22
40#define CODEC_I2S_SPKR_OSR_CLK 23
41#define CODEC_I2S_SPKR_DIV_CLK 24
42#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
43#define CODEC_I2S_SPKR_BIT_CLK 26
44#define SPARE_I2S_SPKR_OSR_SRC 27
45#define SPARE_I2S_SPKR_OSR_CLK 28
46#define SPARE_I2S_SPKR_DIV_CLK 29
47#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
48#define SPARE_I2S_SPKR_BIT_CLK 31
49
50#endif
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index c27b3b5133b9..91940271cf83 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -97,6 +97,7 @@
97#define R8A7790_CLK_LVDS0 26 97#define R8A7790_CLK_LVDS0 26
98 98
99/* MSTP8 */ 99/* MSTP8 */
100#define R8A7790_CLK_MLB 2
100#define R8A7790_CLK_VIN3 8 101#define R8A7790_CLK_VIN3 8
101#define R8A7790_CLK_VIN2 9 102#define R8A7790_CLK_VIN2 9
102#define R8A7790_CLK_VIN1 10 103#define R8A7790_CLK_VIN1 10
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 3ea2bbc0da3f..f096f3f6c16a 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -91,6 +91,8 @@
91#define R8A7791_CLK_LVDS0 26 91#define R8A7791_CLK_LVDS0 26
92 92
93/* MSTP8 */ 93/* MSTP8 */
94#define R8A7791_CLK_IPMMU_SGX 0
95#define R8A7791_CLK_MLB 2
94#define R8A7791_CLK_VIN2 9 96#define R8A7791_CLK_VIN2 9
95#define R8A7791_CLK_VIN1 10 97#define R8A7791_CLK_VIN1 10
96#define R8A7791_CLK_VIN0 11 98#define R8A7791_CLK_VIN0 11
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index aa9c286e60c0..d63323032d6e 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -48,15 +48,25 @@
48#define R8A7794_CLK_SCIFB1 7 48#define R8A7794_CLK_SCIFB1 7
49#define R8A7794_CLK_MSIOF1 8 49#define R8A7794_CLK_MSIOF1 8
50#define R8A7794_CLK_SCIFB2 16 50#define R8A7794_CLK_SCIFB2 16
51#define R8A7794_CLK_SYS_DMAC1 18
52#define R8A7794_CLK_SYS_DMAC0 19
51 53
52/* MSTP3 */ 54/* MSTP3 */
55#define R8A7794_CLK_SDHI2 11
56#define R8A7794_CLK_SDHI1 12
57#define R8A7794_CLK_SDHI0 14
58#define R8A7794_CLK_MMCIF0 15
53#define R8A7794_CLK_CMT1 29 59#define R8A7794_CLK_CMT1 29
60#define R8A7794_CLK_USBDMAC0 30
61#define R8A7794_CLK_USBDMAC1 31
54 62
55/* MSTP5 */ 63/* MSTP5 */
56#define R8A7794_CLK_THERMAL 22 64#define R8A7794_CLK_THERMAL 22
57#define R8A7794_CLK_PWM 23 65#define R8A7794_CLK_PWM 23
58 66
59/* MSTP7 */ 67/* MSTP7 */
68#define R8A7794_CLK_EHCI 3
69#define R8A7794_CLK_HSUSB 4
60#define R8A7794_CLK_HSCIF2 13 70#define R8A7794_CLK_HSCIF2 13
61#define R8A7794_CLK_SCIF5 14 71#define R8A7794_CLK_SCIF5 14
62#define R8A7794_CLK_SCIF4 15 72#define R8A7794_CLK_SCIF4 15
@@ -80,6 +90,13 @@
80#define R8A7794_CLK_GPIO2 10 90#define R8A7794_CLK_GPIO2 10
81#define R8A7794_CLK_GPIO1 11 91#define R8A7794_CLK_GPIO1 11
82#define R8A7794_CLK_GPIO0 12 92#define R8A7794_CLK_GPIO0 12
93#define R8A7794_CLK_QSPI_MOD 17
94#define R8A7794_CLK_I2C5 25
95#define R8A7794_CLK_I2C4 27
96#define R8A7794_CLK_I2C3 28
97#define R8A7794_CLK_I2C2 29
98#define R8A7794_CLK_I2C1 30
99#define R8A7794_CLK_I2C0 31
83 100
84/* MSTP11 */ 101/* MSTP11 */
85#define R8A7794_CLK_SCIFA3 6 102#define R8A7794_CLK_SCIFA3 6
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
index f60ce72a2b2c..dea419708d73 100644
--- a/include/dt-bindings/clock/rk3288-cru.h
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -80,6 +80,12 @@
80#define SCLK_SDIO0_SAMPLE 119 80#define SCLK_SDIO0_SAMPLE 119
81#define SCLK_SDIO1_SAMPLE 120 81#define SCLK_SDIO1_SAMPLE 120
82#define SCLK_EMMC_SAMPLE 121 82#define SCLK_EMMC_SAMPLE 121
83#define SCLK_USBPHY480M_SRC 122
84#define SCLK_PVTM_CORE 123
85#define SCLK_PVTM_GPU 124
86
87#define SCLK_MAC 151
88#define SCLK_MACREF_OUT 152
83 89
84#define DCLK_VOP0 190 90#define DCLK_VOP0 190
85#define DCLK_VOP1 191 91#define DCLK_VOP1 191
@@ -154,6 +160,7 @@
154#define PCLK_PUBL0 365 160#define PCLK_PUBL0 365
155#define PCLK_DDRUPCTL1 366 161#define PCLK_DDRUPCTL1 366
156#define PCLK_PUBL1 367 162#define PCLK_PUBL1 367
163#define PCLK_WDT 368
157 164
158/* hclk gates */ 165/* hclk gates */
159#define HCLK_GPS 448 166#define HCLK_GPS 448
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
new file mode 100644
index 000000000000..1dd3eb2b7d90
--- /dev/null
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -0,0 +1,79 @@
1/*
2 * Copyright 2014 Ulrich Hecht
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
11#define __DT_BINDINGS_CLOCK_SH73A0_H__
12
13/* CPG */
14#define SH73A0_CLK_MAIN 0
15#define SH73A0_CLK_PLL0 1
16#define SH73A0_CLK_PLL1 2
17#define SH73A0_CLK_PLL2 3
18#define SH73A0_CLK_PLL3 4
19#define SH73A0_CLK_DSI0PHY 5
20#define SH73A0_CLK_DSI1PHY 6
21#define SH73A0_CLK_ZG 7
22#define SH73A0_CLK_M3 8
23#define SH73A0_CLK_B 9
24#define SH73A0_CLK_M1 10
25#define SH73A0_CLK_M2 11
26#define SH73A0_CLK_Z 12
27#define SH73A0_CLK_ZX 13
28#define SH73A0_CLK_HP 14
29
30/* MSTP0 */
31#define SH73A0_CLK_IIC2 1
32
33/* MSTP1 */
34#define SH73A0_CLK_CEU1 29
35#define SH73A0_CLK_CSI2_RX1 28
36#define SH73A0_CLK_CEU0 27
37#define SH73A0_CLK_CSI2_RX0 26
38#define SH73A0_CLK_TMU0 25
39#define SH73A0_CLK_DSITX0 18
40#define SH73A0_CLK_IIC0 16
41#define SH73A0_CLK_SGX 12
42#define SH73A0_CLK_LCDC0 0
43
44/* MSTP2 */
45#define SH73A0_CLK_SCIFA7 19
46#define SH73A0_CLK_SY_DMAC 18
47#define SH73A0_CLK_MP_DMAC 17
48#define SH73A0_CLK_SCIFA5 7
49#define SH73A0_CLK_SCIFB 6
50#define SH73A0_CLK_SCIFA0 4
51#define SH73A0_CLK_SCIFA1 3
52#define SH73A0_CLK_SCIFA2 2
53#define SH73A0_CLK_SCIFA3 1
54#define SH73A0_CLK_SCIFA4 0
55
56/* MSTP3 */
57#define SH73A0_CLK_SCIFA6 31
58#define SH73A0_CLK_CMT1 29
59#define SH73A0_CLK_FSI 28
60#define SH73A0_CLK_IRDA 25
61#define SH73A0_CLK_IIC1 23
62#define SH73A0_CLK_USB 22
63#define SH73A0_CLK_FLCTL 15
64#define SH73A0_CLK_SDHI0 14
65#define SH73A0_CLK_SDHI1 13
66#define SH73A0_CLK_MMCIF0 12
67#define SH73A0_CLK_SDHI2 11
68#define SH73A0_CLK_TPU0 4
69#define SH73A0_CLK_TPU1 3
70#define SH73A0_CLK_TPU2 2
71#define SH73A0_CLK_TPU3 1
72#define SH73A0_CLK_TPU4 0
73
74/* MSTP4 */
75#define SH73A0_CLK_IIC3 11
76#define SH73A0_CLK_IIC4 10
77#define SH73A0_CLK_KEYSC 3
78
79#endif
diff --git a/include/dt-bindings/clock/stih418-clks.h b/include/dt-bindings/clock/stih418-clks.h
new file mode 100644
index 000000000000..b62aa0b20217
--- /dev/null
+++ b/include/dt-bindings/clock/stih418-clks.h
@@ -0,0 +1,34 @@
1/*
2 * This header provides constants clk index STMicroelectronics
3 * STiH418 SoC.
4 */
5#ifndef _DT_BINDINGS_CLK_STIH418
6#define _DT_BINDINGS_CLK_STIH418
7
8#include "stih410-clks.h"
9
10/* STiH418 introduces new clock outputs compared to STiH410 */
11
12/* CLOCKGEN C0 */
13#define CLK_PROC_BDISP_0 14
14#define CLK_PROC_BDISP_1 15
15#define CLK_TX_ICN_1 23
16#define CLK_ETH_PHYREF 27
17#define CLK_PP_HEVC 35
18#define CLK_CLUST_HEVC 36
19#define CLK_HWPE_HEVC 37
20#define CLK_FC_HEVC 38
21#define CLK_PROC_MIXER 39
22#define CLK_PROC_SC 40
23#define CLK_AVSP_HEVC 41
24
25/* CLOCKGEN D2 */
26#undef CLK_PIX_PIP
27#undef CLK_PIX_GDP1
28#undef CLK_PIX_GDP2
29#undef CLK_PIX_GDP3
30#undef CLK_PIX_GDP4
31
32#define CLK_TMDS_HDMI_DIV2 5
33#define CLK_VP9 47
34#endif
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 000000000000..ae2eb17a1658
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,345 @@
1/*
2 * This header provides constants for binding nvidia,tegra124-car or
3 * nvidia,tegra132-car.
4 *
5 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
6 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
7 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
8 * this case, those clocks are assigned IDs above 185 in order to highlight
9 * this issue. Implementations that interpret these clock IDs as bit values
10 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
11 * explicitly handle these special cases.
12 *
13 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
14 * above.
15 */
16
17#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
18#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
19
20/* 0 */
21/* 1 */
22/* 2 */
23#define TEGRA124_CLK_ISPB 3
24#define TEGRA124_CLK_RTC 4
25#define TEGRA124_CLK_TIMER 5
26#define TEGRA124_CLK_UARTA 6
27/* 7 (register bit affects uartb and vfir) */
28/* 8 */
29#define TEGRA124_CLK_SDMMC2 9
30/* 10 (register bit affects spdif_in and spdif_out) */
31#define TEGRA124_CLK_I2S1 11
32#define TEGRA124_CLK_I2C1 12
33/* 13 */
34#define TEGRA124_CLK_SDMMC1 14
35#define TEGRA124_CLK_SDMMC4 15
36/* 16 */
37#define TEGRA124_CLK_PWM 17
38#define TEGRA124_CLK_I2S2 18
39/* 20 (register bit affects vi and vi_sensor) */
40/* 21 */
41#define TEGRA124_CLK_USBD 22
42#define TEGRA124_CLK_ISP 23
43/* 26 */
44/* 25 */
45#define TEGRA124_CLK_DISP2 26
46#define TEGRA124_CLK_DISP1 27
47#define TEGRA124_CLK_HOST1X 28
48#define TEGRA124_CLK_VCP 29
49#define TEGRA124_CLK_I2S0 30
50/* 31 */
51
52#define TEGRA124_CLK_MC 32
53/* 33 */
54#define TEGRA124_CLK_APBDMA 34
55/* 35 */
56#define TEGRA124_CLK_KBC 36
57/* 37 */
58/* 38 */
59/* 39 (register bit affects fuse and fuse_burn) */
60#define TEGRA124_CLK_KFUSE 40
61#define TEGRA124_CLK_SBC1 41
62#define TEGRA124_CLK_NOR 42
63/* 43 */
64#define TEGRA124_CLK_SBC2 44
65/* 45 */
66#define TEGRA124_CLK_SBC3 46
67#define TEGRA124_CLK_I2C5 47
68#define TEGRA124_CLK_DSIA 48
69/* 49 */
70#define TEGRA124_CLK_MIPI 50
71#define TEGRA124_CLK_HDMI 51
72#define TEGRA124_CLK_CSI 52
73/* 53 */
74#define TEGRA124_CLK_I2C2 54
75#define TEGRA124_CLK_UARTC 55
76#define TEGRA124_CLK_MIPI_CAL 56
77#define TEGRA124_CLK_EMC 57
78#define TEGRA124_CLK_USB2 58
79#define TEGRA124_CLK_USB3 59
80/* 60 */
81#define TEGRA124_CLK_VDE 61
82#define TEGRA124_CLK_BSEA 62
83#define TEGRA124_CLK_BSEV 63
84
85/* 64 */
86#define TEGRA124_CLK_UARTD 65
87/* 66 */
88#define TEGRA124_CLK_I2C3 67
89#define TEGRA124_CLK_SBC4 68
90#define TEGRA124_CLK_SDMMC3 69
91#define TEGRA124_CLK_PCIE 70
92#define TEGRA124_CLK_OWR 71
93#define TEGRA124_CLK_AFI 72
94#define TEGRA124_CLK_CSITE 73
95/* 74 */
96/* 75 */
97#define TEGRA124_CLK_LA 76
98#define TEGRA124_CLK_TRACE 77
99#define TEGRA124_CLK_SOC_THERM 78
100#define TEGRA124_CLK_DTV 79
101/* 80 */
102#define TEGRA124_CLK_I2CSLOW 81
103#define TEGRA124_CLK_DSIB 82
104#define TEGRA124_CLK_TSEC 83
105/* 84 */
106/* 85 */
107/* 86 */
108/* 87 */
109/* 88 */
110#define TEGRA124_CLK_XUSB_HOST 89
111/* 90 */
112#define TEGRA124_CLK_MSENC 91
113#define TEGRA124_CLK_CSUS 92
114/* 93 */
115/* 94 */
116/* 95 (bit affects xusb_dev and xusb_dev_src) */
117
118/* 96 */
119/* 97 */
120/* 98 */
121#define TEGRA124_CLK_MSELECT 99
122#define TEGRA124_CLK_TSENSOR 100
123#define TEGRA124_CLK_I2S3 101
124#define TEGRA124_CLK_I2S4 102
125#define TEGRA124_CLK_I2C4 103
126#define TEGRA124_CLK_SBC5 104
127#define TEGRA124_CLK_SBC6 105
128#define TEGRA124_CLK_D_AUDIO 106
129#define TEGRA124_CLK_APBIF 107
130#define TEGRA124_CLK_DAM0 108
131#define TEGRA124_CLK_DAM1 109
132#define TEGRA124_CLK_DAM2 110
133#define TEGRA124_CLK_HDA2CODEC_2X 111
134/* 112 */
135#define TEGRA124_CLK_AUDIO0_2X 113
136#define TEGRA124_CLK_AUDIO1_2X 114
137#define TEGRA124_CLK_AUDIO2_2X 115
138#define TEGRA124_CLK_AUDIO3_2X 116
139#define TEGRA124_CLK_AUDIO4_2X 117
140#define TEGRA124_CLK_SPDIF_2X 118
141#define TEGRA124_CLK_ACTMON 119
142#define TEGRA124_CLK_EXTERN1 120
143#define TEGRA124_CLK_EXTERN2 121
144#define TEGRA124_CLK_EXTERN3 122
145#define TEGRA124_CLK_SATA_OOB 123
146#define TEGRA124_CLK_SATA 124
147#define TEGRA124_CLK_HDA 125
148/* 126 */
149#define TEGRA124_CLK_SE 127
150
151#define TEGRA124_CLK_HDA2HDMI 128
152#define TEGRA124_CLK_SATA_COLD 129
153/* 130 */
154/* 131 */
155/* 132 */
156/* 133 */
157/* 134 */
158/* 135 */
159/* 136 */
160/* 137 */
161/* 138 */
162/* 139 */
163/* 140 */
164/* 141 */
165/* 142 */
166/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
167/* xusb_host_src and xusb_ss_src) */
168#define TEGRA124_CLK_CILAB 144
169#define TEGRA124_CLK_CILCD 145
170#define TEGRA124_CLK_CILE 146
171#define TEGRA124_CLK_DSIALP 147
172#define TEGRA124_CLK_DSIBLP 148
173#define TEGRA124_CLK_ENTROPY 149
174#define TEGRA124_CLK_DDS 150
175/* 151 */
176#define TEGRA124_CLK_DP2 152
177#define TEGRA124_CLK_AMX 153
178#define TEGRA124_CLK_ADX 154
179/* 155 (bit affects dfll_ref and dfll_soc) */
180#define TEGRA124_CLK_XUSB_SS 156
181/* 157 */
182/* 158 */
183/* 159 */
184
185/* 160 */
186/* 161 */
187/* 162 */
188/* 163 */
189/* 164 */
190/* 165 */
191#define TEGRA124_CLK_I2C6 166
192/* 167 */
193/* 168 */
194/* 169 */
195/* 170 */
196#define TEGRA124_CLK_VIM2_CLK 171
197/* 172 */
198/* 173 */
199/* 174 */
200/* 175 */
201#define TEGRA124_CLK_HDMI_AUDIO 176
202#define TEGRA124_CLK_CLK72MHZ 177
203#define TEGRA124_CLK_VIC03 178
204/* 179 */
205#define TEGRA124_CLK_ADX1 180
206#define TEGRA124_CLK_DPAUX 181
207#define TEGRA124_CLK_SOR0 182
208/* 183 */
209#define TEGRA124_CLK_GPU 184
210#define TEGRA124_CLK_AMX1 185
211/* 186 */
212/* 187 */
213/* 188 */
214/* 189 */
215/* 190 */
216/* 191 */
217#define TEGRA124_CLK_UARTB 192
218#define TEGRA124_CLK_VFIR 193
219#define TEGRA124_CLK_SPDIF_IN 194
220#define TEGRA124_CLK_SPDIF_OUT 195
221#define TEGRA124_CLK_VI 196
222#define TEGRA124_CLK_VI_SENSOR 197
223#define TEGRA124_CLK_FUSE 198
224#define TEGRA124_CLK_FUSE_BURN 199
225#define TEGRA124_CLK_CLK_32K 200
226#define TEGRA124_CLK_CLK_M 201
227#define TEGRA124_CLK_CLK_M_DIV2 202
228#define TEGRA124_CLK_CLK_M_DIV4 203
229#define TEGRA124_CLK_PLL_REF 204
230#define TEGRA124_CLK_PLL_C 205
231#define TEGRA124_CLK_PLL_C_OUT1 206
232#define TEGRA124_CLK_PLL_C2 207
233#define TEGRA124_CLK_PLL_C3 208
234#define TEGRA124_CLK_PLL_M 209
235#define TEGRA124_CLK_PLL_M_OUT1 210
236#define TEGRA124_CLK_PLL_P 211
237#define TEGRA124_CLK_PLL_P_OUT1 212
238#define TEGRA124_CLK_PLL_P_OUT2 213
239#define TEGRA124_CLK_PLL_P_OUT3 214
240#define TEGRA124_CLK_PLL_P_OUT4 215
241#define TEGRA124_CLK_PLL_A 216
242#define TEGRA124_CLK_PLL_A_OUT0 217
243#define TEGRA124_CLK_PLL_D 218
244#define TEGRA124_CLK_PLL_D_OUT0 219
245#define TEGRA124_CLK_PLL_D2 220
246#define TEGRA124_CLK_PLL_D2_OUT0 221
247#define TEGRA124_CLK_PLL_U 222
248#define TEGRA124_CLK_PLL_U_480M 223
249
250#define TEGRA124_CLK_PLL_U_60M 224
251#define TEGRA124_CLK_PLL_U_48M 225
252#define TEGRA124_CLK_PLL_U_12M 226
253/* 227 */
254/* 228 */
255#define TEGRA124_CLK_PLL_RE_VCO 229
256#define TEGRA124_CLK_PLL_RE_OUT 230
257#define TEGRA124_CLK_PLL_E 231
258#define TEGRA124_CLK_SPDIF_IN_SYNC 232
259#define TEGRA124_CLK_I2S0_SYNC 233
260#define TEGRA124_CLK_I2S1_SYNC 234
261#define TEGRA124_CLK_I2S2_SYNC 235
262#define TEGRA124_CLK_I2S3_SYNC 236
263#define TEGRA124_CLK_I2S4_SYNC 237
264#define TEGRA124_CLK_VIMCLK_SYNC 238
265#define TEGRA124_CLK_AUDIO0 239
266#define TEGRA124_CLK_AUDIO1 240
267#define TEGRA124_CLK_AUDIO2 241
268#define TEGRA124_CLK_AUDIO3 242
269#define TEGRA124_CLK_AUDIO4 243
270#define TEGRA124_CLK_SPDIF 244
271#define TEGRA124_CLK_CLK_OUT_1 245
272#define TEGRA124_CLK_CLK_OUT_2 246
273#define TEGRA124_CLK_CLK_OUT_3 247
274#define TEGRA124_CLK_BLINK 248
275/* 249 */
276/* 250 */
277/* 251 */
278#define TEGRA124_CLK_XUSB_HOST_SRC 252
279#define TEGRA124_CLK_XUSB_FALCON_SRC 253
280#define TEGRA124_CLK_XUSB_FS_SRC 254
281#define TEGRA124_CLK_XUSB_SS_SRC 255
282
283#define TEGRA124_CLK_XUSB_DEV_SRC 256
284#define TEGRA124_CLK_XUSB_DEV 257
285#define TEGRA124_CLK_XUSB_HS_SRC 258
286#define TEGRA124_CLK_SCLK 259
287#define TEGRA124_CLK_HCLK 260
288#define TEGRA124_CLK_PCLK 261
289/* 262 */
290/* 263 */
291#define TEGRA124_CLK_DFLL_REF 264
292#define TEGRA124_CLK_DFLL_SOC 265
293#define TEGRA124_CLK_VI_SENSOR2 266
294#define TEGRA124_CLK_PLL_P_OUT5 267
295#define TEGRA124_CLK_CML0 268
296#define TEGRA124_CLK_CML1 269
297#define TEGRA124_CLK_PLL_C4 270
298#define TEGRA124_CLK_PLL_DP 271
299#define TEGRA124_CLK_PLL_E_MUX 272
300#define TEGRA124_CLK_PLLD_DSI 273
301/* 274 */
302/* 275 */
303/* 276 */
304/* 277 */
305/* 278 */
306/* 279 */
307/* 280 */
308/* 281 */
309/* 282 */
310/* 283 */
311/* 284 */
312/* 285 */
313/* 286 */
314/* 287 */
315
316/* 288 */
317/* 289 */
318/* 290 */
319/* 291 */
320/* 292 */
321/* 293 */
322/* 294 */
323/* 295 */
324/* 296 */
325/* 297 */
326/* 298 */
327/* 299 */
328#define TEGRA124_CLK_AUDIO0_MUX 300
329#define TEGRA124_CLK_AUDIO1_MUX 301
330#define TEGRA124_CLK_AUDIO2_MUX 302
331#define TEGRA124_CLK_AUDIO3_MUX 303
332#define TEGRA124_CLK_AUDIO4_MUX 304
333#define TEGRA124_CLK_SPDIF_MUX 305
334#define TEGRA124_CLK_CLK_OUT_1_MUX 306
335#define TEGRA124_CLK_CLK_OUT_2_MUX 307
336#define TEGRA124_CLK_CLK_OUT_3_MUX 308
337/* 309 */
338/* 310 */
339#define TEGRA124_CLK_SOR0_LVDS 311
340#define TEGRA124_CLK_XUSB_SS_DIV2 312
341
342#define TEGRA124_CLK_PLL_M_UD 313
343#define TEGRA124_CLK_PLL_C_UD 314
344
345#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index af9bc9a3ddbc..2860737f0443 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -1,346 +1,19 @@
1/* 1/*
2 * This header provides constants for binding nvidia,tegra124-car. 2 * This header provides Tegra124-specific constants for binding
3 * 3 * nvidia,tegra124-car.
4 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
5 * registers. These IDs often match those in the CAR's RST_DEVICES registers,
6 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
7 * this case, those clocks are assigned IDs above 185 in order to highlight
8 * this issue. Implementations that interpret these clock IDs as bit values
9 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
10 * explicitly handle these special cases.
11 *
12 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
13 * above.
14 */ 4 */
15 5
6#include <dt-bindings/clock/tegra124-car-common.h>
7
16#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H 8#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
17#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H 9#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
18 10
19/* 0 */ 11#define TEGRA124_CLK_PLL_X 227
20/* 1 */ 12#define TEGRA124_CLK_PLL_X_OUT0 228
21/* 2 */
22#define TEGRA124_CLK_ISPB 3
23#define TEGRA124_CLK_RTC 4
24#define TEGRA124_CLK_TIMER 5
25#define TEGRA124_CLK_UARTA 6
26/* 7 (register bit affects uartb and vfir) */
27/* 8 */
28#define TEGRA124_CLK_SDMMC2 9
29/* 10 (register bit affects spdif_in and spdif_out) */
30#define TEGRA124_CLK_I2S1 11
31#define TEGRA124_CLK_I2C1 12
32/* 13 */
33#define TEGRA124_CLK_SDMMC1 14
34#define TEGRA124_CLK_SDMMC4 15
35/* 16 */
36#define TEGRA124_CLK_PWM 17
37#define TEGRA124_CLK_I2S2 18
38/* 20 (register bit affects vi and vi_sensor) */
39/* 21 */
40#define TEGRA124_CLK_USBD 22
41#define TEGRA124_CLK_ISP 23
42/* 26 */
43/* 25 */
44#define TEGRA124_CLK_DISP2 26
45#define TEGRA124_CLK_DISP1 27
46#define TEGRA124_CLK_HOST1X 28
47#define TEGRA124_CLK_VCP 29
48#define TEGRA124_CLK_I2S0 30
49/* 31 */
50
51#define TEGRA124_CLK_MC 32
52/* 33 */
53#define TEGRA124_CLK_APBDMA 34
54/* 35 */
55#define TEGRA124_CLK_KBC 36
56/* 37 */
57/* 38 */
58/* 39 (register bit affects fuse and fuse_burn) */
59#define TEGRA124_CLK_KFUSE 40
60#define TEGRA124_CLK_SBC1 41
61#define TEGRA124_CLK_NOR 42
62/* 43 */
63#define TEGRA124_CLK_SBC2 44
64/* 45 */
65#define TEGRA124_CLK_SBC3 46
66#define TEGRA124_CLK_I2C5 47
67#define TEGRA124_CLK_DSIA 48
68/* 49 */
69#define TEGRA124_CLK_MIPI 50
70#define TEGRA124_CLK_HDMI 51
71#define TEGRA124_CLK_CSI 52
72/* 53 */
73#define TEGRA124_CLK_I2C2 54
74#define TEGRA124_CLK_UARTC 55
75#define TEGRA124_CLK_MIPI_CAL 56
76#define TEGRA124_CLK_EMC 57
77#define TEGRA124_CLK_USB2 58
78#define TEGRA124_CLK_USB3 59
79/* 60 */
80#define TEGRA124_CLK_VDE 61
81#define TEGRA124_CLK_BSEA 62
82#define TEGRA124_CLK_BSEV 63
83
84/* 64 */
85#define TEGRA124_CLK_UARTD 65
86/* 66 */
87#define TEGRA124_CLK_I2C3 67
88#define TEGRA124_CLK_SBC4 68
89#define TEGRA124_CLK_SDMMC3 69
90#define TEGRA124_CLK_PCIE 70
91#define TEGRA124_CLK_OWR 71
92#define TEGRA124_CLK_AFI 72
93#define TEGRA124_CLK_CSITE 73
94/* 74 */
95/* 75 */
96#define TEGRA124_CLK_LA 76
97#define TEGRA124_CLK_TRACE 77
98#define TEGRA124_CLK_SOC_THERM 78
99#define TEGRA124_CLK_DTV 79
100/* 80 */
101#define TEGRA124_CLK_I2CSLOW 81
102#define TEGRA124_CLK_DSIB 82
103#define TEGRA124_CLK_TSEC 83
104/* 84 */
105/* 85 */
106/* 86 */
107/* 87 */
108/* 88 */
109#define TEGRA124_CLK_XUSB_HOST 89
110/* 90 */
111#define TEGRA124_CLK_MSENC 91
112#define TEGRA124_CLK_CSUS 92
113/* 93 */
114/* 94 */
115/* 95 (bit affects xusb_dev and xusb_dev_src) */
116
117/* 96 */
118/* 97 */
119/* 98 */
120#define TEGRA124_CLK_MSELECT 99
121#define TEGRA124_CLK_TSENSOR 100
122#define TEGRA124_CLK_I2S3 101
123#define TEGRA124_CLK_I2S4 102
124#define TEGRA124_CLK_I2C4 103
125#define TEGRA124_CLK_SBC5 104
126#define TEGRA124_CLK_SBC6 105
127#define TEGRA124_CLK_D_AUDIO 106
128#define TEGRA124_CLK_APBIF 107
129#define TEGRA124_CLK_DAM0 108
130#define TEGRA124_CLK_DAM1 109
131#define TEGRA124_CLK_DAM2 110
132#define TEGRA124_CLK_HDA2CODEC_2X 111
133/* 112 */
134#define TEGRA124_CLK_AUDIO0_2X 113
135#define TEGRA124_CLK_AUDIO1_2X 114
136#define TEGRA124_CLK_AUDIO2_2X 115
137#define TEGRA124_CLK_AUDIO3_2X 116
138#define TEGRA124_CLK_AUDIO4_2X 117
139#define TEGRA124_CLK_SPDIF_2X 118
140#define TEGRA124_CLK_ACTMON 119
141#define TEGRA124_CLK_EXTERN1 120
142#define TEGRA124_CLK_EXTERN2 121
143#define TEGRA124_CLK_EXTERN3 122
144#define TEGRA124_CLK_SATA_OOB 123
145#define TEGRA124_CLK_SATA 124
146#define TEGRA124_CLK_HDA 125
147/* 126 */
148#define TEGRA124_CLK_SE 127
149
150#define TEGRA124_CLK_HDA2HDMI 128
151#define TEGRA124_CLK_SATA_COLD 129
152/* 130 */
153/* 131 */
154/* 132 */
155/* 133 */
156/* 134 */
157/* 135 */
158/* 136 */
159/* 137 */
160/* 138 */
161/* 139 */
162/* 140 */
163/* 141 */
164/* 142 */
165/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
166/* xusb_host_src and xusb_ss_src) */
167#define TEGRA124_CLK_CILAB 144
168#define TEGRA124_CLK_CILCD 145
169#define TEGRA124_CLK_CILE 146
170#define TEGRA124_CLK_DSIALP 147
171#define TEGRA124_CLK_DSIBLP 148
172#define TEGRA124_CLK_ENTROPY 149
173#define TEGRA124_CLK_DDS 150
174/* 151 */
175#define TEGRA124_CLK_DP2 152
176#define TEGRA124_CLK_AMX 153
177#define TEGRA124_CLK_ADX 154
178/* 155 (bit affects dfll_ref and dfll_soc) */
179#define TEGRA124_CLK_XUSB_SS 156
180/* 157 */
181/* 158 */
182/* 159 */
183
184/* 160 */
185/* 161 */
186/* 162 */
187/* 163 */
188/* 164 */
189/* 165 */
190#define TEGRA124_CLK_I2C6 166
191/* 167 */
192/* 168 */
193/* 169 */
194/* 170 */
195#define TEGRA124_CLK_VIM2_CLK 171
196/* 172 */
197/* 173 */
198/* 174 */
199/* 175 */
200#define TEGRA124_CLK_HDMI_AUDIO 176
201#define TEGRA124_CLK_CLK72MHZ 177
202#define TEGRA124_CLK_VIC03 178
203/* 179 */
204#define TEGRA124_CLK_ADX1 180
205#define TEGRA124_CLK_DPAUX 181
206#define TEGRA124_CLK_SOR0 182
207/* 183 */
208#define TEGRA124_CLK_GPU 184
209#define TEGRA124_CLK_AMX1 185
210/* 186 */
211/* 187 */
212/* 188 */
213/* 189 */
214/* 190 */
215/* 191 */
216#define TEGRA124_CLK_UARTB 192
217#define TEGRA124_CLK_VFIR 193
218#define TEGRA124_CLK_SPDIF_IN 194
219#define TEGRA124_CLK_SPDIF_OUT 195
220#define TEGRA124_CLK_VI 196
221#define TEGRA124_CLK_VI_SENSOR 197
222#define TEGRA124_CLK_FUSE 198
223#define TEGRA124_CLK_FUSE_BURN 199
224#define TEGRA124_CLK_CLK_32K 200
225#define TEGRA124_CLK_CLK_M 201
226#define TEGRA124_CLK_CLK_M_DIV2 202
227#define TEGRA124_CLK_CLK_M_DIV4 203
228#define TEGRA124_CLK_PLL_REF 204
229#define TEGRA124_CLK_PLL_C 205
230#define TEGRA124_CLK_PLL_C_OUT1 206
231#define TEGRA124_CLK_PLL_C2 207
232#define TEGRA124_CLK_PLL_C3 208
233#define TEGRA124_CLK_PLL_M 209
234#define TEGRA124_CLK_PLL_M_OUT1 210
235#define TEGRA124_CLK_PLL_P 211
236#define TEGRA124_CLK_PLL_P_OUT1 212
237#define TEGRA124_CLK_PLL_P_OUT2 213
238#define TEGRA124_CLK_PLL_P_OUT3 214
239#define TEGRA124_CLK_PLL_P_OUT4 215
240#define TEGRA124_CLK_PLL_A 216
241#define TEGRA124_CLK_PLL_A_OUT0 217
242#define TEGRA124_CLK_PLL_D 218
243#define TEGRA124_CLK_PLL_D_OUT0 219
244#define TEGRA124_CLK_PLL_D2 220
245#define TEGRA124_CLK_PLL_D2_OUT0 221
246#define TEGRA124_CLK_PLL_U 222
247#define TEGRA124_CLK_PLL_U_480M 223
248
249#define TEGRA124_CLK_PLL_U_60M 224
250#define TEGRA124_CLK_PLL_U_48M 225
251#define TEGRA124_CLK_PLL_U_12M 226
252#define TEGRA124_CLK_PLL_X 227
253#define TEGRA124_CLK_PLL_X_OUT0 228
254#define TEGRA124_CLK_PLL_RE_VCO 229
255#define TEGRA124_CLK_PLL_RE_OUT 230
256#define TEGRA124_CLK_PLL_E 231
257#define TEGRA124_CLK_SPDIF_IN_SYNC 232
258#define TEGRA124_CLK_I2S0_SYNC 233
259#define TEGRA124_CLK_I2S1_SYNC 234
260#define TEGRA124_CLK_I2S2_SYNC 235
261#define TEGRA124_CLK_I2S3_SYNC 236
262#define TEGRA124_CLK_I2S4_SYNC 237
263#define TEGRA124_CLK_VIMCLK_SYNC 238
264#define TEGRA124_CLK_AUDIO0 239
265#define TEGRA124_CLK_AUDIO1 240
266#define TEGRA124_CLK_AUDIO2 241
267#define TEGRA124_CLK_AUDIO3 242
268#define TEGRA124_CLK_AUDIO4 243
269#define TEGRA124_CLK_SPDIF 244
270#define TEGRA124_CLK_CLK_OUT_1 245
271#define TEGRA124_CLK_CLK_OUT_2 246
272#define TEGRA124_CLK_CLK_OUT_3 247
273#define TEGRA124_CLK_BLINK 248
274/* 249 */
275/* 250 */
276/* 251 */
277#define TEGRA124_CLK_XUSB_HOST_SRC 252
278#define TEGRA124_CLK_XUSB_FALCON_SRC 253
279#define TEGRA124_CLK_XUSB_FS_SRC 254
280#define TEGRA124_CLK_XUSB_SS_SRC 255
281
282#define TEGRA124_CLK_XUSB_DEV_SRC 256
283#define TEGRA124_CLK_XUSB_DEV 257
284#define TEGRA124_CLK_XUSB_HS_SRC 258
285#define TEGRA124_CLK_SCLK 259
286#define TEGRA124_CLK_HCLK 260
287#define TEGRA124_CLK_PCLK 261
288#define TEGRA124_CLK_CCLK_G 262
289#define TEGRA124_CLK_CCLK_LP 263
290#define TEGRA124_CLK_DFLL_REF 264
291#define TEGRA124_CLK_DFLL_SOC 265
292#define TEGRA124_CLK_VI_SENSOR2 266
293#define TEGRA124_CLK_PLL_P_OUT5 267
294#define TEGRA124_CLK_CML0 268
295#define TEGRA124_CLK_CML1 269
296#define TEGRA124_CLK_PLL_C4 270
297#define TEGRA124_CLK_PLL_DP 271
298#define TEGRA124_CLK_PLL_E_MUX 272
299/* 273 */
300/* 274 */
301/* 275 */
302/* 276 */
303/* 277 */
304/* 278 */
305/* 279 */
306/* 280 */
307/* 281 */
308/* 282 */
309/* 283 */
310/* 284 */
311/* 285 */
312/* 286 */
313/* 287 */
314
315/* 288 */
316/* 289 */
317/* 290 */
318/* 291 */
319/* 292 */
320/* 293 */
321/* 294 */
322/* 295 */
323/* 296 */
324/* 297 */
325/* 298 */
326/* 299 */
327#define TEGRA124_CLK_AUDIO0_MUX 300
328#define TEGRA124_CLK_AUDIO1_MUX 301
329#define TEGRA124_CLK_AUDIO2_MUX 302
330#define TEGRA124_CLK_AUDIO3_MUX 303
331#define TEGRA124_CLK_AUDIO4_MUX 304
332#define TEGRA124_CLK_SPDIF_MUX 305
333#define TEGRA124_CLK_CLK_OUT_1_MUX 306
334#define TEGRA124_CLK_CLK_OUT_2_MUX 307
335#define TEGRA124_CLK_CLK_OUT_3_MUX 308
336#define TEGRA124_CLK_DSIA_MUX 309
337#define TEGRA124_CLK_DSIB_MUX 310
338#define TEGRA124_CLK_SOR0_LVDS 311
339#define TEGRA124_CLK_XUSB_SS_DIV2 312
340 13
341#define TEGRA124_CLK_PLL_M_UD 313 14#define TEGRA124_CLK_CCLK_G 262
342#define TEGRA124_CLK_PLL_C_UD 314 15#define TEGRA124_CLK_CCLK_LP 263
343 16
344#define TEGRA124_CLK_CLK_MAX 315 17#define TEGRA124_CLK_CLK_MAX 315
345 18
346#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ 19#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 801c0ac50c47..979d24a6799f 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -192,6 +192,7 @@
192#define VF610_PLL5_BYPASS 179 192#define VF610_PLL5_BYPASS 179
193#define VF610_PLL6_BYPASS 180 193#define VF610_PLL6_BYPASS 180
194#define VF610_PLL7_BYPASS 181 194#define VF610_PLL7_BYPASS 181
195#define VF610_CLK_END 182 195#define VF610_CLK_SNVS 182
196#define VF610_CLK_END 183
196 197
197#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 198#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/dma/sun4i-a10.h b/include/dt-bindings/dma/sun4i-a10.h
new file mode 100644
index 000000000000..8caba9ef7e9d
--- /dev/null
+++ b/include/dt-bindings/dma/sun4i-a10.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright 2014 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_
51#define __DT_BINDINGS_DMA_SUN4I_A10_H_
52
53#define SUN4I_DMA_NORMAL 0
54#define SUN4I_DMA_DEDICATED 1
55
56#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/gpio/meson8-gpio.h b/include/dt-bindings/gpio/meson8-gpio.h
new file mode 100644
index 000000000000..fdaeb5cbf5e1
--- /dev/null
+++ b/include/dt-bindings/gpio/meson8-gpio.h
@@ -0,0 +1,157 @@
1/*
2 * GPIO definitions for Amlogic Meson8 SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#ifndef _DT_BINDINGS_MESON8_GPIO_H
15#define _DT_BINDINGS_MESON8_GPIO_H
16
17/* First GPIO chip */
18#define GPIOX_0 0
19#define GPIOX_1 1
20#define GPIOX_2 2
21#define GPIOX_3 3
22#define GPIOX_4 4
23#define GPIOX_5 5
24#define GPIOX_6 6
25#define GPIOX_7 7
26#define GPIOX_8 8
27#define GPIOX_9 9
28#define GPIOX_10 10
29#define GPIOX_11 11
30#define GPIOX_12 12
31#define GPIOX_13 13
32#define GPIOX_14 14
33#define GPIOX_15 15
34#define GPIOX_16 16
35#define GPIOX_17 17
36#define GPIOX_18 18
37#define GPIOX_19 19
38#define GPIOX_20 20
39#define GPIOX_21 21
40#define GPIOY_0 22
41#define GPIOY_1 23
42#define GPIOY_2 24
43#define GPIOY_3 25
44#define GPIOY_4 26
45#define GPIOY_5 27
46#define GPIOY_6 28
47#define GPIOY_7 29
48#define GPIOY_8 30
49#define GPIOY_9 31
50#define GPIOY_10 32
51#define GPIOY_11 33
52#define GPIOY_12 34
53#define GPIOY_13 35
54#define GPIOY_14 36
55#define GPIOY_15 37
56#define GPIOY_16 38
57#define GPIODV_0 39
58#define GPIODV_1 40
59#define GPIODV_2 41
60#define GPIODV_3 42
61#define GPIODV_4 43
62#define GPIODV_5 44
63#define GPIODV_6 45
64#define GPIODV_7 46
65#define GPIODV_8 47
66#define GPIODV_9 48
67#define GPIODV_10 49
68#define GPIODV_11 50
69#define GPIODV_12 51
70#define GPIODV_13 52
71#define GPIODV_14 53
72#define GPIODV_15 54
73#define GPIODV_16 55
74#define GPIODV_17 56
75#define GPIODV_18 57
76#define GPIODV_19 58
77#define GPIODV_20 59
78#define GPIODV_21 60
79#define GPIODV_22 61
80#define GPIODV_23 62
81#define GPIODV_24 63
82#define GPIODV_25 64
83#define GPIODV_26 65
84#define GPIODV_27 66
85#define GPIODV_28 67
86#define GPIODV_29 68
87#define GPIOH_0 69
88#define GPIOH_1 70
89#define GPIOH_2 71
90#define GPIOH_3 72
91#define GPIOH_4 73
92#define GPIOH_5 74
93#define GPIOH_6 75
94#define GPIOH_7 76
95#define GPIOH_8 77
96#define GPIOH_9 78
97#define GPIOZ_0 79
98#define GPIOZ_1 80
99#define GPIOZ_2 81
100#define GPIOZ_3 82
101#define GPIOZ_4 83
102#define GPIOZ_5 84
103#define GPIOZ_6 85
104#define GPIOZ_7 86
105#define GPIOZ_8 87
106#define GPIOZ_9 88
107#define GPIOZ_10 89
108#define GPIOZ_11 90
109#define GPIOZ_12 91
110#define GPIOZ_13 92
111#define GPIOZ_14 93
112#define CARD_0 94
113#define CARD_1 95
114#define CARD_2 96
115#define CARD_3 97
116#define CARD_4 98
117#define CARD_5 99
118#define CARD_6 100
119#define BOOT_0 101
120#define BOOT_1 102
121#define BOOT_2 103
122#define BOOT_3 104
123#define BOOT_4 105
124#define BOOT_5 106
125#define BOOT_6 107
126#define BOOT_7 108
127#define BOOT_8 109
128#define BOOT_9 110
129#define BOOT_10 111
130#define BOOT_11 112
131#define BOOT_12 113
132#define BOOT_13 114
133#define BOOT_14 115
134#define BOOT_15 116
135#define BOOT_16 117
136#define BOOT_17 118
137#define BOOT_18 119
138
139/* Second GPIO chip */
140#define GPIOAO_0 0
141#define GPIOAO_1 1
142#define GPIOAO_2 2
143#define GPIOAO_3 3
144#define GPIOAO_4 4
145#define GPIOAO_5 5
146#define GPIOAO_6 6
147#define GPIOAO_7 7
148#define GPIOAO_8 8
149#define GPIOAO_9 9
150#define GPIOAO_10 10
151#define GPIOAO_11 11
152#define GPIOAO_12 12
153#define GPIOAO_13 13
154#define GPIO_BSD_EN 14
155#define GPIO_TEST_N 15
156
157#endif /* _DT_BINDINGS_MESON8_GPIO_H */
diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h
new file mode 100644
index 000000000000..42121fa238fa
--- /dev/null
+++ b/include/dt-bindings/iio/qcom,spmi-vadc.h
@@ -0,0 +1,119 @@
1/*
2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
15#define _DT_BINDINGS_QCOM_SPMI_VADC_H
16
17/* Voltage ADC channels */
18#define VADC_USBIN 0x00
19#define VADC_DCIN 0x01
20#define VADC_VCHG_SNS 0x02
21#define VADC_SPARE1_03 0x03
22#define VADC_USB_ID_MV 0x04
23#define VADC_VCOIN 0x05
24#define VADC_VBAT_SNS 0x06
25#define VADC_VSYS 0x07
26#define VADC_DIE_TEMP 0x08
27#define VADC_REF_625MV 0x09
28#define VADC_REF_1250MV 0x0a
29#define VADC_CHG_TEMP 0x0b
30#define VADC_SPARE1 0x0c
31#define VADC_SPARE2 0x0d
32#define VADC_GND_REF 0x0e
33#define VADC_VDD_VADC 0x0f
34
35#define VADC_P_MUX1_1_1 0x10
36#define VADC_P_MUX2_1_1 0x11
37#define VADC_P_MUX3_1_1 0x12
38#define VADC_P_MUX4_1_1 0x13
39#define VADC_P_MUX5_1_1 0x14
40#define VADC_P_MUX6_1_1 0x15
41#define VADC_P_MUX7_1_1 0x16
42#define VADC_P_MUX8_1_1 0x17
43#define VADC_P_MUX9_1_1 0x18
44#define VADC_P_MUX10_1_1 0x19
45#define VADC_P_MUX11_1_1 0x1a
46#define VADC_P_MUX12_1_1 0x1b
47#define VADC_P_MUX13_1_1 0x1c
48#define VADC_P_MUX14_1_1 0x1d
49#define VADC_P_MUX15_1_1 0x1e
50#define VADC_P_MUX16_1_1 0x1f
51
52#define VADC_P_MUX1_1_3 0x20
53#define VADC_P_MUX2_1_3 0x21
54#define VADC_P_MUX3_1_3 0x22
55#define VADC_P_MUX4_1_3 0x23
56#define VADC_P_MUX5_1_3 0x24
57#define VADC_P_MUX6_1_3 0x25
58#define VADC_P_MUX7_1_3 0x26
59#define VADC_P_MUX8_1_3 0x27
60#define VADC_P_MUX9_1_3 0x28
61#define VADC_P_MUX10_1_3 0x29
62#define VADC_P_MUX11_1_3 0x2a
63#define VADC_P_MUX12_1_3 0x2b
64#define VADC_P_MUX13_1_3 0x2c
65#define VADC_P_MUX14_1_3 0x2d
66#define VADC_P_MUX15_1_3 0x2e
67#define VADC_P_MUX16_1_3 0x2f
68
69#define VADC_LR_MUX1_BAT_THERM 0x30
70#define VADC_LR_MUX2_BAT_ID 0x31
71#define VADC_LR_MUX3_XO_THERM 0x32
72#define VADC_LR_MUX4_AMUX_THM1 0x33
73#define VADC_LR_MUX5_AMUX_THM2 0x34
74#define VADC_LR_MUX6_AMUX_THM3 0x35
75#define VADC_LR_MUX7_HW_ID 0x36
76#define VADC_LR_MUX8_AMUX_THM4 0x37
77#define VADC_LR_MUX9_AMUX_THM5 0x38
78#define VADC_LR_MUX10_USB_ID 0x39
79#define VADC_AMUX_PU1 0x3a
80#define VADC_AMUX_PU2 0x3b
81#define VADC_LR_MUX3_BUF_XO_THERM 0x3c
82
83#define VADC_LR_MUX1_PU1_BAT_THERM 0x70
84#define VADC_LR_MUX2_PU1_BAT_ID 0x71
85#define VADC_LR_MUX3_PU1_XO_THERM 0x72
86#define VADC_LR_MUX4_PU1_AMUX_THM1 0x73
87#define VADC_LR_MUX5_PU1_AMUX_THM2 0x74
88#define VADC_LR_MUX6_PU1_AMUX_THM3 0x75
89#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x76
90#define VADC_LR_MUX8_PU1_AMUX_THM4 0x77
91#define VADC_LR_MUX9_PU1_AMUX_THM5 0x78
92#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x79
93#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c
94
95#define VADC_LR_MUX1_PU2_BAT_THERM 0xb0
96#define VADC_LR_MUX2_PU2_BAT_ID 0xb1
97#define VADC_LR_MUX3_PU2_XO_THERM 0xb2
98#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb3
99#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb4
100#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb5
101#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb6
102#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb7
103#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb8
104#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb9
105#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc
106
107#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf0
108#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1
109#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2
110#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3
111#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4
112#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5
113#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6
114#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7
115#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8
116#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9
117#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc
118
119#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index 1ea1b702fec2..d4110d5caa3e 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -7,14 +7,14 @@
7 7
8#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/interrupt-controller/irq.h>
9 9
10/* interrupt specific cell 0 */ 10/* interrupt specifier cell 0 */
11 11
12#define GIC_SPI 0 12#define GIC_SPI 0
13#define GIC_PPI 1 13#define GIC_PPI 1
14 14
15/* 15/*
16 * Interrupt specifier cell 2. 16 * Interrupt specifier cell 2.
17 * The flaggs in irq.h are valid, plus those below. 17 * The flags in irq.h are valid, plus those below.
18 */ 18 */
19#define GIC_CPU_MASK_RAW(x) ((x) << 8) 19#define GIC_CPU_MASK_RAW(x) ((x) << 8)
20#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 20#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
diff --git a/include/dt-bindings/mfd/qcom-rpm.h b/include/dt-bindings/mfd/qcom-rpm.h
new file mode 100644
index 000000000000..388a6f3d6165
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom-rpm.h
@@ -0,0 +1,154 @@
1/*
2 * This header provides constants for the Qualcomm RPM bindings.
3 */
4
5#ifndef _DT_BINDINGS_MFD_QCOM_RPM_H
6#define _DT_BINDINGS_MFD_QCOM_RPM_H
7
8/*
9 * Constants use to identify individual resources in the RPM.
10 */
11#define QCOM_RPM_APPS_FABRIC_ARB 1
12#define QCOM_RPM_APPS_FABRIC_CLK 2
13#define QCOM_RPM_APPS_FABRIC_HALT 3
14#define QCOM_RPM_APPS_FABRIC_IOCTL 4
15#define QCOM_RPM_APPS_FABRIC_MODE 5
16#define QCOM_RPM_APPS_L2_CACHE_CTL 6
17#define QCOM_RPM_CFPB_CLK 7
18#define QCOM_RPM_CXO_BUFFERS 8
19#define QCOM_RPM_CXO_CLK 9
20#define QCOM_RPM_DAYTONA_FABRIC_CLK 10
21#define QCOM_RPM_DDR_DMM 11
22#define QCOM_RPM_EBI1_CLK 12
23#define QCOM_RPM_HDMI_SWITCH 13
24#define QCOM_RPM_MMFPB_CLK 14
25#define QCOM_RPM_MM_FABRIC_ARB 15
26#define QCOM_RPM_MM_FABRIC_CLK 16
27#define QCOM_RPM_MM_FABRIC_HALT 17
28#define QCOM_RPM_MM_FABRIC_IOCTL 18
29#define QCOM_RPM_MM_FABRIC_MODE 19
30#define QCOM_RPM_PLL_4 20
31#define QCOM_RPM_PM8058_LDO0 21
32#define QCOM_RPM_PM8058_LDO1 22
33#define QCOM_RPM_PM8058_LDO2 23
34#define QCOM_RPM_PM8058_LDO3 24
35#define QCOM_RPM_PM8058_LDO4 25
36#define QCOM_RPM_PM8058_LDO5 26
37#define QCOM_RPM_PM8058_LDO6 27
38#define QCOM_RPM_PM8058_LDO7 28
39#define QCOM_RPM_PM8058_LDO8 29
40#define QCOM_RPM_PM8058_LDO9 30
41#define QCOM_RPM_PM8058_LDO10 31
42#define QCOM_RPM_PM8058_LDO11 32
43#define QCOM_RPM_PM8058_LDO12 33
44#define QCOM_RPM_PM8058_LDO13 34
45#define QCOM_RPM_PM8058_LDO14 35
46#define QCOM_RPM_PM8058_LDO15 36
47#define QCOM_RPM_PM8058_LDO16 37
48#define QCOM_RPM_PM8058_LDO17 38
49#define QCOM_RPM_PM8058_LDO18 39
50#define QCOM_RPM_PM8058_LDO19 40
51#define QCOM_RPM_PM8058_LDO20 41
52#define QCOM_RPM_PM8058_LDO21 42
53#define QCOM_RPM_PM8058_LDO22 43
54#define QCOM_RPM_PM8058_LDO23 44
55#define QCOM_RPM_PM8058_LDO24 45
56#define QCOM_RPM_PM8058_LDO25 46
57#define QCOM_RPM_PM8058_LVS0 47
58#define QCOM_RPM_PM8058_LVS1 48
59#define QCOM_RPM_PM8058_NCP 49
60#define QCOM_RPM_PM8058_SMPS0 50
61#define QCOM_RPM_PM8058_SMPS1 51
62#define QCOM_RPM_PM8058_SMPS2 52
63#define QCOM_RPM_PM8058_SMPS3 53
64#define QCOM_RPM_PM8058_SMPS4 54
65#define QCOM_RPM_PM8821_LDO1 55
66#define QCOM_RPM_PM8821_SMPS1 56
67#define QCOM_RPM_PM8821_SMPS2 57
68#define QCOM_RPM_PM8901_LDO0 58
69#define QCOM_RPM_PM8901_LDO1 59
70#define QCOM_RPM_PM8901_LDO2 60
71#define QCOM_RPM_PM8901_LDO3 61
72#define QCOM_RPM_PM8901_LDO4 62
73#define QCOM_RPM_PM8901_LDO5 63
74#define QCOM_RPM_PM8901_LDO6 64
75#define QCOM_RPM_PM8901_LVS0 65
76#define QCOM_RPM_PM8901_LVS1 66
77#define QCOM_RPM_PM8901_LVS2 67
78#define QCOM_RPM_PM8901_LVS3 68
79#define QCOM_RPM_PM8901_MVS 69
80#define QCOM_RPM_PM8901_SMPS0 70
81#define QCOM_RPM_PM8901_SMPS1 71
82#define QCOM_RPM_PM8901_SMPS2 72
83#define QCOM_RPM_PM8901_SMPS3 73
84#define QCOM_RPM_PM8901_SMPS4 74
85#define QCOM_RPM_PM8921_CLK1 75
86#define QCOM_RPM_PM8921_CLK2 76
87#define QCOM_RPM_PM8921_LDO1 77
88#define QCOM_RPM_PM8921_LDO2 78
89#define QCOM_RPM_PM8921_LDO3 79
90#define QCOM_RPM_PM8921_LDO4 80
91#define QCOM_RPM_PM8921_LDO5 81
92#define QCOM_RPM_PM8921_LDO6 82
93#define QCOM_RPM_PM8921_LDO7 83
94#define QCOM_RPM_PM8921_LDO8 84
95#define QCOM_RPM_PM8921_LDO9 85
96#define QCOM_RPM_PM8921_LDO10 86
97#define QCOM_RPM_PM8921_LDO11 87
98#define QCOM_RPM_PM8921_LDO12 88
99#define QCOM_RPM_PM8921_LDO13 89
100#define QCOM_RPM_PM8921_LDO14 90
101#define QCOM_RPM_PM8921_LDO15 91
102#define QCOM_RPM_PM8921_LDO16 92
103#define QCOM_RPM_PM8921_LDO17 93
104#define QCOM_RPM_PM8921_LDO18 94
105#define QCOM_RPM_PM8921_LDO19 95
106#define QCOM_RPM_PM8921_LDO20 96
107#define QCOM_RPM_PM8921_LDO21 97
108#define QCOM_RPM_PM8921_LDO22 98
109#define QCOM_RPM_PM8921_LDO23 99
110#define QCOM_RPM_PM8921_LDO24 100
111#define QCOM_RPM_PM8921_LDO25 101
112#define QCOM_RPM_PM8921_LDO26 102
113#define QCOM_RPM_PM8921_LDO27 103
114#define QCOM_RPM_PM8921_LDO28 104
115#define QCOM_RPM_PM8921_LDO29 105
116#define QCOM_RPM_PM8921_LVS1 106
117#define QCOM_RPM_PM8921_LVS2 107
118#define QCOM_RPM_PM8921_LVS3 108
119#define QCOM_RPM_PM8921_LVS4 109
120#define QCOM_RPM_PM8921_LVS5 110
121#define QCOM_RPM_PM8921_LVS6 111
122#define QCOM_RPM_PM8921_LVS7 112
123#define QCOM_RPM_PM8921_MVS 113
124#define QCOM_RPM_PM8921_NCP 114
125#define QCOM_RPM_PM8921_SMPS1 115
126#define QCOM_RPM_PM8921_SMPS2 116
127#define QCOM_RPM_PM8921_SMPS3 117
128#define QCOM_RPM_PM8921_SMPS4 118
129#define QCOM_RPM_PM8921_SMPS5 119
130#define QCOM_RPM_PM8921_SMPS6 120
131#define QCOM_RPM_PM8921_SMPS7 121
132#define QCOM_RPM_PM8921_SMPS8 122
133#define QCOM_RPM_PXO_CLK 123
134#define QCOM_RPM_QDSS_CLK 124
135#define QCOM_RPM_SFPB_CLK 125
136#define QCOM_RPM_SMI_CLK 126
137#define QCOM_RPM_SYS_FABRIC_ARB 127
138#define QCOM_RPM_SYS_FABRIC_CLK 128
139#define QCOM_RPM_SYS_FABRIC_HALT 129
140#define QCOM_RPM_SYS_FABRIC_IOCTL 130
141#define QCOM_RPM_SYS_FABRIC_MODE 131
142#define QCOM_RPM_USB_OTG_SWITCH 132
143#define QCOM_RPM_VDDMIN_GPIO 133
144
145/*
146 * Constants used to select force mode for regulators.
147 */
148#define QCOM_RPM_FORCE_MODE_NONE 0
149#define QCOM_RPM_FORCE_MODE_LPM 1
150#define QCOM_RPM_FORCE_MODE_HPM 2
151#define QCOM_RPM_FORCE_MODE_AUTO 3
152#define QCOM_RPM_FORCE_MODE_BYPASS 4
153
154#endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 1c75b8ca5228..13949259705a 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -61,6 +61,7 @@
61#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) 61#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
62#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) 62#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
63#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) 63#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
64#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
64#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 65#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
65#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) 66#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
66#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) 67#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
diff --git a/include/dt-bindings/pinctrl/sun4i-a10.h b/include/dt-bindings/pinctrl/sun4i-a10.h
new file mode 100644
index 000000000000..f7553c143b40
--- /dev/null
+++ b/include/dt-bindings/pinctrl/sun4i-a10.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2014 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
51#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
52
53#define SUN4I_PINCTRL_10_MA 0
54#define SUN4I_PINCTRL_20_MA 1
55#define SUN4I_PINCTRL_30_MA 2
56#define SUN4I_PINCTRL_40_MA 3
57
58#define SUN4I_PINCTRL_NO_PULL 0
59#define SUN4I_PINCTRL_PULL_UP 1
60#define SUN4I_PINCTRL_PULL_DOWN 2
61
62#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */
diff --git a/include/dt-bindings/sound/samsung-i2s.h b/include/dt-bindings/sound/samsung-i2s.h
new file mode 100644
index 000000000000..0c69818d530c
--- /dev/null
+++ b/include/dt-bindings/sound/samsung-i2s.h
@@ -0,0 +1,8 @@
1#ifndef _DT_BINDINGS_SAMSUNG_I2S_H
2#define _DT_BINDINGS_SAMSUNG_I2S_H
3
4#define CLK_I2S_CDCLK 0
5#define CLK_I2S_RCLK_SRC 1
6#define CLK_I2S_RCLK_PSR 2
7
8#endif /* _DT_BINDINGS_SAMSUNG_I2S_H */
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h
index 59822a995858..b5e6b0069ac7 100644
--- a/include/dt-bindings/thermal/thermal.h
+++ b/include/dt-bindings/thermal/thermal.h
@@ -11,7 +11,7 @@
11#define _DT_BINDINGS_THERMAL_THERMAL_H 11#define _DT_BINDINGS_THERMAL_THERMAL_H
12 12
13/* On cooling devices upper and lower limits */ 13/* On cooling devices upper and lower limits */
14#define THERMAL_NO_LIMIT (-1UL) 14#define THERMAL_NO_LIMIT (~0)
15 15
16#endif 16#endif
17 17
diff --git a/include/dt-bindings/thermal/thermal_exynos.h b/include/dt-bindings/thermal/thermal_exynos.h
new file mode 100644
index 000000000000..0646500bca69
--- /dev/null
+++ b/include/dt-bindings/thermal/thermal_exynos.h
@@ -0,0 +1,28 @@
1/*
2 * thermal_exynos.h - Samsung EXYNOS TMU device tree definitions
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Lukasz Majewski <l.majewski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#ifndef _EXYNOS_THERMAL_TMU_DT_H
20#define _EXYNOS_THERMAL_TMU_DT_H
21
22#define TYPE_ONE_POINT_TRIMMING 0
23#define TYPE_ONE_POINT_TRIMMING_25 1
24#define TYPE_ONE_POINT_TRIMMING_85 2
25#define TYPE_TWO_POINT_TRIMMING 3
26#define TYPE_NONE 4
27
28#endif /* _EXYNOS_THERMAL_TMU_DT_H */