diff options
Diffstat (limited to 'include/dt-bindings')
30 files changed, 3388 insertions, 10 deletions
diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h new file mode 100644 index 000000000000..0b4cb999a3f7 --- /dev/null +++ b/include/dt-bindings/clk/at91.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for AT91 pmc status. | ||
| 3 | * | ||
| 4 | * The constants defined in this header are being used in dts. | ||
| 5 | * | ||
| 6 | * Licensed under GPLv2 or later. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _DT_BINDINGS_CLK_AT91_H | ||
| 10 | #define _DT_BINDINGS_CLK_AT91_H | ||
| 11 | |||
| 12 | #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ | ||
| 13 | #define AT91_PMC_LOCKA 1 /* PLLA Lock */ | ||
| 14 | #define AT91_PMC_LOCKB 2 /* PLLB Lock */ | ||
| 15 | #define AT91_PMC_MCKRDY 3 /* Master Clock */ | ||
| 16 | #define AT91_PMC_LOCKU 6 /* UPLL Lock */ | ||
| 17 | #define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ | ||
| 18 | #define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ | ||
| 19 | #define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ | ||
| 20 | #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ | ||
| 21 | |||
| 22 | #endif | ||
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f427c60f..0ae6f5a75d2a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | #define EXYNOS_SCLK_I2S 7 | 19 | #define EXYNOS_SCLK_I2S 7 |
| 20 | #define EXYNOS_PCM_BUS 8 | 20 | #define EXYNOS_PCM_BUS 8 |
| 21 | #define EXYNOS_SCLK_PCM 9 | 21 | #define EXYNOS_SCLK_PCM 9 |
| 22 | #define EXYNOS_ADMA 10 | ||
| 22 | 23 | ||
| 23 | #define EXYNOS_AUDSS_MAX_CLKS 10 | 24 | #define EXYNOS_AUDSS_MAX_CLKS 11 |
| 24 | 25 | ||
| 25 | #endif | 26 | #endif |
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h new file mode 100644 index 000000000000..75aff336dfb0 --- /dev/null +++ b/include/dt-bindings/clock/exynos4.h | |||
| @@ -0,0 +1,244 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 3 | * Author: Andrzej Haja <a.hajda@samsung.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * Device Tree binding constants for Exynos4 clock controller. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H | ||
| 13 | #define _DT_BINDINGS_CLOCK_EXYNOS_4_H | ||
| 14 | |||
| 15 | /* core clocks */ | ||
| 16 | #define CLK_XXTI 1 | ||
| 17 | #define CLK_XUSBXTI 2 | ||
| 18 | #define CLK_FIN_PLL 3 | ||
| 19 | #define CLK_FOUT_APLL 4 | ||
| 20 | #define CLK_FOUT_MPLL 5 | ||
| 21 | #define CLK_FOUT_EPLL 6 | ||
| 22 | #define CLK_FOUT_VPLL 7 | ||
| 23 | #define CLK_SCLK_APLL 8 | ||
| 24 | #define CLK_SCLK_MPLL 9 | ||
| 25 | #define CLK_SCLK_EPLL 10 | ||
| 26 | #define CLK_SCLK_VPLL 11 | ||
| 27 | #define CLK_ARM_CLK 12 | ||
| 28 | #define CLK_ACLK200 13 | ||
| 29 | #define CLK_ACLK100 14 | ||
| 30 | #define CLK_ACLK160 15 | ||
| 31 | #define CLK_ACLK133 16 | ||
| 32 | #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ | ||
| 33 | #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ | ||
| 34 | #define CLK_MOUT_CORE 19 | ||
| 35 | #define CLK_MOUT_APLL 20 | ||
| 36 | |||
| 37 | /* gate for special clocks (sclk) */ | ||
| 38 | #define CLK_SCLK_FIMC0 128 | ||
| 39 | #define CLK_SCLK_FIMC1 129 | ||
| 40 | #define CLK_SCLK_FIMC2 130 | ||
| 41 | #define CLK_SCLK_FIMC3 131 | ||
| 42 | #define CLK_SCLK_CAM0 132 | ||
| 43 | #define CLK_SCLK_CAM1 133 | ||
| 44 | #define CLK_SCLK_CSIS0 134 | ||
| 45 | #define CLK_SCLK_CSIS1 135 | ||
| 46 | #define CLK_SCLK_HDMI 136 | ||
| 47 | #define CLK_SCLK_MIXER 137 | ||
| 48 | #define CLK_SCLK_DAC 138 | ||
| 49 | #define CLK_SCLK_PIXEL 139 | ||
| 50 | #define CLK_SCLK_FIMD0 140 | ||
| 51 | #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ | ||
| 52 | #define CLK_SCLK_MDNIE_PWM0 142 | ||
| 53 | #define CLK_SCLK_MIPI0 143 | ||
| 54 | #define CLK_SCLK_AUDIO0 144 | ||
| 55 | #define CLK_SCLK_MMC0 145 | ||
| 56 | #define CLK_SCLK_MMC1 146 | ||
| 57 | #define CLK_SCLK_MMC2 147 | ||
| 58 | #define CLK_SCLK_MMC3 148 | ||
| 59 | #define CLK_SCLK_MMC4 149 | ||
| 60 | #define CLK_SCLK_SATA 150 /* Exynos4210 only */ | ||
| 61 | #define CLK_SCLK_UART0 151 | ||
| 62 | #define CLK_SCLK_UART1 152 | ||
| 63 | #define CLK_SCLK_UART2 153 | ||
| 64 | #define CLK_SCLK_UART3 154 | ||
| 65 | #define CLK_SCLK_UART4 155 | ||
| 66 | #define CLK_SCLK_AUDIO1 156 | ||
| 67 | #define CLK_SCLK_AUDIO2 157 | ||
| 68 | #define CLK_SCLK_SPDIF 158 | ||
| 69 | #define CLK_SCLK_SPI0 159 | ||
| 70 | #define CLK_SCLK_SPI1 160 | ||
| 71 | #define CLK_SCLK_SPI2 161 | ||
| 72 | #define CLK_SCLK_SLIMBUS 162 | ||
| 73 | #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ | ||
| 74 | #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ | ||
| 75 | #define CLK_SCLK_PCM1 165 | ||
| 76 | #define CLK_SCLK_PCM2 166 | ||
| 77 | #define CLK_SCLK_I2S1 167 | ||
| 78 | #define CLK_SCLK_I2S2 168 | ||
| 79 | #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ | ||
| 80 | #define CLK_SCLK_MFC 170 | ||
| 81 | #define CLK_SCLK_PCM0 171 | ||
| 82 | #define CLK_SCLK_G3D 172 | ||
| 83 | #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ | ||
| 84 | #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ | ||
| 85 | #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ | ||
| 86 | #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ | ||
| 87 | #define CLK_SCLK_FIMG2D 177 | ||
| 88 | |||
| 89 | /* gate clocks */ | ||
| 90 | #define CLK_FIMC0 256 | ||
| 91 | #define CLK_FIMC1 257 | ||
| 92 | #define CLK_FIMC2 258 | ||
| 93 | #define CLK_FIMC3 259 | ||
| 94 | #define CLK_CSIS0 260 | ||
| 95 | #define CLK_CSIS1 261 | ||
| 96 | #define CLK_JPEG 262 | ||
| 97 | #define CLK_SMMU_FIMC0 263 | ||
| 98 | #define CLK_SMMU_FIMC1 264 | ||
| 99 | #define CLK_SMMU_FIMC2 265 | ||
| 100 | #define CLK_SMMU_FIMC3 266 | ||
| 101 | #define CLK_SMMU_JPEG 267 | ||
| 102 | #define CLK_VP 268 | ||
| 103 | #define CLK_MIXER 269 | ||
| 104 | #define CLK_TVENC 270 /* Exynos4210 only */ | ||
| 105 | #define CLK_HDMI 271 | ||
| 106 | #define CLK_SMMU_TV 272 | ||
| 107 | #define CLK_MFC 273 | ||
| 108 | #define CLK_SMMU_MFCL 274 | ||
| 109 | #define CLK_SMMU_MFCR 275 | ||
| 110 | #define CLK_G3D 276 | ||
| 111 | #define CLK_G2D 277 | ||
| 112 | #define CLK_ROTATOR 278 /* Exynos4210 only */ | ||
| 113 | #define CLK_MDMA 279 /* Exynos4210 only */ | ||
| 114 | #define CLK_SMMU_G2D 280 /* Exynos4210 only */ | ||
| 115 | #define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */ | ||
| 116 | #define CLK_SMMU_MDMA 282 /* Exynos4210 only */ | ||
| 117 | #define CLK_FIMD0 283 | ||
| 118 | #define CLK_MIE0 284 | ||
| 119 | #define CLK_MDNIE0 285 /* Exynos4412 only */ | ||
| 120 | #define CLK_DSIM0 286 | ||
| 121 | #define CLK_SMMU_FIMD0 287 | ||
| 122 | #define CLK_FIMD1 288 /* Exynos4210 only */ | ||
| 123 | #define CLK_MIE1 289 /* Exynos4210 only */ | ||
| 124 | #define CLK_DSIM1 290 /* Exynos4210 only */ | ||
| 125 | #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ | ||
| 126 | #define CLK_PDMA0 292 | ||
| 127 | #define CLK_PDMA1 293 | ||
| 128 | #define CLK_PCIE_PHY 294 | ||
| 129 | #define CLK_SATA_PHY 295 /* Exynos4210 only */ | ||
| 130 | #define CLK_TSI 296 | ||
| 131 | #define CLK_SDMMC0 297 | ||
| 132 | #define CLK_SDMMC1 298 | ||
| 133 | #define CLK_SDMMC2 299 | ||
| 134 | #define CLK_SDMMC3 300 | ||
| 135 | #define CLK_SDMMC4 301 | ||
| 136 | #define CLK_SATA 302 /* Exynos4210 only */ | ||
| 137 | #define CLK_SROMC 303 | ||
| 138 | #define CLK_USB_HOST 304 | ||
| 139 | #define CLK_USB_DEVICE 305 | ||
| 140 | #define CLK_PCIE 306 | ||
| 141 | #define CLK_ONENAND 307 | ||
| 142 | #define CLK_NFCON 308 | ||
| 143 | #define CLK_SMMU_PCIE 309 | ||
| 144 | #define CLK_GPS 310 | ||
| 145 | #define CLK_SMMU_GPS 311 | ||
| 146 | #define CLK_UART0 312 | ||
| 147 | #define CLK_UART1 313 | ||
| 148 | #define CLK_UART2 314 | ||
| 149 | #define CLK_UART3 315 | ||
| 150 | #define CLK_UART4 316 | ||
| 151 | #define CLK_I2C0 317 | ||
| 152 | #define CLK_I2C1 318 | ||
| 153 | #define CLK_I2C2 319 | ||
| 154 | #define CLK_I2C3 320 | ||
| 155 | #define CLK_I2C4 321 | ||
| 156 | #define CLK_I2C5 322 | ||
| 157 | #define CLK_I2C6 323 | ||
| 158 | #define CLK_I2C7 324 | ||
| 159 | #define CLK_I2C_HDMI 325 | ||
| 160 | #define CLK_TSADC 326 | ||
| 161 | #define CLK_SPI0 327 | ||
| 162 | #define CLK_SPI1 328 | ||
| 163 | #define CLK_SPI2 329 | ||
| 164 | #define CLK_I2S1 330 | ||
| 165 | #define CLK_I2S2 331 | ||
| 166 | #define CLK_PCM0 332 | ||
| 167 | #define CLK_I2S0 333 | ||
| 168 | #define CLK_PCM1 334 | ||
| 169 | #define CLK_PCM2 335 | ||
| 170 | #define CLK_PWM 336 | ||
| 171 | #define CLK_SLIMBUS 337 | ||
| 172 | #define CLK_SPDIF 338 | ||
| 173 | #define CLK_AC97 339 | ||
| 174 | #define CLK_MODEMIF 340 | ||
| 175 | #define CLK_CHIPID 341 | ||
| 176 | #define CLK_SYSREG 342 | ||
| 177 | #define CLK_HDMI_CEC 343 | ||
| 178 | #define CLK_MCT 344 | ||
| 179 | #define CLK_WDT 345 | ||
| 180 | #define CLK_RTC 346 | ||
| 181 | #define CLK_KEYIF 347 | ||
| 182 | #define CLK_AUDSS 348 | ||
| 183 | #define CLK_MIPI_HSI 349 /* Exynos4210 only */ | ||
| 184 | #define CLK_MDMA2 350 /* Exynos4210 only */ | ||
| 185 | #define CLK_PIXELASYNCM0 351 | ||
| 186 | #define CLK_PIXELASYNCM1 352 | ||
| 187 | #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ | ||
| 188 | #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ | ||
| 189 | #define CLK_PPMUISPX 355 /* Exynos4x12 only */ | ||
| 190 | #define CLK_PPMUISPMX 356 /* Exynos4x12 only */ | ||
| 191 | #define CLK_FIMC_ISP 357 /* Exynos4x12 only */ | ||
| 192 | #define CLK_FIMC_DRC 358 /* Exynos4x12 only */ | ||
| 193 | #define CLK_FIMC_FD 359 /* Exynos4x12 only */ | ||
| 194 | #define CLK_MCUISP 360 /* Exynos4x12 only */ | ||
| 195 | #define CLK_GICISP 361 /* Exynos4x12 only */ | ||
| 196 | #define CLK_SMMU_ISP 362 /* Exynos4x12 only */ | ||
| 197 | #define CLK_SMMU_DRC 363 /* Exynos4x12 only */ | ||
| 198 | #define CLK_SMMU_FD 364 /* Exynos4x12 only */ | ||
| 199 | #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ | ||
| 200 | #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ | ||
| 201 | #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ | ||
| 202 | #define CLK_MPWM_ISP 368 /* Exynos4x12 only */ | ||
| 203 | #define CLK_I2C0_ISP 369 /* Exynos4x12 only */ | ||
| 204 | #define CLK_I2C1_ISP 370 /* Exynos4x12 only */ | ||
| 205 | #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ | ||
| 206 | #define CLK_PWM_ISP 372 /* Exynos4x12 only */ | ||
| 207 | #define CLK_WDT_ISP 373 /* Exynos4x12 only */ | ||
| 208 | #define CLK_UART_ISP 374 /* Exynos4x12 only */ | ||
| 209 | #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ | ||
| 210 | #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ | ||
| 211 | #define CLK_SPI0_ISP 377 /* Exynos4x12 only */ | ||
| 212 | #define CLK_SPI1_ISP 378 /* Exynos4x12 only */ | ||
| 213 | #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ | ||
| 214 | #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ | ||
| 215 | #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ | ||
| 216 | #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ | ||
| 217 | #define CLK_TMU_APBIF 383 | ||
| 218 | |||
| 219 | /* mux clocks */ | ||
| 220 | #define CLK_MOUT_FIMC0 384 | ||
| 221 | #define CLK_MOUT_FIMC1 385 | ||
| 222 | #define CLK_MOUT_FIMC2 386 | ||
| 223 | #define CLK_MOUT_FIMC3 387 | ||
| 224 | #define CLK_MOUT_CAM0 388 | ||
| 225 | #define CLK_MOUT_CAM1 389 | ||
| 226 | #define CLK_MOUT_CSIS0 390 | ||
| 227 | #define CLK_MOUT_CSIS1 391 | ||
| 228 | #define CLK_MOUT_G3D0 392 | ||
| 229 | #define CLK_MOUT_G3D1 393 | ||
| 230 | #define CLK_MOUT_G3D 394 | ||
| 231 | #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ | ||
| 232 | |||
| 233 | /* div clocks */ | ||
| 234 | #define CLK_DIV_ISP0 450 /* Exynos4x12 only */ | ||
| 235 | #define CLK_DIV_ISP1 451 /* Exynos4x12 only */ | ||
| 236 | #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ | ||
| 237 | #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ | ||
| 238 | #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ | ||
| 239 | #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ | ||
| 240 | |||
| 241 | /* must be greater than maximal clock id */ | ||
| 242 | #define CLK_NR_CLKS 456 | ||
| 243 | |||
| 244 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ | ||
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h new file mode 100644 index 000000000000..922f2dca9bf0 --- /dev/null +++ b/include/dt-bindings/clock/exynos5250.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 3 | * Author: Andrzej Haja <a.hajda@samsung.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * Device Tree binding constants for Exynos5250 clock controller. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H | ||
| 13 | #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H | ||
| 14 | |||
| 15 | /* core clocks */ | ||
| 16 | #define CLK_FIN_PLL 1 | ||
| 17 | #define CLK_FOUT_APLL 2 | ||
| 18 | #define CLK_FOUT_MPLL 3 | ||
| 19 | #define CLK_FOUT_BPLL 4 | ||
| 20 | #define CLK_FOUT_GPLL 5 | ||
| 21 | #define CLK_FOUT_CPLL 6 | ||
| 22 | #define CLK_FOUT_EPLL 7 | ||
| 23 | #define CLK_FOUT_VPLL 8 | ||
| 24 | |||
| 25 | /* gate for special clocks (sclk) */ | ||
| 26 | #define CLK_SCLK_CAM_BAYER 128 | ||
| 27 | #define CLK_SCLK_CAM0 129 | ||
| 28 | #define CLK_SCLK_CAM1 130 | ||
| 29 | #define CLK_SCLK_GSCL_WA 131 | ||
| 30 | #define CLK_SCLK_GSCL_WB 132 | ||
| 31 | #define CLK_SCLK_FIMD1 133 | ||
| 32 | #define CLK_SCLK_MIPI1 134 | ||
| 33 | #define CLK_SCLK_DP 135 | ||
| 34 | #define CLK_SCLK_HDMI 136 | ||
| 35 | #define CLK_SCLK_PIXEL 137 | ||
| 36 | #define CLK_SCLK_AUDIO0 138 | ||
| 37 | #define CLK_SCLK_MMC0 139 | ||
| 38 | #define CLK_SCLK_MMC1 140 | ||
| 39 | #define CLK_SCLK_MMC2 141 | ||
| 40 | #define CLK_SCLK_MMC3 142 | ||
| 41 | #define CLK_SCLK_SATA 143 | ||
| 42 | #define CLK_SCLK_USB3 144 | ||
| 43 | #define CLK_SCLK_JPEG 145 | ||
| 44 | #define CLK_SCLK_UART0 146 | ||
| 45 | #define CLK_SCLK_UART1 147 | ||
| 46 | #define CLK_SCLK_UART2 148 | ||
| 47 | #define CLK_SCLK_UART3 149 | ||
| 48 | #define CLK_SCLK_PWM 150 | ||
| 49 | #define CLK_SCLK_AUDIO1 151 | ||
| 50 | #define CLK_SCLK_AUDIO2 152 | ||
| 51 | #define CLK_SCLK_SPDIF 153 | ||
| 52 | #define CLK_SCLK_SPI0 154 | ||
| 53 | #define CLK_SCLK_SPI1 155 | ||
| 54 | #define CLK_SCLK_SPI2 156 | ||
| 55 | #define CLK_DIV_I2S1 157 | ||
| 56 | #define CLK_DIV_I2S2 158 | ||
| 57 | #define CLK_SCLK_HDMIPHY 159 | ||
| 58 | #define CLK_DIV_PCM0 160 | ||
| 59 | |||
| 60 | /* gate clocks */ | ||
| 61 | #define CLK_GSCL0 256 | ||
| 62 | #define CLK_GSCL1 257 | ||
| 63 | #define CLK_GSCL2 258 | ||
| 64 | #define CLK_GSCL3 259 | ||
| 65 | #define CLK_GSCL_WA 260 | ||
| 66 | #define CLK_GSCL_WB 261 | ||
| 67 | #define CLK_SMMU_GSCL0 262 | ||
| 68 | #define CLK_SMMU_GSCL1 263 | ||
| 69 | #define CLK_SMMU_GSCL2 264 | ||
| 70 | #define CLK_SMMU_GSCL3 265 | ||
| 71 | #define CLK_MFC 266 | ||
| 72 | #define CLK_SMMU_MFCL 267 | ||
| 73 | #define CLK_SMMU_MFCR 268 | ||
| 74 | #define CLK_ROTATOR 269 | ||
| 75 | #define CLK_JPEG 270 | ||
| 76 | #define CLK_MDMA1 271 | ||
| 77 | #define CLK_SMMU_ROTATOR 272 | ||
| 78 | #define CLK_SMMU_JPEG 273 | ||
| 79 | #define CLK_SMMU_MDMA1 274 | ||
| 80 | #define CLK_PDMA0 275 | ||
| 81 | #define CLK_PDMA1 276 | ||
| 82 | #define CLK_SATA 277 | ||
| 83 | #define CLK_USBOTG 278 | ||
| 84 | #define CLK_MIPI_HSI 279 | ||
| 85 | #define CLK_SDMMC0 280 | ||
| 86 | #define CLK_SDMMC1 281 | ||
| 87 | #define CLK_SDMMC2 282 | ||
| 88 | #define CLK_SDMMC3 283 | ||
| 89 | #define CLK_SROMC 284 | ||
| 90 | #define CLK_USB2 285 | ||
| 91 | #define CLK_USB3 286 | ||
| 92 | #define CLK_SATA_PHYCTRL 287 | ||
| 93 | #define CLK_SATA_PHYI2C 288 | ||
| 94 | #define CLK_UART0 289 | ||
| 95 | #define CLK_UART1 290 | ||
| 96 | #define CLK_UART2 291 | ||
| 97 | #define CLK_UART3 292 | ||
| 98 | #define CLK_UART4 293 | ||
| 99 | #define CLK_I2C0 294 | ||
| 100 | #define CLK_I2C1 295 | ||
| 101 | #define CLK_I2C2 296 | ||
| 102 | #define CLK_I2C3 297 | ||
| 103 | #define CLK_I2C4 298 | ||
| 104 | #define CLK_I2C5 299 | ||
| 105 | #define CLK_I2C6 300 | ||
| 106 | #define CLK_I2C7 301 | ||
| 107 | #define CLK_I2C_HDMI 302 | ||
| 108 | #define CLK_ADC 303 | ||
| 109 | #define CLK_SPI0 304 | ||
| 110 | #define CLK_SPI1 305 | ||
| 111 | #define CLK_SPI2 306 | ||
| 112 | #define CLK_I2S1 307 | ||
| 113 | #define CLK_I2S2 308 | ||
| 114 | #define CLK_PCM1 309 | ||
| 115 | #define CLK_PCM2 310 | ||
| 116 | #define CLK_PWM 311 | ||
| 117 | #define CLK_SPDIF 312 | ||
| 118 | #define CLK_AC97 313 | ||
| 119 | #define CLK_HSI2C0 314 | ||
| 120 | #define CLK_HSI2C1 315 | ||
| 121 | #define CLK_HSI2C2 316 | ||
| 122 | #define CLK_HSI2C3 317 | ||
| 123 | #define CLK_CHIPID 318 | ||
| 124 | #define CLK_SYSREG 319 | ||
| 125 | #define CLK_PMU 320 | ||
| 126 | #define CLK_CMU_TOP 321 | ||
| 127 | #define CLK_CMU_CORE 322 | ||
| 128 | #define CLK_CMU_MEM 323 | ||
| 129 | #define CLK_TZPC0 324 | ||
| 130 | #define CLK_TZPC1 325 | ||
| 131 | #define CLK_TZPC2 326 | ||
| 132 | #define CLK_TZPC3 327 | ||
| 133 | #define CLK_TZPC4 328 | ||
| 134 | #define CLK_TZPC5 329 | ||
| 135 | #define CLK_TZPC6 330 | ||
| 136 | #define CLK_TZPC7 331 | ||
| 137 | #define CLK_TZPC8 332 | ||
| 138 | #define CLK_TZPC9 333 | ||
| 139 | #define CLK_HDMI_CEC 334 | ||
| 140 | #define CLK_MCT 335 | ||
| 141 | #define CLK_WDT 336 | ||
| 142 | #define CLK_RTC 337 | ||
| 143 | #define CLK_TMU 338 | ||
| 144 | #define CLK_FIMD1 339 | ||
| 145 | #define CLK_MIE1 340 | ||
| 146 | #define CLK_DSIM0 341 | ||
| 147 | #define CLK_DP 342 | ||
| 148 | #define CLK_MIXER 343 | ||
| 149 | #define CLK_HDMI 344 | ||
| 150 | #define CLK_G2D 345 | ||
| 151 | #define CLK_MDMA0 346 | ||
| 152 | #define CLK_SMMU_MDMA0 347 | ||
| 153 | |||
| 154 | /* mux clocks */ | ||
| 155 | #define CLK_MOUT_HDMI 1024 | ||
| 156 | |||
| 157 | /* must be greater than maximal clock id */ | ||
| 158 | #define CLK_NR_CLKS 1025 | ||
| 159 | |||
| 160 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ | ||
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h new file mode 100644 index 000000000000..5eefd8813f02 --- /dev/null +++ b/include/dt-bindings/clock/exynos5420.h | |||
| @@ -0,0 +1,188 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 3 | * Author: Andrzej Haja <a.hajda@samsung.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * Device Tree binding constants for Exynos5420 clock controller. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H | ||
| 13 | #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H | ||
| 14 | |||
| 15 | /* core clocks */ | ||
| 16 | #define CLK_FIN_PLL 1 | ||
| 17 | #define CLK_FOUT_APLL 2 | ||
| 18 | #define CLK_FOUT_CPLL 3 | ||
| 19 | #define CLK_FOUT_DPLL 4 | ||
| 20 | #define CLK_FOUT_EPLL 5 | ||
| 21 | #define CLK_FOUT_RPLL 6 | ||
| 22 | #define CLK_FOUT_IPLL 7 | ||
| 23 | #define CLK_FOUT_SPLL 8 | ||
| 24 | #define CLK_FOUT_VPLL 9 | ||
| 25 | #define CLK_FOUT_MPLL 10 | ||
| 26 | #define CLK_FOUT_BPLL 11 | ||
| 27 | #define CLK_FOUT_KPLL 12 | ||
| 28 | |||
| 29 | /* gate for special clocks (sclk) */ | ||
| 30 | #define CLK_SCLK_UART0 128 | ||
| 31 | #define CLK_SCLK_UART1 129 | ||
| 32 | #define CLK_SCLK_UART2 130 | ||
| 33 | #define CLK_SCLK_UART3 131 | ||
| 34 | #define CLK_SCLK_MMC0 132 | ||
| 35 | #define CLK_SCLK_MMC1 133 | ||
| 36 | #define CLK_SCLK_MMC2 134 | ||
| 37 | #define CLK_SCLK_SPI0 135 | ||
| 38 | #define CLK_SCLK_SPI1 136 | ||
| 39 | #define CLK_SCLK_SPI2 137 | ||
| 40 | #define CLK_SCLK_I2S1 138 | ||
| 41 | #define CLK_SCLK_I2S2 139 | ||
| 42 | #define CLK_SCLK_PCM1 140 | ||
| 43 | #define CLK_SCLK_PCM2 141 | ||
| 44 | #define CLK_SCLK_SPDIF 142 | ||
| 45 | #define CLK_SCLK_HDMI 143 | ||
| 46 | #define CLK_SCLK_PIXEL 144 | ||
| 47 | #define CLK_SCLK_DP1 145 | ||
| 48 | #define CLK_SCLK_MIPI1 146 | ||
| 49 | #define CLK_SCLK_FIMD1 147 | ||
| 50 | #define CLK_SCLK_MAUDIO0 148 | ||
| 51 | #define CLK_SCLK_MAUPCM0 149 | ||
| 52 | #define CLK_SCLK_USBD300 150 | ||
| 53 | #define CLK_SCLK_USBD301 151 | ||
| 54 | #define CLK_SCLK_USBPHY300 152 | ||
| 55 | #define CLK_SCLK_USBPHY301 153 | ||
| 56 | #define CLK_SCLK_UNIPRO 154 | ||
| 57 | #define CLK_SCLK_PWM 155 | ||
| 58 | #define CLK_SCLK_GSCL_WA 156 | ||
| 59 | #define CLK_SCLK_GSCL_WB 157 | ||
| 60 | #define CLK_SCLK_HDMIPHY 158 | ||
| 61 | |||
| 62 | /* gate clocks */ | ||
| 63 | #define CLK_ACLK66_PERIC 256 | ||
| 64 | #define CLK_UART0 257 | ||
| 65 | #define CLK_UART1 258 | ||
| 66 | #define CLK_UART2 259 | ||
| 67 | #define CLK_UART3 260 | ||
| 68 | #define CLK_I2C0 261 | ||
| 69 | #define CLK_I2C1 262 | ||
| 70 | #define CLK_I2C2 263 | ||
| 71 | #define CLK_I2C3 264 | ||
| 72 | #define CLK_I2C4 265 | ||
| 73 | #define CLK_I2C5 266 | ||
| 74 | #define CLK_I2C6 267 | ||
| 75 | #define CLK_I2C7 268 | ||
| 76 | #define CLK_I2C_HDMI 269 | ||
| 77 | #define CLK_TSADC 270 | ||
| 78 | #define CLK_SPI0 271 | ||
| 79 | #define CLK_SPI1 272 | ||
| 80 | #define CLK_SPI2 273 | ||
| 81 | #define CLK_KEYIF 274 | ||
| 82 | #define CLK_I2S1 275 | ||
| 83 | #define CLK_I2S2 276 | ||
| 84 | #define CLK_PCM1 277 | ||
| 85 | #define CLK_PCM2 278 | ||
| 86 | #define CLK_PWM 279 | ||
| 87 | #define CLK_SPDIF 280 | ||
| 88 | #define CLK_I2C8 281 | ||
| 89 | #define CLK_I2C9 282 | ||
| 90 | #define CLK_I2C10 283 | ||
| 91 | #define CLK_ACLK66_PSGEN 300 | ||
| 92 | #define CLK_CHIPID 301 | ||
| 93 | #define CLK_SYSREG 302 | ||
| 94 | #define CLK_TZPC0 303 | ||
| 95 | #define CLK_TZPC1 304 | ||
| 96 | #define CLK_TZPC2 305 | ||
| 97 | #define CLK_TZPC3 306 | ||
| 98 | #define CLK_TZPC4 307 | ||
| 99 | #define CLK_TZPC5 308 | ||
| 100 | #define CLK_TZPC6 309 | ||
| 101 | #define CLK_TZPC7 310 | ||
| 102 | #define CLK_TZPC8 311 | ||
| 103 | #define CLK_TZPC9 312 | ||
| 104 | #define CLK_HDMI_CEC 313 | ||
| 105 | #define CLK_SECKEY 314 | ||
| 106 | #define CLK_MCT 315 | ||
| 107 | #define CLK_WDT 316 | ||
| 108 | #define CLK_RTC 317 | ||
| 109 | #define CLK_TMU 318 | ||
| 110 | #define CLK_TMU_GPU 319 | ||
| 111 | #define CLK_PCLK66_GPIO 330 | ||
| 112 | #define CLK_ACLK200_FSYS2 350 | ||
| 113 | #define CLK_MMC0 351 | ||
| 114 | #define CLK_MMC1 352 | ||
| 115 | #define CLK_MMC2 353 | ||
| 116 | #define CLK_SROMC 354 | ||
| 117 | #define CLK_UFS 355 | ||
| 118 | #define CLK_ACLK200_FSYS 360 | ||
| 119 | #define CLK_TSI 361 | ||
| 120 | #define CLK_PDMA0 362 | ||
| 121 | #define CLK_PDMA1 363 | ||
| 122 | #define CLK_RTIC 364 | ||
| 123 | #define CLK_USBH20 365 | ||
| 124 | #define CLK_USBD300 366 | ||
| 125 | #define CLK_USBD301 367 | ||
| 126 | #define CLK_ACLK400_MSCL 380 | ||
| 127 | #define CLK_MSCL0 381 | ||
| 128 | #define CLK_MSCL1 382 | ||
| 129 | #define CLK_MSCL2 383 | ||
| 130 | #define CLK_SMMU_MSCL0 384 | ||
| 131 | #define CLK_SMMU_MSCL1 385 | ||
| 132 | #define CLK_SMMU_MSCL2 386 | ||
| 133 | #define CLK_ACLK333 400 | ||
| 134 | #define CLK_MFC 401 | ||
| 135 | #define CLK_SMMU_MFCL 402 | ||
| 136 | #define CLK_SMMU_MFCR 403 | ||
| 137 | #define CLK_ACLK200_DISP1 410 | ||
| 138 | #define CLK_DSIM1 411 | ||
| 139 | #define CLK_DP1 412 | ||
| 140 | #define CLK_HDMI 413 | ||
| 141 | #define CLK_ACLK300_DISP1 420 | ||
| 142 | #define CLK_FIMD1 421 | ||
| 143 | #define CLK_SMMU_FIMD1 422 | ||
| 144 | #define CLK_ACLK166 430 | ||
| 145 | #define CLK_MIXER 431 | ||
| 146 | #define CLK_ACLK266 440 | ||
| 147 | #define CLK_ROTATOR 441 | ||
| 148 | #define CLK_MDMA1 442 | ||
| 149 | #define CLK_SMMU_ROTATOR 443 | ||
| 150 | #define CLK_SMMU_MDMA1 444 | ||
| 151 | #define CLK_ACLK300_JPEG 450 | ||
| 152 | #define CLK_JPEG 451 | ||
| 153 | #define CLK_JPEG2 452 | ||
| 154 | #define CLK_SMMU_JPEG 453 | ||
| 155 | #define CLK_ACLK300_GSCL 460 | ||
| 156 | #define CLK_SMMU_GSCL0 461 | ||
| 157 | #define CLK_SMMU_GSCL1 462 | ||
| 158 | #define CLK_GSCL_WA 463 | ||
| 159 | #define CLK_GSCL_WB 464 | ||
| 160 | #define CLK_GSCL0 465 | ||
| 161 | #define CLK_GSCL1 466 | ||
| 162 | #define CLK_CLK_3AA 467 | ||
| 163 | #define CLK_ACLK266_G2D 470 | ||
| 164 | #define CLK_SSS 471 | ||
| 165 | #define CLK_SLIM_SSS 472 | ||
| 166 | #define CLK_MDMA0 473 | ||
| 167 | #define CLK_ACLK333_G2D 480 | ||
| 168 | #define CLK_G2D 481 | ||
| 169 | #define CLK_ACLK333_432_GSCL 490 | ||
| 170 | #define CLK_SMMU_3AA 491 | ||
| 171 | #define CLK_SMMU_FIMCL0 492 | ||
| 172 | #define CLK_SMMU_FIMCL1 493 | ||
| 173 | #define CLK_SMMU_FIMCL3 494 | ||
| 174 | #define CLK_FIMC_LITE3 495 | ||
| 175 | #define CLK_ACLK_G3D 500 | ||
| 176 | #define CLK_G3D 501 | ||
| 177 | #define CLK_SMMU_MIXER 502 | ||
| 178 | |||
| 179 | /* mux clocks */ | ||
| 180 | #define CLK_MOUT_HDMI 640 | ||
| 181 | |||
| 182 | /* divider clocks */ | ||
| 183 | #define CLK_DOUT_PIXEL 768 | ||
| 184 | |||
| 185 | /* must be greater than maximal clock id */ | ||
| 186 | #define CLK_NR_CLKS 769 | ||
| 187 | |||
| 188 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ | ||
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h new file mode 100644 index 000000000000..70cd85077fa9 --- /dev/null +++ b/include/dt-bindings/clock/exynos5440.h | |||
| @@ -0,0 +1,42 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013 Samsung Electronics Co., Ltd. | ||
| 3 | * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License version 2 as | ||
| 7 | * published by the Free Software Foundation. | ||
| 8 | * | ||
| 9 | * Device Tree binding constants for Exynos5440 clock controller. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H | ||
| 13 | #define _DT_BINDINGS_CLOCK_EXYNOS_5440_H | ||
| 14 | |||
| 15 | #define CLK_XTAL 1 | ||
| 16 | #define CLK_ARM_CLK 2 | ||
| 17 | #define CLK_SPI_BAUD 16 | ||
| 18 | #define CLK_PB0_250 17 | ||
| 19 | #define CLK_PR0_250 18 | ||
| 20 | #define CLK_PR1_250 19 | ||
| 21 | #define CLK_B_250 20 | ||
| 22 | #define CLK_B_125 21 | ||
| 23 | #define CLK_B_200 22 | ||
| 24 | #define CLK_SATA 23 | ||
| 25 | #define CLK_USB 24 | ||
| 26 | #define CLK_GMAC0 25 | ||
| 27 | #define CLK_CS250 26 | ||
| 28 | #define CLK_PB0_250_O 27 | ||
| 29 | #define CLK_PR0_250_O 28 | ||
| 30 | #define CLK_PR1_250_O 29 | ||
| 31 | #define CLK_B_250_O 30 | ||
| 32 | #define CLK_B_125_O 31 | ||
| 33 | #define CLK_B_200_O 32 | ||
| 34 | #define CLK_SATA_O 33 | ||
| 35 | #define CLK_USB_O 34 | ||
| 36 | #define CLK_GMAC0_O 35 | ||
| 37 | #define CLK_CS250_O 36 | ||
| 38 | |||
| 39 | /* must be greater than maximal clock id */ | ||
| 40 | #define CLK_NR_CLKS 37 | ||
| 41 | |||
| 42 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ | ||
diff --git a/include/dt-bindings/clock/hi3620-clock.h b/include/dt-bindings/clock/hi3620-clock.h new file mode 100644 index 000000000000..6eaa6a45e110 --- /dev/null +++ b/include/dt-bindings/clock/hi3620-clock.h | |||
| @@ -0,0 +1,152 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2012-2013 Hisilicon Limited. | ||
| 3 | * Copyright (c) 2012-2013 Linaro Limited. | ||
| 4 | * | ||
| 5 | * Author: Haojian Zhuang <haojian.zhuang@linaro.org> | ||
| 6 | * Xin Li <li.xin@linaro.org> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License along | ||
| 19 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 20 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | ||
| 21 | * | ||
| 22 | */ | ||
| 23 | |||
| 24 | #ifndef __DTS_HI3620_CLOCK_H | ||
| 25 | #define __DTS_HI3620_CLOCK_H | ||
| 26 | |||
| 27 | #define HI3620_NONE_CLOCK 0 | ||
| 28 | |||
| 29 | /* fixed rate & fixed factor clocks */ | ||
| 30 | #define HI3620_OSC32K 1 | ||
| 31 | #define HI3620_OSC26M 2 | ||
| 32 | #define HI3620_PCLK 3 | ||
| 33 | #define HI3620_PLL_ARM0 4 | ||
| 34 | #define HI3620_PLL_ARM1 5 | ||
| 35 | #define HI3620_PLL_PERI 6 | ||
| 36 | #define HI3620_PLL_USB 7 | ||
| 37 | #define HI3620_PLL_HDMI 8 | ||
| 38 | #define HI3620_PLL_GPU 9 | ||
| 39 | #define HI3620_RCLK_TCXO 10 | ||
| 40 | #define HI3620_RCLK_CFGAXI 11 | ||
| 41 | #define HI3620_RCLK_PICO 12 | ||
| 42 | |||
| 43 | /* mux clocks */ | ||
| 44 | #define HI3620_TIMER0_MUX 32 | ||
| 45 | #define HI3620_TIMER1_MUX 33 | ||
| 46 | #define HI3620_TIMER2_MUX 34 | ||
| 47 | #define HI3620_TIMER3_MUX 35 | ||
| 48 | #define HI3620_TIMER4_MUX 36 | ||
| 49 | #define HI3620_TIMER5_MUX 37 | ||
| 50 | #define HI3620_TIMER6_MUX 38 | ||
| 51 | #define HI3620_TIMER7_MUX 39 | ||
| 52 | #define HI3620_TIMER8_MUX 40 | ||
| 53 | #define HI3620_TIMER9_MUX 41 | ||
| 54 | #define HI3620_UART0_MUX 42 | ||
| 55 | #define HI3620_UART1_MUX 43 | ||
| 56 | #define HI3620_UART2_MUX 44 | ||
| 57 | #define HI3620_UART3_MUX 45 | ||
| 58 | #define HI3620_UART4_MUX 46 | ||
| 59 | #define HI3620_SPI0_MUX 47 | ||
| 60 | #define HI3620_SPI1_MUX 48 | ||
| 61 | #define HI3620_SPI2_MUX 49 | ||
| 62 | #define HI3620_SAXI_MUX 50 | ||
| 63 | #define HI3620_PWM0_MUX 51 | ||
| 64 | #define HI3620_PWM1_MUX 52 | ||
| 65 | #define HI3620_SD_MUX 53 | ||
| 66 | #define HI3620_MMC1_MUX 54 | ||
| 67 | #define HI3620_MMC1_MUX2 55 | ||
| 68 | #define HI3620_G2D_MUX 56 | ||
| 69 | #define HI3620_VENC_MUX 57 | ||
| 70 | #define HI3620_VDEC_MUX 58 | ||
| 71 | #define HI3620_VPP_MUX 59 | ||
| 72 | #define HI3620_EDC0_MUX 60 | ||
| 73 | #define HI3620_LDI0_MUX 61 | ||
| 74 | #define HI3620_EDC1_MUX 62 | ||
| 75 | #define HI3620_LDI1_MUX 63 | ||
| 76 | #define HI3620_RCLK_HSIC 64 | ||
| 77 | #define HI3620_MMC2_MUX 65 | ||
| 78 | #define HI3620_MMC3_MUX 66 | ||
| 79 | |||
| 80 | /* divider clocks */ | ||
| 81 | #define HI3620_SHAREAXI_DIV 128 | ||
| 82 | #define HI3620_CFGAXI_DIV 129 | ||
| 83 | #define HI3620_SD_DIV 130 | ||
| 84 | #define HI3620_MMC1_DIV 131 | ||
| 85 | #define HI3620_HSIC_DIV 132 | ||
| 86 | #define HI3620_MMC2_DIV 133 | ||
| 87 | #define HI3620_MMC3_DIV 134 | ||
| 88 | |||
| 89 | /* gate clocks */ | ||
| 90 | #define HI3620_TIMERCLK01 160 | ||
| 91 | #define HI3620_TIMER_RCLK01 161 | ||
| 92 | #define HI3620_TIMERCLK23 162 | ||
| 93 | #define HI3620_TIMER_RCLK23 163 | ||
| 94 | #define HI3620_TIMERCLK45 164 | ||
| 95 | #define HI3620_TIMERCLK67 165 | ||
| 96 | #define HI3620_TIMERCLK89 166 | ||
| 97 | #define HI3620_RTCCLK 167 | ||
| 98 | #define HI3620_KPC_CLK 168 | ||
| 99 | #define HI3620_GPIOCLK0 169 | ||
| 100 | #define HI3620_GPIOCLK1 170 | ||
| 101 | #define HI3620_GPIOCLK2 171 | ||
| 102 | #define HI3620_GPIOCLK3 172 | ||
| 103 | #define HI3620_GPIOCLK4 173 | ||
| 104 | #define HI3620_GPIOCLK5 174 | ||
| 105 | #define HI3620_GPIOCLK6 175 | ||
| 106 | #define HI3620_GPIOCLK7 176 | ||
| 107 | #define HI3620_GPIOCLK8 177 | ||
| 108 | #define HI3620_GPIOCLK9 178 | ||
| 109 | #define HI3620_GPIOCLK10 179 | ||
| 110 | #define HI3620_GPIOCLK11 180 | ||
| 111 | #define HI3620_GPIOCLK12 181 | ||
| 112 | #define HI3620_GPIOCLK13 182 | ||
| 113 | #define HI3620_GPIOCLK14 183 | ||
| 114 | #define HI3620_GPIOCLK15 184 | ||
| 115 | #define HI3620_GPIOCLK16 185 | ||
| 116 | #define HI3620_GPIOCLK17 186 | ||
| 117 | #define HI3620_GPIOCLK18 187 | ||
| 118 | #define HI3620_GPIOCLK19 188 | ||
| 119 | #define HI3620_GPIOCLK20 189 | ||
| 120 | #define HI3620_GPIOCLK21 190 | ||
| 121 | #define HI3620_DPHY0_CLK 191 | ||
| 122 | #define HI3620_DPHY1_CLK 192 | ||
| 123 | #define HI3620_DPHY2_CLK 193 | ||
| 124 | #define HI3620_USBPHY_CLK 194 | ||
| 125 | #define HI3620_ACP_CLK 195 | ||
| 126 | #define HI3620_PWMCLK0 196 | ||
| 127 | #define HI3620_PWMCLK1 197 | ||
| 128 | #define HI3620_UARTCLK0 198 | ||
| 129 | #define HI3620_UARTCLK1 199 | ||
| 130 | #define HI3620_UARTCLK2 200 | ||
| 131 | #define HI3620_UARTCLK3 201 | ||
| 132 | #define HI3620_UARTCLK4 202 | ||
| 133 | #define HI3620_SPICLK0 203 | ||
| 134 | #define HI3620_SPICLK1 204 | ||
| 135 | #define HI3620_SPICLK2 205 | ||
| 136 | #define HI3620_I2CCLK0 206 | ||
| 137 | #define HI3620_I2CCLK1 207 | ||
| 138 | #define HI3620_I2CCLK2 208 | ||
| 139 | #define HI3620_I2CCLK3 209 | ||
| 140 | #define HI3620_SCI_CLK 210 | ||
| 141 | #define HI3620_DDRC_PER_CLK 211 | ||
| 142 | #define HI3620_DMAC_CLK 212 | ||
| 143 | #define HI3620_USB2DVC_CLK 213 | ||
| 144 | #define HI3620_SD_CLK 214 | ||
| 145 | #define HI3620_MMC_CLK1 215 | ||
| 146 | #define HI3620_MMC_CLK2 216 | ||
| 147 | #define HI3620_MMC_CLK3 217 | ||
| 148 | #define HI3620_MCU_CLK 218 | ||
| 149 | |||
| 150 | #define HI3620_NR_CLKS 219 | ||
| 151 | |||
| 152 | #endif /* __DTS_HI3620_CLOCK_H */ | ||
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h new file mode 100644 index 000000000000..5f2667ecd98e --- /dev/null +++ b/include/dt-bindings/clock/imx5-clock.h | |||
| @@ -0,0 +1,203 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_IMX5_H | ||
| 11 | #define __DT_BINDINGS_CLOCK_IMX5_H | ||
| 12 | |||
| 13 | #define IMX5_CLK_DUMMY 0 | ||
| 14 | #define IMX5_CLK_CKIL 1 | ||
| 15 | #define IMX5_CLK_OSC 2 | ||
| 16 | #define IMX5_CLK_CKIH1 3 | ||
| 17 | #define IMX5_CLK_CKIH2 4 | ||
| 18 | #define IMX5_CLK_AHB 5 | ||
| 19 | #define IMX5_CLK_IPG 6 | ||
| 20 | #define IMX5_CLK_AXI_A 7 | ||
| 21 | #define IMX5_CLK_AXI_B 8 | ||
| 22 | #define IMX5_CLK_UART_PRED 9 | ||
| 23 | #define IMX5_CLK_UART_ROOT 10 | ||
| 24 | #define IMX5_CLK_ESDHC_A_PRED 11 | ||
| 25 | #define IMX5_CLK_ESDHC_B_PRED 12 | ||
| 26 | #define IMX5_CLK_ESDHC_C_SEL 13 | ||
| 27 | #define IMX5_CLK_ESDHC_D_SEL 14 | ||
| 28 | #define IMX5_CLK_EMI_SEL 15 | ||
| 29 | #define IMX5_CLK_EMI_SLOW_PODF 16 | ||
| 30 | #define IMX5_CLK_NFC_PODF 17 | ||
| 31 | #define IMX5_CLK_ECSPI_PRED 18 | ||
| 32 | #define IMX5_CLK_ECSPI_PODF 19 | ||
| 33 | #define IMX5_CLK_USBOH3_PRED 20 | ||
| 34 | #define IMX5_CLK_USBOH3_PODF 21 | ||
| 35 | #define IMX5_CLK_USB_PHY_PRED 22 | ||
| 36 | #define IMX5_CLK_USB_PHY_PODF 23 | ||
| 37 | #define IMX5_CLK_CPU_PODF 24 | ||
| 38 | #define IMX5_CLK_DI_PRED 25 | ||
| 39 | #define IMX5_CLK_TVE_SEL 27 | ||
| 40 | #define IMX5_CLK_UART1_IPG_GATE 28 | ||
| 41 | #define IMX5_CLK_UART1_PER_GATE 29 | ||
| 42 | #define IMX5_CLK_UART2_IPG_GATE 30 | ||
| 43 | #define IMX5_CLK_UART2_PER_GATE 31 | ||
| 44 | #define IMX5_CLK_UART3_IPG_GATE 32 | ||
| 45 | #define IMX5_CLK_UART3_PER_GATE 33 | ||
| 46 | #define IMX5_CLK_I2C1_GATE 34 | ||
| 47 | #define IMX5_CLK_I2C2_GATE 35 | ||
| 48 | #define IMX5_CLK_GPT_IPG_GATE 36 | ||
| 49 | #define IMX5_CLK_PWM1_IPG_GATE 37 | ||
| 50 | #define IMX5_CLK_PWM1_HF_GATE 38 | ||
| 51 | #define IMX5_CLK_PWM2_IPG_GATE 39 | ||
| 52 | #define IMX5_CLK_PWM2_HF_GATE 40 | ||
| 53 | #define IMX5_CLK_GPT_HF_GATE 41 | ||
| 54 | #define IMX5_CLK_FEC_GATE 42 | ||
| 55 | #define IMX5_CLK_USBOH3_PER_GATE 43 | ||
| 56 | #define IMX5_CLK_ESDHC1_IPG_GATE 44 | ||
| 57 | #define IMX5_CLK_ESDHC2_IPG_GATE 45 | ||
| 58 | #define IMX5_CLK_ESDHC3_IPG_GATE 46 | ||
| 59 | #define IMX5_CLK_ESDHC4_IPG_GATE 47 | ||
| 60 | #define IMX5_CLK_SSI1_IPG_GATE 48 | ||
| 61 | #define IMX5_CLK_SSI2_IPG_GATE 49 | ||
| 62 | #define IMX5_CLK_SSI3_IPG_GATE 50 | ||
| 63 | #define IMX5_CLK_ECSPI1_IPG_GATE 51 | ||
| 64 | #define IMX5_CLK_ECSPI1_PER_GATE 52 | ||
| 65 | #define IMX5_CLK_ECSPI2_IPG_GATE 53 | ||
| 66 | #define IMX5_CLK_ECSPI2_PER_GATE 54 | ||
| 67 | #define IMX5_CLK_CSPI_IPG_GATE 55 | ||
| 68 | #define IMX5_CLK_SDMA_GATE 56 | ||
| 69 | #define IMX5_CLK_EMI_SLOW_GATE 57 | ||
| 70 | #define IMX5_CLK_IPU_SEL 58 | ||
| 71 | #define IMX5_CLK_IPU_GATE 59 | ||
| 72 | #define IMX5_CLK_NFC_GATE 60 | ||
| 73 | #define IMX5_CLK_IPU_DI1_GATE 61 | ||
| 74 | #define IMX5_CLK_VPU_SEL 62 | ||
| 75 | #define IMX5_CLK_VPU_GATE 63 | ||
| 76 | #define IMX5_CLK_VPU_REFERENCE_GATE 64 | ||
| 77 | #define IMX5_CLK_UART4_IPG_GATE 65 | ||
| 78 | #define IMX5_CLK_UART4_PER_GATE 66 | ||
| 79 | #define IMX5_CLK_UART5_IPG_GATE 67 | ||
| 80 | #define IMX5_CLK_UART5_PER_GATE 68 | ||
| 81 | #define IMX5_CLK_TVE_GATE 69 | ||
| 82 | #define IMX5_CLK_TVE_PRED 70 | ||
| 83 | #define IMX5_CLK_ESDHC1_PER_GATE 71 | ||
| 84 | #define IMX5_CLK_ESDHC2_PER_GATE 72 | ||
| 85 | #define IMX5_CLK_ESDHC3_PER_GATE 73 | ||
| 86 | #define IMX5_CLK_ESDHC4_PER_GATE 74 | ||
| 87 | #define IMX5_CLK_USB_PHY_GATE 75 | ||
| 88 | #define IMX5_CLK_HSI2C_GATE 76 | ||
| 89 | #define IMX5_CLK_MIPI_HSC1_GATE 77 | ||
| 90 | #define IMX5_CLK_MIPI_HSC2_GATE 78 | ||
| 91 | #define IMX5_CLK_MIPI_ESC_GATE 79 | ||
| 92 | #define IMX5_CLK_MIPI_HSP_GATE 80 | ||
| 93 | #define IMX5_CLK_LDB_DI1_DIV_3_5 81 | ||
| 94 | #define IMX5_CLK_LDB_DI1_DIV 82 | ||
| 95 | #define IMX5_CLK_LDB_DI0_DIV_3_5 83 | ||
| 96 | #define IMX5_CLK_LDB_DI0_DIV 84 | ||
| 97 | #define IMX5_CLK_LDB_DI1_GATE 85 | ||
| 98 | #define IMX5_CLK_CAN2_SERIAL_GATE 86 | ||
| 99 | #define IMX5_CLK_CAN2_IPG_GATE 87 | ||
| 100 | #define IMX5_CLK_I2C3_GATE 88 | ||
| 101 | #define IMX5_CLK_LP_APM 89 | ||
| 102 | #define IMX5_CLK_PERIPH_APM 90 | ||
| 103 | #define IMX5_CLK_MAIN_BUS 91 | ||
| 104 | #define IMX5_CLK_AHB_MAX 92 | ||
| 105 | #define IMX5_CLK_AIPS_TZ1 93 | ||
| 106 | #define IMX5_CLK_AIPS_TZ2 94 | ||
| 107 | #define IMX5_CLK_TMAX1 95 | ||
| 108 | #define IMX5_CLK_TMAX2 96 | ||
| 109 | #define IMX5_CLK_TMAX3 97 | ||
| 110 | #define IMX5_CLK_SPBA 98 | ||
| 111 | #define IMX5_CLK_UART_SEL 99 | ||
| 112 | #define IMX5_CLK_ESDHC_A_SEL 100 | ||
| 113 | #define IMX5_CLK_ESDHC_B_SEL 101 | ||
| 114 | #define IMX5_CLK_ESDHC_A_PODF 102 | ||
| 115 | #define IMX5_CLK_ESDHC_B_PODF 103 | ||
| 116 | #define IMX5_CLK_ECSPI_SEL 104 | ||
| 117 | #define IMX5_CLK_USBOH3_SEL 105 | ||
| 118 | #define IMX5_CLK_USB_PHY_SEL 106 | ||
| 119 | #define IMX5_CLK_IIM_GATE 107 | ||
| 120 | #define IMX5_CLK_USBOH3_GATE 108 | ||
| 121 | #define IMX5_CLK_EMI_FAST_GATE 109 | ||
| 122 | #define IMX5_CLK_IPU_DI0_GATE 110 | ||
| 123 | #define IMX5_CLK_GPC_DVFS 111 | ||
| 124 | #define IMX5_CLK_PLL1_SW 112 | ||
| 125 | #define IMX5_CLK_PLL2_SW 113 | ||
| 126 | #define IMX5_CLK_PLL3_SW 114 | ||
| 127 | #define IMX5_CLK_IPU_DI0_SEL 115 | ||
| 128 | #define IMX5_CLK_IPU_DI1_SEL 116 | ||
| 129 | #define IMX5_CLK_TVE_EXT_SEL 117 | ||
| 130 | #define IMX5_CLK_MX51_MIPI 118 | ||
| 131 | #define IMX5_CLK_PLL4_SW 119 | ||
| 132 | #define IMX5_CLK_LDB_DI1_SEL 120 | ||
| 133 | #define IMX5_CLK_DI_PLL4_PODF 121 | ||
| 134 | #define IMX5_CLK_LDB_DI0_SEL 122 | ||
| 135 | #define IMX5_CLK_LDB_DI0_GATE 123 | ||
| 136 | #define IMX5_CLK_USB_PHY1_GATE 124 | ||
| 137 | #define IMX5_CLK_USB_PHY2_GATE 125 | ||
| 138 | #define IMX5_CLK_PER_LP_APM 126 | ||
| 139 | #define IMX5_CLK_PER_PRED1 127 | ||
| 140 | #define IMX5_CLK_PER_PRED2 128 | ||
| 141 | #define IMX5_CLK_PER_PODF 129 | ||
| 142 | #define IMX5_CLK_PER_ROOT 130 | ||
| 143 | #define IMX5_CLK_SSI_APM 131 | ||
| 144 | #define IMX5_CLK_SSI1_ROOT_SEL 132 | ||
| 145 | #define IMX5_CLK_SSI2_ROOT_SEL 133 | ||
| 146 | #define IMX5_CLK_SSI3_ROOT_SEL 134 | ||
| 147 | #define IMX5_CLK_SSI_EXT1_SEL 135 | ||
| 148 | #define IMX5_CLK_SSI_EXT2_SEL 136 | ||
| 149 | #define IMX5_CLK_SSI_EXT1_COM_SEL 137 | ||
| 150 | #define IMX5_CLK_SSI_EXT2_COM_SEL 138 | ||
| 151 | #define IMX5_CLK_SSI1_ROOT_PRED 139 | ||
| 152 | #define IMX5_CLK_SSI1_ROOT_PODF 140 | ||
| 153 | #define IMX5_CLK_SSI2_ROOT_PRED 141 | ||
| 154 | #define IMX5_CLK_SSI2_ROOT_PODF 142 | ||
| 155 | #define IMX5_CLK_SSI_EXT1_PRED 143 | ||
| 156 | #define IMX5_CLK_SSI_EXT1_PODF 144 | ||
| 157 | #define IMX5_CLK_SSI_EXT2_PRED 145 | ||
| 158 | #define IMX5_CLK_SSI_EXT2_PODF 146 | ||
| 159 | #define IMX5_CLK_SSI1_ROOT_GATE 147 | ||
| 160 | #define IMX5_CLK_SSI2_ROOT_GATE 148 | ||
| 161 | #define IMX5_CLK_SSI3_ROOT_GATE 149 | ||
| 162 | #define IMX5_CLK_SSI_EXT1_GATE 150 | ||
| 163 | #define IMX5_CLK_SSI_EXT2_GATE 151 | ||
| 164 | #define IMX5_CLK_EPIT1_IPG_GATE 152 | ||
| 165 | #define IMX5_CLK_EPIT1_HF_GATE 153 | ||
| 166 | #define IMX5_CLK_EPIT2_IPG_GATE 154 | ||
| 167 | #define IMX5_CLK_EPIT2_HF_GATE 155 | ||
| 168 | #define IMX5_CLK_CAN_SEL 156 | ||
| 169 | #define IMX5_CLK_CAN1_SERIAL_GATE 157 | ||
| 170 | #define IMX5_CLK_CAN1_IPG_GATE 158 | ||
| 171 | #define IMX5_CLK_OWIRE_GATE 159 | ||
| 172 | #define IMX5_CLK_GPU3D_SEL 160 | ||
| 173 | #define IMX5_CLK_GPU2D_SEL 161 | ||
| 174 | #define IMX5_CLK_GPU3D_GATE 162 | ||
| 175 | #define IMX5_CLK_GPU2D_GATE 163 | ||
| 176 | #define IMX5_CLK_GARB_GATE 164 | ||
| 177 | #define IMX5_CLK_CKO1_SEL 165 | ||
| 178 | #define IMX5_CLK_CKO1_PODF 166 | ||
| 179 | #define IMX5_CLK_CKO1 167 | ||
| 180 | #define IMX5_CLK_CKO2_SEL 168 | ||
| 181 | #define IMX5_CLK_CKO2_PODF 169 | ||
| 182 | #define IMX5_CLK_CKO2 170 | ||
| 183 | #define IMX5_CLK_SRTC_GATE 171 | ||
| 184 | #define IMX5_CLK_PATA_GATE 172 | ||
| 185 | #define IMX5_CLK_SATA_GATE 173 | ||
| 186 | #define IMX5_CLK_SPDIF_XTAL_SEL 174 | ||
| 187 | #define IMX5_CLK_SPDIF0_SEL 175 | ||
| 188 | #define IMX5_CLK_SPDIF1_SEL 176 | ||
| 189 | #define IMX5_CLK_SPDIF0_PRED 177 | ||
| 190 | #define IMX5_CLK_SPDIF0_PODF 178 | ||
| 191 | #define IMX5_CLK_SPDIF1_PRED 179 | ||
| 192 | #define IMX5_CLK_SPDIF1_PODF 180 | ||
| 193 | #define IMX5_CLK_SPDIF0_COM_SEL 181 | ||
| 194 | #define IMX5_CLK_SPDIF1_COM_SEL 182 | ||
| 195 | #define IMX5_CLK_SPDIF0_GATE 183 | ||
| 196 | #define IMX5_CLK_SPDIF1_GATE 184 | ||
| 197 | #define IMX5_CLK_SPDIF_IPG_GATE 185 | ||
| 198 | #define IMX5_CLK_OCRAM 186 | ||
| 199 | #define IMX5_CLK_SAHARA_IPG_GATE 187 | ||
| 200 | #define IMX5_CLK_SATA_REF 188 | ||
| 201 | #define IMX5_CLK_END 189 | ||
| 202 | |||
| 203 | #endif /* __DT_BINDINGS_CLOCK_IMX5_H */ | ||
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index 7fcdf90879f2..7cf5c9969336 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h | |||
| @@ -143,6 +143,8 @@ | |||
| 143 | #define IMX6SL_CLK_USDHC2 130 | 143 | #define IMX6SL_CLK_USDHC2 130 |
| 144 | #define IMX6SL_CLK_USDHC3 131 | 144 | #define IMX6SL_CLK_USDHC3 131 |
| 145 | #define IMX6SL_CLK_USDHC4 132 | 145 | #define IMX6SL_CLK_USDHC4 132 |
| 146 | #define IMX6SL_CLK_CLK_END 133 | 146 | #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 |
| 147 | #define IMX6SL_CLK_SPBA 134 | ||
| 148 | #define IMX6SL_CLK_END 135 | ||
| 147 | 149 | ||
| 148 | #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ | 150 | #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ |
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8660.h b/include/dt-bindings/clock/qcom,gcc-msm8660.h new file mode 100644 index 000000000000..67665f6813dd --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8660.h | |||
| @@ -0,0 +1,276 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H | ||
| 15 | #define _DT_BINDINGS_CLK_MSM_GCC_8660_H | ||
| 16 | |||
| 17 | #define AFAB_CLK_SRC 0 | ||
| 18 | #define AFAB_CORE_CLK 1 | ||
| 19 | #define SCSS_A_CLK 2 | ||
| 20 | #define SCSS_H_CLK 3 | ||
| 21 | #define SCSS_XO_SRC_CLK 4 | ||
| 22 | #define AFAB_EBI1_CH0_A_CLK 5 | ||
| 23 | #define AFAB_EBI1_CH1_A_CLK 6 | ||
| 24 | #define AFAB_AXI_S0_FCLK 7 | ||
| 25 | #define AFAB_AXI_S1_FCLK 8 | ||
| 26 | #define AFAB_AXI_S2_FCLK 9 | ||
| 27 | #define AFAB_AXI_S3_FCLK 10 | ||
| 28 | #define AFAB_AXI_S4_FCLK 11 | ||
| 29 | #define SFAB_CORE_CLK 12 | ||
| 30 | #define SFAB_AXI_S0_FCLK 13 | ||
| 31 | #define SFAB_AXI_S1_FCLK 14 | ||
| 32 | #define SFAB_AXI_S2_FCLK 15 | ||
| 33 | #define SFAB_AXI_S3_FCLK 16 | ||
| 34 | #define SFAB_AXI_S4_FCLK 17 | ||
| 35 | #define SFAB_AHB_S0_FCLK 18 | ||
| 36 | #define SFAB_AHB_S1_FCLK 19 | ||
| 37 | #define SFAB_AHB_S2_FCLK 20 | ||
| 38 | #define SFAB_AHB_S3_FCLK 21 | ||
| 39 | #define SFAB_AHB_S4_FCLK 22 | ||
| 40 | #define SFAB_AHB_S5_FCLK 23 | ||
| 41 | #define SFAB_AHB_S6_FCLK 24 | ||
| 42 | #define SFAB_ADM0_M0_A_CLK 25 | ||
| 43 | #define SFAB_ADM0_M1_A_CLK 26 | ||
| 44 | #define SFAB_ADM0_M2_A_CLK 27 | ||
| 45 | #define ADM0_CLK 28 | ||
| 46 | #define ADM0_PBUS_CLK 29 | ||
| 47 | #define SFAB_ADM1_M0_A_CLK 30 | ||
| 48 | #define SFAB_ADM1_M1_A_CLK 31 | ||
| 49 | #define SFAB_ADM1_M2_A_CLK 32 | ||
| 50 | #define MMFAB_ADM1_M3_A_CLK 33 | ||
| 51 | #define ADM1_CLK 34 | ||
| 52 | #define ADM1_PBUS_CLK 35 | ||
| 53 | #define IMEM0_A_CLK 36 | ||
| 54 | #define MAHB0_CLK 37 | ||
| 55 | #define SFAB_LPASS_Q6_A_CLK 38 | ||
| 56 | #define SFAB_AFAB_M_A_CLK 39 | ||
| 57 | #define AFAB_SFAB_M0_A_CLK 40 | ||
| 58 | #define AFAB_SFAB_M1_A_CLK 41 | ||
| 59 | #define DFAB_CLK_SRC 42 | ||
| 60 | #define DFAB_CLK 43 | ||
| 61 | #define DFAB_CORE_CLK 44 | ||
| 62 | #define SFAB_DFAB_M_A_CLK 45 | ||
| 63 | #define DFAB_SFAB_M_A_CLK 46 | ||
| 64 | #define DFAB_SWAY0_H_CLK 47 | ||
| 65 | #define DFAB_SWAY1_H_CLK 48 | ||
| 66 | #define DFAB_ARB0_H_CLK 49 | ||
| 67 | #define DFAB_ARB1_H_CLK 50 | ||
| 68 | #define PPSS_H_CLK 51 | ||
| 69 | #define PPSS_PROC_CLK 52 | ||
| 70 | #define PPSS_TIMER0_CLK 53 | ||
| 71 | #define PPSS_TIMER1_CLK 54 | ||
| 72 | #define PMEM_A_CLK 55 | ||
| 73 | #define DMA_BAM_H_CLK 56 | ||
| 74 | #define SIC_H_CLK 57 | ||
| 75 | #define SPS_TIC_H_CLK 58 | ||
| 76 | #define SLIMBUS_H_CLK 59 | ||
| 77 | #define SLIMBUS_XO_SRC_CLK 60 | ||
| 78 | #define CFPB_2X_CLK_SRC 61 | ||
| 79 | #define CFPB_CLK 62 | ||
| 80 | #define CFPB0_H_CLK 63 | ||
| 81 | #define CFPB1_H_CLK 64 | ||
| 82 | #define CFPB2_H_CLK 65 | ||
| 83 | #define EBI2_2X_CLK 66 | ||
| 84 | #define EBI2_CLK 67 | ||
| 85 | #define SFAB_CFPB_M_H_CLK 68 | ||
| 86 | #define CFPB_MASTER_H_CLK 69 | ||
| 87 | #define SFAB_CFPB_S_HCLK 70 | ||
| 88 | #define CFPB_SPLITTER_H_CLK 71 | ||
| 89 | #define TSIF_H_CLK 72 | ||
| 90 | #define TSIF_INACTIVITY_TIMERS_CLK 73 | ||
| 91 | #define TSIF_REF_SRC 74 | ||
| 92 | #define TSIF_REF_CLK 75 | ||
| 93 | #define CE1_H_CLK 76 | ||
| 94 | #define CE2_H_CLK 77 | ||
| 95 | #define SFPB_H_CLK_SRC 78 | ||
| 96 | #define SFPB_H_CLK 79 | ||
| 97 | #define SFAB_SFPB_M_H_CLK 80 | ||
| 98 | #define SFAB_SFPB_S_H_CLK 81 | ||
| 99 | #define RPM_PROC_CLK 82 | ||
| 100 | #define RPM_BUS_H_CLK 83 | ||
| 101 | #define RPM_SLEEP_CLK 84 | ||
| 102 | #define RPM_TIMER_CLK 85 | ||
| 103 | #define MODEM_AHB1_H_CLK 86 | ||
| 104 | #define MODEM_AHB2_H_CLK 87 | ||
| 105 | #define RPM_MSG_RAM_H_CLK 88 | ||
| 106 | #define SC_H_CLK 89 | ||
| 107 | #define SC_A_CLK 90 | ||
| 108 | #define PMIC_ARB0_H_CLK 91 | ||
| 109 | #define PMIC_ARB1_H_CLK 92 | ||
| 110 | #define PMIC_SSBI2_SRC 93 | ||
| 111 | #define PMIC_SSBI2_CLK 94 | ||
| 112 | #define SDC1_H_CLK 95 | ||
| 113 | #define SDC2_H_CLK 96 | ||
| 114 | #define SDC3_H_CLK 97 | ||
| 115 | #define SDC4_H_CLK 98 | ||
| 116 | #define SDC5_H_CLK 99 | ||
| 117 | #define SDC1_SRC 100 | ||
| 118 | #define SDC2_SRC 101 | ||
| 119 | #define SDC3_SRC 102 | ||
| 120 | #define SDC4_SRC 103 | ||
| 121 | #define SDC5_SRC 104 | ||
| 122 | #define SDC1_CLK 105 | ||
| 123 | #define SDC2_CLK 106 | ||
| 124 | #define SDC3_CLK 107 | ||
| 125 | #define SDC4_CLK 108 | ||
| 126 | #define SDC5_CLK 109 | ||
| 127 | #define USB_HS1_H_CLK 110 | ||
| 128 | #define USB_HS1_XCVR_SRC 111 | ||
| 129 | #define USB_HS1_XCVR_CLK 112 | ||
| 130 | #define USB_HS2_H_CLK 113 | ||
| 131 | #define USB_HS2_XCVR_SRC 114 | ||
| 132 | #define USB_HS2_XCVR_CLK 115 | ||
| 133 | #define USB_FS1_H_CLK 116 | ||
| 134 | #define USB_FS1_XCVR_FS_SRC 117 | ||
| 135 | #define USB_FS1_XCVR_FS_CLK 118 | ||
| 136 | #define USB_FS1_SYSTEM_CLK 119 | ||
| 137 | #define USB_FS2_H_CLK 120 | ||
| 138 | #define USB_FS2_XCVR_FS_SRC 121 | ||
| 139 | #define USB_FS2_XCVR_FS_CLK 122 | ||
| 140 | #define USB_FS2_SYSTEM_CLK 123 | ||
| 141 | #define GSBI_COMMON_SIM_SRC 124 | ||
| 142 | #define GSBI1_H_CLK 125 | ||
| 143 | #define GSBI2_H_CLK 126 | ||
| 144 | #define GSBI3_H_CLK 127 | ||
| 145 | #define GSBI4_H_CLK 128 | ||
| 146 | #define GSBI5_H_CLK 129 | ||
| 147 | #define GSBI6_H_CLK 130 | ||
| 148 | #define GSBI7_H_CLK 131 | ||
| 149 | #define GSBI8_H_CLK 132 | ||
| 150 | #define GSBI9_H_CLK 133 | ||
| 151 | #define GSBI10_H_CLK 134 | ||
| 152 | #define GSBI11_H_CLK 135 | ||
| 153 | #define GSBI12_H_CLK 136 | ||
| 154 | #define GSBI1_UART_SRC 137 | ||
| 155 | #define GSBI1_UART_CLK 138 | ||
| 156 | #define GSBI2_UART_SRC 139 | ||
| 157 | #define GSBI2_UART_CLK 140 | ||
| 158 | #define GSBI3_UART_SRC 141 | ||
| 159 | #define GSBI3_UART_CLK 142 | ||
| 160 | #define GSBI4_UART_SRC 143 | ||
| 161 | #define GSBI4_UART_CLK 144 | ||
| 162 | #define GSBI5_UART_SRC 145 | ||
| 163 | #define GSBI5_UART_CLK 146 | ||
| 164 | #define GSBI6_UART_SRC 147 | ||
| 165 | #define GSBI6_UART_CLK 148 | ||
| 166 | #define GSBI7_UART_SRC 149 | ||
| 167 | #define GSBI7_UART_CLK 150 | ||
| 168 | #define GSBI8_UART_SRC 151 | ||
| 169 | #define GSBI8_UART_CLK 152 | ||
| 170 | #define GSBI9_UART_SRC 153 | ||
| 171 | #define GSBI9_UART_CLK 154 | ||
| 172 | #define GSBI10_UART_SRC 155 | ||
| 173 | #define GSBI10_UART_CLK 156 | ||
| 174 | #define GSBI11_UART_SRC 157 | ||
| 175 | #define GSBI11_UART_CLK 158 | ||
| 176 | #define GSBI12_UART_SRC 159 | ||
| 177 | #define GSBI12_UART_CLK 160 | ||
| 178 | #define GSBI1_QUP_SRC 161 | ||
| 179 | #define GSBI1_QUP_CLK 162 | ||
| 180 | #define GSBI2_QUP_SRC 163 | ||
| 181 | #define GSBI2_QUP_CLK 164 | ||
| 182 | #define GSBI3_QUP_SRC 165 | ||
| 183 | #define GSBI3_QUP_CLK 166 | ||
| 184 | #define GSBI4_QUP_SRC 167 | ||
| 185 | #define GSBI4_QUP_CLK 168 | ||
| 186 | #define GSBI5_QUP_SRC 169 | ||
| 187 | #define GSBI5_QUP_CLK 170 | ||
| 188 | #define GSBI6_QUP_SRC 171 | ||
| 189 | #define GSBI6_QUP_CLK 172 | ||
| 190 | #define GSBI7_QUP_SRC 173 | ||
| 191 | #define GSBI7_QUP_CLK 174 | ||
| 192 | #define GSBI8_QUP_SRC 175 | ||
| 193 | #define GSBI8_QUP_CLK 176 | ||
| 194 | #define GSBI9_QUP_SRC 177 | ||
| 195 | #define GSBI9_QUP_CLK 178 | ||
| 196 | #define GSBI10_QUP_SRC 179 | ||
| 197 | #define GSBI10_QUP_CLK 180 | ||
| 198 | #define GSBI11_QUP_SRC 181 | ||
| 199 | #define GSBI11_QUP_CLK 182 | ||
| 200 | #define GSBI12_QUP_SRC 183 | ||
| 201 | #define GSBI12_QUP_CLK 184 | ||
| 202 | #define GSBI1_SIM_CLK 185 | ||
| 203 | #define GSBI2_SIM_CLK 186 | ||
| 204 | #define GSBI3_SIM_CLK 187 | ||
| 205 | #define GSBI4_SIM_CLK 188 | ||
| 206 | #define GSBI5_SIM_CLK 189 | ||
| 207 | #define GSBI6_SIM_CLK 190 | ||
| 208 | #define GSBI7_SIM_CLK 191 | ||
| 209 | #define GSBI8_SIM_CLK 192 | ||
| 210 | #define GSBI9_SIM_CLK 193 | ||
| 211 | #define GSBI10_SIM_CLK 194 | ||
| 212 | #define GSBI11_SIM_CLK 195 | ||
| 213 | #define GSBI12_SIM_CLK 196 | ||
| 214 | #define SPDM_CFG_H_CLK 197 | ||
| 215 | #define SPDM_MSTR_H_CLK 198 | ||
| 216 | #define SPDM_FF_CLK_SRC 199 | ||
| 217 | #define SPDM_FF_CLK 200 | ||
| 218 | #define SEC_CTRL_CLK 201 | ||
| 219 | #define SEC_CTRL_ACC_CLK_SRC 202 | ||
| 220 | #define SEC_CTRL_ACC_CLK 203 | ||
| 221 | #define TLMM_H_CLK 204 | ||
| 222 | #define TLMM_CLK 205 | ||
| 223 | #define MARM_CLK_SRC 206 | ||
| 224 | #define MARM_CLK 207 | ||
| 225 | #define MAHB1_SRC 208 | ||
| 226 | #define MAHB1_CLK 209 | ||
| 227 | #define SFAB_MSS_S_H_CLK 210 | ||
| 228 | #define MAHB2_SRC 211 | ||
| 229 | #define MAHB2_CLK 212 | ||
| 230 | #define MSS_MODEM_CLK_SRC 213 | ||
| 231 | #define MSS_MODEM_CXO_CLK 214 | ||
| 232 | #define MSS_SLP_CLK 215 | ||
| 233 | #define MSS_SYS_REF_CLK 216 | ||
| 234 | #define TSSC_CLK_SRC 217 | ||
| 235 | #define TSSC_CLK 218 | ||
| 236 | #define PDM_SRC 219 | ||
| 237 | #define PDM_CLK 220 | ||
| 238 | #define GP0_SRC 221 | ||
| 239 | #define GP0_CLK 222 | ||
| 240 | #define GP1_SRC 223 | ||
| 241 | #define GP1_CLK 224 | ||
| 242 | #define GP2_SRC 225 | ||
| 243 | #define GP2_CLK 226 | ||
| 244 | #define PMEM_CLK 227 | ||
| 245 | #define MPM_CLK 228 | ||
| 246 | #define EBI1_ASFAB_SRC 229 | ||
| 247 | #define EBI1_CLK_SRC 230 | ||
| 248 | #define EBI1_CH0_CLK 231 | ||
| 249 | #define EBI1_CH1_CLK 232 | ||
| 250 | #define SFAB_SMPSS_S_H_CLK 233 | ||
| 251 | #define PRNG_SRC 234 | ||
| 252 | #define PRNG_CLK 235 | ||
| 253 | #define PXO_SRC 236 | ||
| 254 | #define LPASS_CXO_CLK 237 | ||
| 255 | #define LPASS_PXO_CLK 238 | ||
| 256 | #define SPDM_CY_PORT0_CLK 239 | ||
| 257 | #define SPDM_CY_PORT1_CLK 240 | ||
| 258 | #define SPDM_CY_PORT2_CLK 241 | ||
| 259 | #define SPDM_CY_PORT3_CLK 242 | ||
| 260 | #define SPDM_CY_PORT4_CLK 243 | ||
| 261 | #define SPDM_CY_PORT5_CLK 244 | ||
| 262 | #define SPDM_CY_PORT6_CLK 245 | ||
| 263 | #define SPDM_CY_PORT7_CLK 246 | ||
| 264 | #define PLL0 247 | ||
| 265 | #define PLL0_VOTE 248 | ||
| 266 | #define PLL5 249 | ||
| 267 | #define PLL6 250 | ||
| 268 | #define PLL6_VOTE 251 | ||
| 269 | #define PLL8 252 | ||
| 270 | #define PLL8_VOTE 253 | ||
| 271 | #define PLL9 254 | ||
| 272 | #define PLL10 255 | ||
| 273 | #define PLL11 256 | ||
| 274 | #define PLL12 257 | ||
| 275 | |||
| 276 | #endif | ||
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h new file mode 100644 index 000000000000..03bbf49d43b7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h | |||
| @@ -0,0 +1,313 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H | ||
| 15 | #define _DT_BINDINGS_CLK_MSM_GCC_8960_H | ||
| 16 | |||
| 17 | #define AFAB_CLK_SRC 0 | ||
| 18 | #define AFAB_CORE_CLK 1 | ||
| 19 | #define SFAB_MSS_Q6_SW_A_CLK 2 | ||
| 20 | #define SFAB_MSS_Q6_FW_A_CLK 3 | ||
| 21 | #define QDSS_STM_CLK 4 | ||
| 22 | #define SCSS_A_CLK 5 | ||
| 23 | #define SCSS_H_CLK 6 | ||
| 24 | #define SCSS_XO_SRC_CLK 7 | ||
| 25 | #define AFAB_EBI1_CH0_A_CLK 8 | ||
| 26 | #define AFAB_EBI1_CH1_A_CLK 9 | ||
| 27 | #define AFAB_AXI_S0_FCLK 10 | ||
| 28 | #define AFAB_AXI_S1_FCLK 11 | ||
| 29 | #define AFAB_AXI_S2_FCLK 12 | ||
| 30 | #define AFAB_AXI_S3_FCLK 13 | ||
| 31 | #define AFAB_AXI_S4_FCLK 14 | ||
| 32 | #define SFAB_CORE_CLK 15 | ||
| 33 | #define SFAB_AXI_S0_FCLK 16 | ||
| 34 | #define SFAB_AXI_S1_FCLK 17 | ||
| 35 | #define SFAB_AXI_S2_FCLK 18 | ||
| 36 | #define SFAB_AXI_S3_FCLK 19 | ||
| 37 | #define SFAB_AXI_S4_FCLK 20 | ||
| 38 | #define SFAB_AHB_S0_FCLK 21 | ||
| 39 | #define SFAB_AHB_S1_FCLK 22 | ||
| 40 | #define SFAB_AHB_S2_FCLK 23 | ||
| 41 | #define SFAB_AHB_S3_FCLK 24 | ||
| 42 | #define SFAB_AHB_S4_FCLK 25 | ||
| 43 | #define SFAB_AHB_S5_FCLK 26 | ||
| 44 | #define SFAB_AHB_S6_FCLK 27 | ||
| 45 | #define SFAB_AHB_S7_FCLK 28 | ||
| 46 | #define QDSS_AT_CLK_SRC 29 | ||
| 47 | #define QDSS_AT_CLK 30 | ||
| 48 | #define QDSS_TRACECLKIN_CLK_SRC 31 | ||
| 49 | #define QDSS_TRACECLKIN_CLK 32 | ||
| 50 | #define QDSS_TSCTR_CLK_SRC 33 | ||
| 51 | #define QDSS_TSCTR_CLK 34 | ||
| 52 | #define SFAB_ADM0_M0_A_CLK 35 | ||
| 53 | #define SFAB_ADM0_M1_A_CLK 36 | ||
| 54 | #define SFAB_ADM0_M2_A_CLK 37 | ||
| 55 | #define ADM0_CLK 38 | ||
| 56 | #define ADM0_PBUS_CLK 39 | ||
| 57 | #define MSS_XPU_CLK 40 | ||
| 58 | #define IMEM0_A_CLK 41 | ||
| 59 | #define QDSS_H_CLK 42 | ||
| 60 | #define PCIE_A_CLK 43 | ||
| 61 | #define PCIE_AUX_CLK 44 | ||
| 62 | #define PCIE_PHY_REF_CLK 45 | ||
| 63 | #define PCIE_H_CLK 46 | ||
| 64 | #define SFAB_CLK_SRC 47 | ||
| 65 | #define MAHB0_CLK 48 | ||
| 66 | #define Q6SW_CLK_SRC 49 | ||
| 67 | #define Q6SW_CLK 50 | ||
| 68 | #define Q6FW_CLK_SRC 51 | ||
| 69 | #define Q6FW_CLK 52 | ||
| 70 | #define SFAB_MSS_M_A_CLK 53 | ||
| 71 | #define SFAB_USB3_M_A_CLK 54 | ||
| 72 | #define SFAB_LPASS_Q6_A_CLK 55 | ||
| 73 | #define SFAB_AFAB_M_A_CLK 56 | ||
| 74 | #define AFAB_SFAB_M0_A_CLK 57 | ||
| 75 | #define AFAB_SFAB_M1_A_CLK 58 | ||
| 76 | #define SFAB_SATA_S_H_CLK 59 | ||
| 77 | #define DFAB_CLK_SRC 60 | ||
| 78 | #define DFAB_CLK 61 | ||
| 79 | #define SFAB_DFAB_M_A_CLK 62 | ||
| 80 | #define DFAB_SFAB_M_A_CLK 63 | ||
| 81 | #define DFAB_SWAY0_H_CLK 64 | ||
| 82 | #define DFAB_SWAY1_H_CLK 65 | ||
| 83 | #define DFAB_ARB0_H_CLK 66 | ||
| 84 | #define DFAB_ARB1_H_CLK 67 | ||
| 85 | #define PPSS_H_CLK 68 | ||
| 86 | #define PPSS_PROC_CLK 69 | ||
| 87 | #define PPSS_TIMER0_CLK 70 | ||
| 88 | #define PPSS_TIMER1_CLK 71 | ||
| 89 | #define PMEM_A_CLK 72 | ||
| 90 | #define DMA_BAM_H_CLK 73 | ||
| 91 | #define SIC_H_CLK 74 | ||
| 92 | #define SPS_TIC_H_CLK 75 | ||
| 93 | #define SLIMBUS_H_CLK 76 | ||
| 94 | #define SLIMBUS_XO_SRC_CLK 77 | ||
| 95 | #define CFPB_2X_CLK_SRC 78 | ||
| 96 | #define CFPB_CLK 79 | ||
| 97 | #define CFPB0_H_CLK 80 | ||
| 98 | #define CFPB1_H_CLK 81 | ||
| 99 | #define CFPB2_H_CLK 82 | ||
| 100 | #define SFAB_CFPB_M_H_CLK 83 | ||
| 101 | #define CFPB_MASTER_H_CLK 84 | ||
| 102 | #define SFAB_CFPB_S_HCLK 85 | ||
| 103 | #define CFPB_SPLITTER_H_CLK 86 | ||
| 104 | #define TSIF_H_CLK 87 | ||
| 105 | #define TSIF_INACTIVITY_TIMERS_CLK 88 | ||
| 106 | #define TSIF_REF_SRC 89 | ||
| 107 | #define TSIF_REF_CLK 90 | ||
| 108 | #define CE1_H_CLK 91 | ||
| 109 | #define CE1_CORE_CLK 92 | ||
| 110 | #define CE1_SLEEP_CLK 93 | ||
| 111 | #define CE2_H_CLK 94 | ||
| 112 | #define CE2_CORE_CLK 95 | ||
| 113 | #define CE2_SLEEP_CLK 96 | ||
| 114 | #define SFPB_H_CLK_SRC 97 | ||
| 115 | #define SFPB_H_CLK 98 | ||
| 116 | #define SFAB_SFPB_M_H_CLK 99 | ||
| 117 | #define SFAB_SFPB_S_H_CLK 100 | ||
| 118 | #define RPM_PROC_CLK 101 | ||
| 119 | #define RPM_BUS_H_CLK 102 | ||
| 120 | #define RPM_SLEEP_CLK 103 | ||
| 121 | #define RPM_TIMER_CLK 104 | ||
| 122 | #define RPM_MSG_RAM_H_CLK 105 | ||
| 123 | #define PMIC_ARB0_H_CLK 106 | ||
| 124 | #define PMIC_ARB1_H_CLK 107 | ||
| 125 | #define PMIC_SSBI2_SRC 108 | ||
| 126 | #define PMIC_SSBI2_CLK 109 | ||
| 127 | #define SDC1_H_CLK 110 | ||
| 128 | #define SDC2_H_CLK 111 | ||
| 129 | #define SDC3_H_CLK 112 | ||
| 130 | #define SDC4_H_CLK 113 | ||
| 131 | #define SDC5_H_CLK 114 | ||
| 132 | #define SDC1_SRC 115 | ||
| 133 | #define SDC2_SRC 116 | ||
| 134 | #define SDC3_SRC 117 | ||
| 135 | #define SDC4_SRC 118 | ||
| 136 | #define SDC5_SRC 119 | ||
| 137 | #define SDC1_CLK 120 | ||
| 138 | #define SDC2_CLK 121 | ||
| 139 | #define SDC3_CLK 122 | ||
| 140 | #define SDC4_CLK 123 | ||
| 141 | #define SDC5_CLK 124 | ||
| 142 | #define DFAB_A2_H_CLK 125 | ||
| 143 | #define USB_HS1_H_CLK 126 | ||
| 144 | #define USB_HS1_XCVR_SRC 127 | ||
| 145 | #define USB_HS1_XCVR_CLK 128 | ||
| 146 | #define USB_HSIC_H_CLK 129 | ||
| 147 | #define USB_HSIC_XCVR_FS_SRC 130 | ||
| 148 | #define USB_HSIC_XCVR_FS_CLK 131 | ||
| 149 | #define USB_HSIC_SYSTEM_CLK_SRC 132 | ||
| 150 | #define USB_HSIC_SYSTEM_CLK 133 | ||
| 151 | #define CFPB0_C0_H_CLK 134 | ||
| 152 | #define CFPB0_C1_H_CLK 135 | ||
| 153 | #define CFPB0_D0_H_CLK 136 | ||
| 154 | #define CFPB0_D1_H_CLK 137 | ||
| 155 | #define USB_FS1_H_CLK 138 | ||
| 156 | #define USB_FS1_XCVR_FS_SRC 139 | ||
| 157 | #define USB_FS1_XCVR_FS_CLK 140 | ||
| 158 | #define USB_FS1_SYSTEM_CLK 141 | ||
| 159 | #define USB_FS2_H_CLK 142 | ||
| 160 | #define USB_FS2_XCVR_FS_SRC 143 | ||
| 161 | #define USB_FS2_XCVR_FS_CLK 144 | ||
| 162 | #define USB_FS2_SYSTEM_CLK 145 | ||
| 163 | #define GSBI_COMMON_SIM_SRC 146 | ||
| 164 | #define GSBI1_H_CLK 147 | ||
| 165 | #define GSBI2_H_CLK 148 | ||
| 166 | #define GSBI3_H_CLK 149 | ||
| 167 | #define GSBI4_H_CLK 150 | ||
| 168 | #define GSBI5_H_CLK 151 | ||
| 169 | #define GSBI6_H_CLK 152 | ||
| 170 | #define GSBI7_H_CLK 153 | ||
| 171 | #define GSBI8_H_CLK 154 | ||
| 172 | #define GSBI9_H_CLK 155 | ||
| 173 | #define GSBI10_H_CLK 156 | ||
| 174 | #define GSBI11_H_CLK 157 | ||
| 175 | #define GSBI12_H_CLK 158 | ||
| 176 | #define GSBI1_UART_SRC 159 | ||
| 177 | #define GSBI1_UART_CLK 160 | ||
| 178 | #define GSBI2_UART_SRC 161 | ||
| 179 | #define GSBI2_UART_CLK 162 | ||
| 180 | #define GSBI3_UART_SRC 163 | ||
| 181 | #define GSBI3_UART_CLK 164 | ||
| 182 | #define GSBI4_UART_SRC 165 | ||
| 183 | #define GSBI4_UART_CLK 166 | ||
| 184 | #define GSBI5_UART_SRC 167 | ||
| 185 | #define GSBI5_UART_CLK 168 | ||
| 186 | #define GSBI6_UART_SRC 169 | ||
| 187 | #define GSBI6_UART_CLK 170 | ||
| 188 | #define GSBI7_UART_SRC 171 | ||
| 189 | #define GSBI7_UART_CLK 172 | ||
| 190 | #define GSBI8_UART_SRC 173 | ||
| 191 | #define GSBI8_UART_CLK 174 | ||
| 192 | #define GSBI9_UART_SRC 175 | ||
| 193 | #define GSBI9_UART_CLK 176 | ||
| 194 | #define GSBI10_UART_SRC 177 | ||
| 195 | #define GSBI10_UART_CLK 178 | ||
| 196 | #define GSBI11_UART_SRC 179 | ||
| 197 | #define GSBI11_UART_CLK 180 | ||
| 198 | #define GSBI12_UART_SRC 181 | ||
| 199 | #define GSBI12_UART_CLK 182 | ||
| 200 | #define GSBI1_QUP_SRC 183 | ||
| 201 | #define GSBI1_QUP_CLK 184 | ||
| 202 | #define GSBI2_QUP_SRC 185 | ||
| 203 | #define GSBI2_QUP_CLK 186 | ||
| 204 | #define GSBI3_QUP_SRC 187 | ||
| 205 | #define GSBI3_QUP_CLK 188 | ||
| 206 | #define GSBI4_QUP_SRC 189 | ||
| 207 | #define GSBI4_QUP_CLK 190 | ||
| 208 | #define GSBI5_QUP_SRC 191 | ||
| 209 | #define GSBI5_QUP_CLK 192 | ||
| 210 | #define GSBI6_QUP_SRC 193 | ||
| 211 | #define GSBI6_QUP_CLK 194 | ||
| 212 | #define GSBI7_QUP_SRC 195 | ||
| 213 | #define GSBI7_QUP_CLK 196 | ||
| 214 | #define GSBI8_QUP_SRC 197 | ||
| 215 | #define GSBI8_QUP_CLK 198 | ||
| 216 | #define GSBI9_QUP_SRC 199 | ||
| 217 | #define GSBI9_QUP_CLK 200 | ||
| 218 | #define GSBI10_QUP_SRC 201 | ||
| 219 | #define GSBI10_QUP_CLK 202 | ||
| 220 | #define GSBI11_QUP_SRC 203 | ||
| 221 | #define GSBI11_QUP_CLK 204 | ||
| 222 | #define GSBI12_QUP_SRC 205 | ||
| 223 | #define GSBI12_QUP_CLK 206 | ||
| 224 | #define GSBI1_SIM_CLK 207 | ||
| 225 | #define GSBI2_SIM_CLK 208 | ||
| 226 | #define GSBI3_SIM_CLK 209 | ||
| 227 | #define GSBI4_SIM_CLK 210 | ||
| 228 | #define GSBI5_SIM_CLK 211 | ||
| 229 | #define GSBI6_SIM_CLK 212 | ||
| 230 | #define GSBI7_SIM_CLK 213 | ||
| 231 | #define GSBI8_SIM_CLK 214 | ||
| 232 | #define GSBI9_SIM_CLK 215 | ||
| 233 | #define GSBI10_SIM_CLK 216 | ||
| 234 | #define GSBI11_SIM_CLK 217 | ||
| 235 | #define GSBI12_SIM_CLK 218 | ||
| 236 | #define USB_HSIC_HSIC_CLK_SRC 219 | ||
| 237 | #define USB_HSIC_HSIC_CLK 220 | ||
| 238 | #define USB_HSIC_HSIO_CAL_CLK 221 | ||
| 239 | #define SPDM_CFG_H_CLK 222 | ||
| 240 | #define SPDM_MSTR_H_CLK 223 | ||
| 241 | #define SPDM_FF_CLK_SRC 224 | ||
| 242 | #define SPDM_FF_CLK 225 | ||
| 243 | #define SEC_CTRL_CLK 226 | ||
| 244 | #define SEC_CTRL_ACC_CLK_SRC 227 | ||
| 245 | #define SEC_CTRL_ACC_CLK 228 | ||
| 246 | #define TLMM_H_CLK 229 | ||
| 247 | #define TLMM_CLK 230 | ||
| 248 | #define SFAB_MSS_S_H_CLK 231 | ||
| 249 | #define MSS_SLP_CLK 232 | ||
| 250 | #define MSS_Q6SW_JTAG_CLK 233 | ||
| 251 | #define MSS_Q6FW_JTAG_CLK 234 | ||
| 252 | #define MSS_S_H_CLK 235 | ||
| 253 | #define MSS_CXO_SRC_CLK 236 | ||
| 254 | #define SATA_H_CLK 237 | ||
| 255 | #define SATA_SRC_CLK 238 | ||
| 256 | #define SATA_RXOOB_CLK 239 | ||
| 257 | #define SATA_PMALIVE_CLK 240 | ||
| 258 | #define SATA_PHY_REF_CLK 241 | ||
| 259 | #define TSSC_CLK_SRC 242 | ||
| 260 | #define TSSC_CLK 243 | ||
| 261 | #define PDM_SRC 244 | ||
| 262 | #define PDM_CLK 245 | ||
| 263 | #define GP0_SRC 246 | ||
| 264 | #define GP0_CLK 247 | ||
| 265 | #define GP1_SRC 248 | ||
| 266 | #define GP1_CLK 249 | ||
| 267 | #define GP2_SRC 250 | ||
| 268 | #define GP2_CLK 251 | ||
| 269 | #define MPM_CLK 252 | ||
| 270 | #define EBI1_CLK_SRC 253 | ||
| 271 | #define EBI1_CH0_CLK 254 | ||
| 272 | #define EBI1_CH1_CLK 255 | ||
| 273 | #define EBI1_2X_CLK 256 | ||
| 274 | #define EBI1_CH0_DQ_CLK 257 | ||
| 275 | #define EBI1_CH1_DQ_CLK 258 | ||
| 276 | #define EBI1_CH0_CA_CLK 259 | ||
| 277 | #define EBI1_CH1_CA_CLK 260 | ||
| 278 | #define EBI1_XO_CLK 261 | ||
| 279 | #define SFAB_SMPSS_S_H_CLK 262 | ||
| 280 | #define PRNG_SRC 263 | ||
| 281 | #define PRNG_CLK 264 | ||
| 282 | #define PXO_SRC 265 | ||
| 283 | #define LPASS_CXO_CLK 266 | ||
| 284 | #define LPASS_PXO_CLK 267 | ||
| 285 | #define SPDM_CY_PORT0_CLK 268 | ||
| 286 | #define SPDM_CY_PORT1_CLK 269 | ||
| 287 | #define SPDM_CY_PORT2_CLK 270 | ||
| 288 | #define SPDM_CY_PORT3_CLK 271 | ||
| 289 | #define SPDM_CY_PORT4_CLK 272 | ||
| 290 | #define SPDM_CY_PORT5_CLK 273 | ||
| 291 | #define SPDM_CY_PORT6_CLK 274 | ||
| 292 | #define SPDM_CY_PORT7_CLK 275 | ||
| 293 | #define PLL0 276 | ||
| 294 | #define PLL0_VOTE 277 | ||
| 295 | #define PLL3 278 | ||
| 296 | #define PLL3_VOTE 279 | ||
| 297 | #define PLL4_VOTE 280 | ||
| 298 | #define PLL5 281 | ||
| 299 | #define PLL5_VOTE 282 | ||
| 300 | #define PLL6 283 | ||
| 301 | #define PLL6_VOTE 284 | ||
| 302 | #define PLL7_VOTE 285 | ||
| 303 | #define PLL8 286 | ||
| 304 | #define PLL8_VOTE 287 | ||
| 305 | #define PLL9 288 | ||
| 306 | #define PLL10 289 | ||
| 307 | #define PLL11 290 | ||
| 308 | #define PLL12 291 | ||
| 309 | #define PLL13 292 | ||
| 310 | #define PLL14 293 | ||
| 311 | #define PLL14_VOTE 294 | ||
| 312 | |||
| 313 | #endif | ||
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h new file mode 100644 index 000000000000..223ca174d9d3 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h | |||
| @@ -0,0 +1,320 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H | ||
| 15 | #define _DT_BINDINGS_CLK_MSM_GCC_8974_H | ||
| 16 | |||
| 17 | #define GPLL0 0 | ||
| 18 | #define GPLL0_VOTE 1 | ||
| 19 | #define CONFIG_NOC_CLK_SRC 2 | ||
| 20 | #define GPLL2 3 | ||
| 21 | #define GPLL2_VOTE 4 | ||
| 22 | #define GPLL3 5 | ||
| 23 | #define GPLL3_VOTE 6 | ||
| 24 | #define PERIPH_NOC_CLK_SRC 7 | ||
| 25 | #define BLSP_UART_SIM_CLK_SRC 8 | ||
| 26 | #define QDSS_TSCTR_CLK_SRC 9 | ||
| 27 | #define BIMC_DDR_CLK_SRC 10 | ||
| 28 | #define SYSTEM_NOC_CLK_SRC 11 | ||
| 29 | #define GPLL1 12 | ||
| 30 | #define GPLL1_VOTE 13 | ||
| 31 | #define RPM_CLK_SRC 14 | ||
| 32 | #define GCC_BIMC_CLK 15 | ||
| 33 | #define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 | ||
| 34 | #define KPSS_AHB_CLK_SRC 17 | ||
| 35 | #define QDSS_AT_CLK_SRC 18 | ||
| 36 | #define USB30_MASTER_CLK_SRC 19 | ||
| 37 | #define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 | ||
| 38 | #define QDSS_STM_CLK_SRC 21 | ||
| 39 | #define ACC_CLK_SRC 22 | ||
| 40 | #define SEC_CTRL_CLK_SRC 23 | ||
| 41 | #define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 | ||
| 42 | #define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 | ||
| 43 | #define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 | ||
| 44 | #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 | ||
| 45 | #define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 | ||
| 46 | #define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 | ||
| 47 | #define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 | ||
| 48 | #define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 | ||
| 49 | #define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 | ||
| 50 | #define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 | ||
| 51 | #define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 | ||
| 52 | #define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 | ||
| 53 | #define BLSP1_UART1_APPS_CLK_SRC 36 | ||
| 54 | #define BLSP1_UART2_APPS_CLK_SRC 37 | ||
| 55 | #define BLSP1_UART3_APPS_CLK_SRC 38 | ||
| 56 | #define BLSP1_UART4_APPS_CLK_SRC 39 | ||
| 57 | #define BLSP1_UART5_APPS_CLK_SRC 40 | ||
| 58 | #define BLSP1_UART6_APPS_CLK_SRC 41 | ||
| 59 | #define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 | ||
| 60 | #define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 | ||
| 61 | #define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 | ||
| 62 | #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 | ||
| 63 | #define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 | ||
| 64 | #define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 | ||
| 65 | #define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 | ||
| 66 | #define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 | ||
| 67 | #define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 | ||
| 68 | #define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 | ||
| 69 | #define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 | ||
| 70 | #define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 | ||
| 71 | #define BLSP2_UART1_APPS_CLK_SRC 54 | ||
| 72 | #define BLSP2_UART2_APPS_CLK_SRC 55 | ||
| 73 | #define BLSP2_UART3_APPS_CLK_SRC 56 | ||
| 74 | #define BLSP2_UART4_APPS_CLK_SRC 57 | ||
| 75 | #define BLSP2_UART5_APPS_CLK_SRC 58 | ||
| 76 | #define BLSP2_UART6_APPS_CLK_SRC 59 | ||
| 77 | #define CE1_CLK_SRC 60 | ||
| 78 | #define CE2_CLK_SRC 61 | ||
| 79 | #define GP1_CLK_SRC 62 | ||
| 80 | #define GP2_CLK_SRC 63 | ||
| 81 | #define GP3_CLK_SRC 64 | ||
| 82 | #define PDM2_CLK_SRC 65 | ||
| 83 | #define QDSS_TRACECLKIN_CLK_SRC 66 | ||
| 84 | #define RBCPR_CLK_SRC 67 | ||
| 85 | #define SDCC1_APPS_CLK_SRC 68 | ||
| 86 | #define SDCC2_APPS_CLK_SRC 69 | ||
| 87 | #define SDCC3_APPS_CLK_SRC 70 | ||
| 88 | #define SDCC4_APPS_CLK_SRC 71 | ||
| 89 | #define SPMI_AHB_CLK_SRC 72 | ||
| 90 | #define SPMI_SER_CLK_SRC 73 | ||
| 91 | #define TSIF_REF_CLK_SRC 74 | ||
| 92 | #define USB30_MOCK_UTMI_CLK_SRC 75 | ||
| 93 | #define USB_HS_SYSTEM_CLK_SRC 76 | ||
| 94 | #define USB_HSIC_CLK_SRC 77 | ||
| 95 | #define USB_HSIC_IO_CAL_CLK_SRC 78 | ||
| 96 | #define USB_HSIC_SYSTEM_CLK_SRC 79 | ||
| 97 | #define GCC_BAM_DMA_AHB_CLK 80 | ||
| 98 | #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 | ||
| 99 | #define GCC_BIMC_CFG_AHB_CLK 82 | ||
| 100 | #define GCC_BIMC_KPSS_AXI_CLK 83 | ||
| 101 | #define GCC_BIMC_SLEEP_CLK 84 | ||
| 102 | #define GCC_BIMC_SYSNOC_AXI_CLK 85 | ||
| 103 | #define GCC_BIMC_XO_CLK 86 | ||
| 104 | #define GCC_BLSP1_AHB_CLK 87 | ||
| 105 | #define GCC_BLSP1_SLEEP_CLK 88 | ||
| 106 | #define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 | ||
| 107 | #define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 | ||
| 108 | #define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 | ||
| 109 | #define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 | ||
| 110 | #define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 | ||
| 111 | #define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 | ||
| 112 | #define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 | ||
| 113 | #define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 | ||
| 114 | #define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 | ||
| 115 | #define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 | ||
| 116 | #define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 | ||
| 117 | #define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 | ||
| 118 | #define GCC_BLSP1_UART1_APPS_CLK 101 | ||
| 119 | #define GCC_BLSP1_UART1_SIM_CLK 102 | ||
| 120 | #define GCC_BLSP1_UART2_APPS_CLK 103 | ||
| 121 | #define GCC_BLSP1_UART2_SIM_CLK 104 | ||
| 122 | #define GCC_BLSP1_UART3_APPS_CLK 105 | ||
| 123 | #define GCC_BLSP1_UART3_SIM_CLK 106 | ||
| 124 | #define GCC_BLSP1_UART4_APPS_CLK 107 | ||
| 125 | #define GCC_BLSP1_UART4_SIM_CLK 108 | ||
| 126 | #define GCC_BLSP1_UART5_APPS_CLK 109 | ||
| 127 | #define GCC_BLSP1_UART5_SIM_CLK 110 | ||
| 128 | #define GCC_BLSP1_UART6_APPS_CLK 111 | ||
| 129 | #define GCC_BLSP1_UART6_SIM_CLK 112 | ||
| 130 | #define GCC_BLSP2_AHB_CLK 113 | ||
| 131 | #define GCC_BLSP2_SLEEP_CLK 114 | ||
| 132 | #define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 | ||
| 133 | #define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 | ||
| 134 | #define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 | ||
| 135 | #define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 | ||
| 136 | #define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 | ||
| 137 | #define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 | ||
| 138 | #define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 | ||
| 139 | #define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 | ||
| 140 | #define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 | ||
| 141 | #define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 | ||
| 142 | #define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 | ||
| 143 | #define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 | ||
| 144 | #define GCC_BLSP2_UART1_APPS_CLK 127 | ||
| 145 | #define GCC_BLSP2_UART1_SIM_CLK 128 | ||
| 146 | #define GCC_BLSP2_UART2_APPS_CLK 129 | ||
| 147 | #define GCC_BLSP2_UART2_SIM_CLK 130 | ||
| 148 | #define GCC_BLSP2_UART3_APPS_CLK 131 | ||
| 149 | #define GCC_BLSP2_UART3_SIM_CLK 132 | ||
| 150 | #define GCC_BLSP2_UART4_APPS_CLK 133 | ||
| 151 | #define GCC_BLSP2_UART4_SIM_CLK 134 | ||
| 152 | #define GCC_BLSP2_UART5_APPS_CLK 135 | ||
| 153 | #define GCC_BLSP2_UART5_SIM_CLK 136 | ||
| 154 | #define GCC_BLSP2_UART6_APPS_CLK 137 | ||
| 155 | #define GCC_BLSP2_UART6_SIM_CLK 138 | ||
| 156 | #define GCC_BOOT_ROM_AHB_CLK 139 | ||
| 157 | #define GCC_CE1_AHB_CLK 140 | ||
| 158 | #define GCC_CE1_AXI_CLK 141 | ||
| 159 | #define GCC_CE1_CLK 142 | ||
| 160 | #define GCC_CE2_AHB_CLK 143 | ||
| 161 | #define GCC_CE2_AXI_CLK 144 | ||
| 162 | #define GCC_CE2_CLK 145 | ||
| 163 | #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 | ||
| 164 | #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 | ||
| 165 | #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 | ||
| 166 | #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 | ||
| 167 | #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 | ||
| 168 | #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 | ||
| 169 | #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 | ||
| 170 | #define GCC_CFG_NOC_AHB_CLK 153 | ||
| 171 | #define GCC_CFG_NOC_DDR_CFG_CLK 154 | ||
| 172 | #define GCC_CFG_NOC_RPM_AHB_CLK 155 | ||
| 173 | #define GCC_BIMC_DDR_CPLL0_CLK 156 | ||
| 174 | #define GCC_BIMC_DDR_CPLL1_CLK 157 | ||
| 175 | #define GCC_DDR_DIM_CFG_CLK 158 | ||
| 176 | #define GCC_DDR_DIM_SLEEP_CLK 159 | ||
| 177 | #define GCC_DEHR_CLK 160 | ||
| 178 | #define GCC_AHB_CLK 161 | ||
| 179 | #define GCC_IM_SLEEP_CLK 162 | ||
| 180 | #define GCC_XO_CLK 163 | ||
| 181 | #define GCC_XO_DIV4_CLK 164 | ||
| 182 | #define GCC_GP1_CLK 165 | ||
| 183 | #define GCC_GP2_CLK 166 | ||
| 184 | #define GCC_GP3_CLK 167 | ||
| 185 | #define GCC_IMEM_AXI_CLK 168 | ||
| 186 | #define GCC_IMEM_CFG_AHB_CLK 169 | ||
| 187 | #define GCC_KPSS_AHB_CLK 170 | ||
| 188 | #define GCC_KPSS_AXI_CLK 171 | ||
| 189 | #define GCC_LPASS_Q6_AXI_CLK 172 | ||
| 190 | #define GCC_MMSS_NOC_AT_CLK 173 | ||
| 191 | #define GCC_MMSS_NOC_CFG_AHB_CLK 174 | ||
| 192 | #define GCC_OCMEM_NOC_CFG_AHB_CLK 175 | ||
| 193 | #define GCC_OCMEM_SYS_NOC_AXI_CLK 176 | ||
| 194 | #define GCC_MPM_AHB_CLK 177 | ||
| 195 | #define GCC_MSG_RAM_AHB_CLK 178 | ||
| 196 | #define GCC_MSS_CFG_AHB_CLK 179 | ||
| 197 | #define GCC_MSS_Q6_BIMC_AXI_CLK 180 | ||
| 198 | #define GCC_NOC_CONF_XPU_AHB_CLK 181 | ||
| 199 | #define GCC_PDM2_CLK 182 | ||
| 200 | #define GCC_PDM_AHB_CLK 183 | ||
| 201 | #define GCC_PDM_XO4_CLK 184 | ||
| 202 | #define GCC_PERIPH_NOC_AHB_CLK 185 | ||
| 203 | #define GCC_PERIPH_NOC_AT_CLK 186 | ||
| 204 | #define GCC_PERIPH_NOC_CFG_AHB_CLK 187 | ||
| 205 | #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 | ||
| 206 | #define GCC_PERIPH_XPU_AHB_CLK 189 | ||
| 207 | #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 | ||
| 208 | #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 | ||
| 209 | #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 | ||
| 210 | #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 | ||
| 211 | #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 | ||
| 212 | #define GCC_PRNG_AHB_CLK 195 | ||
| 213 | #define GCC_QDSS_AT_CLK 196 | ||
| 214 | #define GCC_QDSS_CFG_AHB_CLK 197 | ||
| 215 | #define GCC_QDSS_DAP_AHB_CLK 198 | ||
| 216 | #define GCC_QDSS_DAP_CLK 199 | ||
| 217 | #define GCC_QDSS_ETR_USB_CLK 200 | ||
| 218 | #define GCC_QDSS_STM_CLK 201 | ||
| 219 | #define GCC_QDSS_TRACECLKIN_CLK 202 | ||
| 220 | #define GCC_QDSS_TSCTR_DIV16_CLK 203 | ||
| 221 | #define GCC_QDSS_TSCTR_DIV2_CLK 204 | ||
| 222 | #define GCC_QDSS_TSCTR_DIV3_CLK 205 | ||
| 223 | #define GCC_QDSS_TSCTR_DIV4_CLK 206 | ||
| 224 | #define GCC_QDSS_TSCTR_DIV8_CLK 207 | ||
| 225 | #define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 | ||
| 226 | #define GCC_RBCPR_AHB_CLK 209 | ||
| 227 | #define GCC_RBCPR_CLK 210 | ||
| 228 | #define GCC_RPM_BUS_AHB_CLK 211 | ||
| 229 | #define GCC_RPM_PROC_HCLK 212 | ||
| 230 | #define GCC_RPM_SLEEP_CLK 213 | ||
| 231 | #define GCC_RPM_TIMER_CLK 214 | ||
| 232 | #define GCC_SDCC1_AHB_CLK 215 | ||
| 233 | #define GCC_SDCC1_APPS_CLK 216 | ||
| 234 | #define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 | ||
| 235 | #define GCC_SDCC2_AHB_CLK 218 | ||
| 236 | #define GCC_SDCC2_APPS_CLK 219 | ||
| 237 | #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 | ||
| 238 | #define GCC_SDCC3_AHB_CLK 221 | ||
| 239 | #define GCC_SDCC3_APPS_CLK 222 | ||
| 240 | #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 | ||
| 241 | #define GCC_SDCC4_AHB_CLK 224 | ||
| 242 | #define GCC_SDCC4_APPS_CLK 225 | ||
| 243 | #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 | ||
| 244 | #define GCC_SEC_CTRL_ACC_CLK 227 | ||
| 245 | #define GCC_SEC_CTRL_AHB_CLK 228 | ||
| 246 | #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 | ||
| 247 | #define GCC_SEC_CTRL_CLK 230 | ||
| 248 | #define GCC_SEC_CTRL_SENSE_CLK 231 | ||
| 249 | #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 | ||
| 250 | #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 | ||
| 251 | #define GCC_SPDM_BIMC_CY_CLK 234 | ||
| 252 | #define GCC_SPDM_CFG_AHB_CLK 235 | ||
| 253 | #define GCC_SPDM_DEBUG_CY_CLK 236 | ||
| 254 | #define GCC_SPDM_FF_CLK 237 | ||
| 255 | #define GCC_SPDM_MSTR_AHB_CLK 238 | ||
| 256 | #define GCC_SPDM_PNOC_CY_CLK 239 | ||
| 257 | #define GCC_SPDM_RPM_CY_CLK 240 | ||
| 258 | #define GCC_SPDM_SNOC_CY_CLK 241 | ||
| 259 | #define GCC_SPMI_AHB_CLK 242 | ||
| 260 | #define GCC_SPMI_CNOC_AHB_CLK 243 | ||
| 261 | #define GCC_SPMI_SER_CLK 244 | ||
| 262 | #define GCC_SNOC_CNOC_AHB_CLK 245 | ||
| 263 | #define GCC_SNOC_PNOC_AHB_CLK 246 | ||
| 264 | #define GCC_SYS_NOC_AT_CLK 247 | ||
| 265 | #define GCC_SYS_NOC_AXI_CLK 248 | ||
| 266 | #define GCC_SYS_NOC_KPSS_AHB_CLK 249 | ||
| 267 | #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 | ||
| 268 | #define GCC_SYS_NOC_USB3_AXI_CLK 251 | ||
| 269 | #define GCC_TCSR_AHB_CLK 252 | ||
| 270 | #define GCC_TLMM_AHB_CLK 253 | ||
| 271 | #define GCC_TLMM_CLK 254 | ||
| 272 | #define GCC_TSIF_AHB_CLK 255 | ||
| 273 | #define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 | ||
| 274 | #define GCC_TSIF_REF_CLK 257 | ||
| 275 | #define GCC_USB2A_PHY_SLEEP_CLK 258 | ||
| 276 | #define GCC_USB2B_PHY_SLEEP_CLK 259 | ||
| 277 | #define GCC_USB30_MASTER_CLK 260 | ||
| 278 | #define GCC_USB30_MOCK_UTMI_CLK 261 | ||
| 279 | #define GCC_USB30_SLEEP_CLK 262 | ||
| 280 | #define GCC_USB_HS_AHB_CLK 263 | ||
| 281 | #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 | ||
| 282 | #define GCC_USB_HS_SYSTEM_CLK 265 | ||
| 283 | #define GCC_USB_HSIC_AHB_CLK 266 | ||
| 284 | #define GCC_USB_HSIC_CLK 267 | ||
| 285 | #define GCC_USB_HSIC_IO_CAL_CLK 268 | ||
| 286 | #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 | ||
| 287 | #define GCC_USB_HSIC_SYSTEM_CLK 270 | ||
| 288 | #define GCC_WCSS_GPLL1_CLK_SRC 271 | ||
| 289 | #define GCC_MMSS_GPLL0_CLK_SRC 272 | ||
| 290 | #define GCC_LPASS_GPLL0_CLK_SRC 273 | ||
| 291 | #define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 | ||
| 292 | #define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 | ||
| 293 | #define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 | ||
| 294 | #define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 | ||
| 295 | #define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 | ||
| 296 | #define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 | ||
| 297 | #define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 | ||
| 298 | #define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 | ||
| 299 | #define GCC_MPM_AHB_CLK_SLEEP_ENA 282 | ||
| 300 | #define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 | ||
| 301 | #define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 | ||
| 302 | #define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 | ||
| 303 | #define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 | ||
| 304 | #define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 | ||
| 305 | #define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 | ||
| 306 | #define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 | ||
| 307 | #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 | ||
| 308 | #define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 | ||
| 309 | #define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 | ||
| 310 | #define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 | ||
| 311 | #define GCC_TLMM_CLK_SLEEP_ENA 294 | ||
| 312 | #define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 | ||
| 313 | #define GCC_CE1_CLK_SLEEP_ENA 296 | ||
| 314 | #define GCC_CE1_AXI_CLK_SLEEP_ENA 297 | ||
| 315 | #define GCC_CE1_AHB_CLK_SLEEP_ENA 298 | ||
| 316 | #define GCC_CE2_CLK_SLEEP_ENA 299 | ||
| 317 | #define GCC_CE2_AXI_CLK_SLEEP_ENA 300 | ||
| 318 | #define GCC_CE2_AHB_CLK_SLEEP_ENA 301 | ||
| 319 | |||
| 320 | #endif | ||
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h new file mode 100644 index 000000000000..5868ef14a777 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H | ||
| 15 | #define _DT_BINDINGS_CLK_MSM_MMCC_8960_H | ||
| 16 | |||
| 17 | #define MMSS_AHB_SRC 0 | ||
| 18 | #define FAB_AHB_CLK 1 | ||
| 19 | #define APU_AHB_CLK 2 | ||
| 20 | #define TV_ENC_AHB_CLK 3 | ||
| 21 | #define AMP_AHB_CLK 4 | ||
| 22 | #define DSI2_S_AHB_CLK 5 | ||
| 23 | #define JPEGD_AHB_CLK 6 | ||
| 24 | #define GFX2D0_AHB_CLK 7 | ||
| 25 | #define DSI_S_AHB_CLK 8 | ||
| 26 | #define DSI2_M_AHB_CLK 9 | ||
| 27 | #define VPE_AHB_CLK 10 | ||
| 28 | #define SMMU_AHB_CLK 11 | ||
| 29 | #define HDMI_M_AHB_CLK 12 | ||
| 30 | #define VFE_AHB_CLK 13 | ||
| 31 | #define ROT_AHB_CLK 14 | ||
| 32 | #define VCODEC_AHB_CLK 15 | ||
| 33 | #define MDP_AHB_CLK 16 | ||
| 34 | #define DSI_M_AHB_CLK 17 | ||
| 35 | #define CSI_AHB_CLK 18 | ||
| 36 | #define MMSS_IMEM_AHB_CLK 19 | ||
| 37 | #define IJPEG_AHB_CLK 20 | ||
| 38 | #define HDMI_S_AHB_CLK 21 | ||
| 39 | #define GFX3D_AHB_CLK 22 | ||
| 40 | #define GFX2D1_AHB_CLK 23 | ||
| 41 | #define MMSS_FPB_CLK 24 | ||
| 42 | #define MMSS_AXI_SRC 25 | ||
| 43 | #define MMSS_FAB_CORE 26 | ||
| 44 | #define FAB_MSP_AXI_CLK 27 | ||
| 45 | #define JPEGD_AXI_CLK 28 | ||
| 46 | #define GMEM_AXI_CLK 29 | ||
| 47 | #define MDP_AXI_CLK 30 | ||
| 48 | #define MMSS_IMEM_AXI_CLK 31 | ||
| 49 | #define IJPEG_AXI_CLK 32 | ||
| 50 | #define GFX3D_AXI_CLK 33 | ||
| 51 | #define VCODEC_AXI_CLK 34 | ||
| 52 | #define VFE_AXI_CLK 35 | ||
| 53 | #define VPE_AXI_CLK 36 | ||
| 54 | #define ROT_AXI_CLK 37 | ||
| 55 | #define VCODEC_AXI_A_CLK 38 | ||
| 56 | #define VCODEC_AXI_B_CLK 39 | ||
| 57 | #define MM_AXI_S3_FCLK 40 | ||
| 58 | #define MM_AXI_S2_FCLK 41 | ||
| 59 | #define MM_AXI_S1_FCLK 42 | ||
| 60 | #define MM_AXI_S0_FCLK 43 | ||
| 61 | #define MM_AXI_S2_CLK 44 | ||
| 62 | #define MM_AXI_S1_CLK 45 | ||
| 63 | #define MM_AXI_S0_CLK 46 | ||
| 64 | #define CSI0_SRC 47 | ||
| 65 | #define CSI0_CLK 48 | ||
| 66 | #define CSI0_PHY_CLK 49 | ||
| 67 | #define CSI1_SRC 50 | ||
| 68 | #define CSI1_CLK 51 | ||
| 69 | #define CSI1_PHY_CLK 52 | ||
| 70 | #define CSI2_SRC 53 | ||
| 71 | #define CSI2_CLK 54 | ||
| 72 | #define CSI2_PHY_CLK 55 | ||
| 73 | #define DSI_SRC 56 | ||
| 74 | #define DSI_CLK 57 | ||
| 75 | #define CSI_PIX_CLK 58 | ||
| 76 | #define CSI_RDI_CLK 59 | ||
| 77 | #define MDP_VSYNC_CLK 60 | ||
| 78 | #define HDMI_DIV_CLK 61 | ||
| 79 | #define HDMI_APP_CLK 62 | ||
| 80 | #define CSI_PIX1_CLK 63 | ||
| 81 | #define CSI_RDI2_CLK 64 | ||
| 82 | #define CSI_RDI1_CLK 65 | ||
| 83 | #define GFX2D0_SRC 66 | ||
| 84 | #define GFX2D0_CLK 67 | ||
| 85 | #define GFX2D1_SRC 68 | ||
| 86 | #define GFX2D1_CLK 69 | ||
| 87 | #define GFX3D_SRC 70 | ||
| 88 | #define GFX3D_CLK 71 | ||
| 89 | #define IJPEG_SRC 72 | ||
| 90 | #define IJPEG_CLK 73 | ||
| 91 | #define JPEGD_SRC 74 | ||
| 92 | #define JPEGD_CLK 75 | ||
| 93 | #define MDP_SRC 76 | ||
| 94 | #define MDP_CLK 77 | ||
| 95 | #define MDP_LUT_CLK 78 | ||
| 96 | #define DSI2_PIXEL_SRC 79 | ||
| 97 | #define DSI2_PIXEL_CLK 80 | ||
| 98 | #define DSI2_SRC 81 | ||
| 99 | #define DSI2_CLK 82 | ||
| 100 | #define DSI1_BYTE_SRC 83 | ||
| 101 | #define DSI1_BYTE_CLK 84 | ||
| 102 | #define DSI2_BYTE_SRC 85 | ||
| 103 | #define DSI2_BYTE_CLK 86 | ||
| 104 | #define DSI1_ESC_SRC 87 | ||
| 105 | #define DSI1_ESC_CLK 88 | ||
| 106 | #define DSI2_ESC_SRC 89 | ||
| 107 | #define DSI2_ESC_CLK 90 | ||
| 108 | #define ROT_SRC 91 | ||
| 109 | #define ROT_CLK 92 | ||
| 110 | #define TV_ENC_CLK 93 | ||
| 111 | #define TV_DAC_CLK 94 | ||
| 112 | #define HDMI_TV_CLK 95 | ||
| 113 | #define MDP_TV_CLK 96 | ||
| 114 | #define TV_SRC 97 | ||
| 115 | #define VCODEC_SRC 98 | ||
| 116 | #define VCODEC_CLK 99 | ||
| 117 | #define VFE_SRC 100 | ||
| 118 | #define VFE_CLK 101 | ||
| 119 | #define VFE_CSI_CLK 102 | ||
| 120 | #define VPE_SRC 103 | ||
| 121 | #define VPE_CLK 104 | ||
| 122 | #define DSI_PIXEL_SRC 105 | ||
| 123 | #define DSI_PIXEL_CLK 106 | ||
| 124 | #define CAMCLK0_SRC 107 | ||
| 125 | #define CAMCLK0_CLK 108 | ||
| 126 | #define CAMCLK1_SRC 109 | ||
| 127 | #define CAMCLK1_CLK 110 | ||
| 128 | #define CAMCLK2_SRC 111 | ||
| 129 | #define CAMCLK2_CLK 112 | ||
| 130 | #define CSIPHYTIMER_SRC 113 | ||
| 131 | #define CSIPHY2_TIMER_CLK 114 | ||
| 132 | #define CSIPHY1_TIMER_CLK 115 | ||
| 133 | #define CSIPHY0_TIMER_CLK 116 | ||
| 134 | #define PLL1 117 | ||
| 135 | #define PLL2 118 | ||
| 136 | |||
| 137 | #endif | ||
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h new file mode 100644 index 000000000000..04d318d1187a --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h | |||
| @@ -0,0 +1,161 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H | ||
| 15 | #define _DT_BINDINGS_CLK_MSM_MMCC_8974_H | ||
| 16 | |||
| 17 | #define MMSS_AHB_CLK_SRC 0 | ||
| 18 | #define MMSS_AXI_CLK_SRC 1 | ||
| 19 | #define MMPLL0 2 | ||
| 20 | #define MMPLL0_VOTE 3 | ||
| 21 | #define MMPLL1 4 | ||
| 22 | #define MMPLL1_VOTE 5 | ||
| 23 | #define MMPLL2 6 | ||
| 24 | #define MMPLL3 7 | ||
| 25 | #define CSI0_CLK_SRC 8 | ||
| 26 | #define CSI1_CLK_SRC 9 | ||
| 27 | #define CSI2_CLK_SRC 10 | ||
| 28 | #define CSI3_CLK_SRC 11 | ||
| 29 | #define VFE0_CLK_SRC 12 | ||
| 30 | #define VFE1_CLK_SRC 13 | ||
| 31 | #define MDP_CLK_SRC 14 | ||
| 32 | #define GFX3D_CLK_SRC 15 | ||
| 33 | #define JPEG0_CLK_SRC 16 | ||
| 34 | #define JPEG1_CLK_SRC 17 | ||
| 35 | #define JPEG2_CLK_SRC 18 | ||
| 36 | #define PCLK0_CLK_SRC 19 | ||
| 37 | #define PCLK1_CLK_SRC 20 | ||
| 38 | #define VCODEC0_CLK_SRC 21 | ||
| 39 | #define CCI_CLK_SRC 22 | ||
| 40 | #define CAMSS_GP0_CLK_SRC 23 | ||
| 41 | #define CAMSS_GP1_CLK_SRC 24 | ||
| 42 | #define MCLK0_CLK_SRC 25 | ||
| 43 | #define MCLK1_CLK_SRC 26 | ||
| 44 | #define MCLK2_CLK_SRC 27 | ||
| 45 | #define MCLK3_CLK_SRC 28 | ||
| 46 | #define CSI0PHYTIMER_CLK_SRC 29 | ||
| 47 | #define CSI1PHYTIMER_CLK_SRC 30 | ||
| 48 | #define CSI2PHYTIMER_CLK_SRC 31 | ||
| 49 | #define CPP_CLK_SRC 32 | ||
| 50 | #define BYTE0_CLK_SRC 33 | ||
| 51 | #define BYTE1_CLK_SRC 34 | ||
| 52 | #define EDPAUX_CLK_SRC 35 | ||
| 53 | #define EDPLINK_CLK_SRC 36 | ||
| 54 | #define EDPPIXEL_CLK_SRC 37 | ||
| 55 | #define ESC0_CLK_SRC 38 | ||
| 56 | #define ESC1_CLK_SRC 39 | ||
| 57 | #define EXTPCLK_CLK_SRC 40 | ||
| 58 | #define HDMI_CLK_SRC 41 | ||
| 59 | #define VSYNC_CLK_SRC 42 | ||
| 60 | #define RBCPR_CLK_SRC 43 | ||
| 61 | #define CAMSS_CCI_CCI_AHB_CLK 44 | ||
| 62 | #define CAMSS_CCI_CCI_CLK 45 | ||
| 63 | #define CAMSS_CSI0_AHB_CLK 46 | ||
| 64 | #define CAMSS_CSI0_CLK 47 | ||
| 65 | #define CAMSS_CSI0PHY_CLK 48 | ||
| 66 | #define CAMSS_CSI0PIX_CLK 49 | ||
| 67 | #define CAMSS_CSI0RDI_CLK 50 | ||
| 68 | #define CAMSS_CSI1_AHB_CLK 51 | ||
| 69 | #define CAMSS_CSI1_CLK 52 | ||
| 70 | #define CAMSS_CSI1PHY_CLK 53 | ||
| 71 | #define CAMSS_CSI1PIX_CLK 54 | ||
| 72 | #define CAMSS_CSI1RDI_CLK 55 | ||
| 73 | #define CAMSS_CSI2_AHB_CLK 56 | ||
| 74 | #define CAMSS_CSI2_CLK 57 | ||
| 75 | #define CAMSS_CSI2PHY_CLK 58 | ||
| 76 | #define CAMSS_CSI2PIX_CLK 59 | ||
| 77 | #define CAMSS_CSI2RDI_CLK 60 | ||
| 78 | #define CAMSS_CSI3_AHB_CLK 61 | ||
| 79 | #define CAMSS_CSI3_CLK 62 | ||
| 80 | #define CAMSS_CSI3PHY_CLK 63 | ||
| 81 | #define CAMSS_CSI3PIX_CLK 64 | ||
| 82 | #define CAMSS_CSI3RDI_CLK 65 | ||
| 83 | #define CAMSS_CSI_VFE0_CLK 66 | ||
| 84 | #define CAMSS_CSI_VFE1_CLK 67 | ||
| 85 | #define CAMSS_GP0_CLK 68 | ||
| 86 | #define CAMSS_GP1_CLK 69 | ||
| 87 | #define CAMSS_ISPIF_AHB_CLK 70 | ||
| 88 | #define CAMSS_JPEG_JPEG0_CLK 71 | ||
| 89 | #define CAMSS_JPEG_JPEG1_CLK 72 | ||
| 90 | #define CAMSS_JPEG_JPEG2_CLK 73 | ||
| 91 | #define CAMSS_JPEG_JPEG_AHB_CLK 74 | ||
| 92 | #define CAMSS_JPEG_JPEG_AXI_CLK 75 | ||
| 93 | #define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76 | ||
| 94 | #define CAMSS_MCLK0_CLK 77 | ||
| 95 | #define CAMSS_MCLK1_CLK 78 | ||
| 96 | #define CAMSS_MCLK2_CLK 79 | ||
| 97 | #define CAMSS_MCLK3_CLK 80 | ||
| 98 | #define CAMSS_MICRO_AHB_CLK 81 | ||
| 99 | #define CAMSS_PHY0_CSI0PHYTIMER_CLK 82 | ||
| 100 | #define CAMSS_PHY1_CSI1PHYTIMER_CLK 83 | ||
| 101 | #define CAMSS_PHY2_CSI2PHYTIMER_CLK 84 | ||
| 102 | #define CAMSS_TOP_AHB_CLK 85 | ||
| 103 | #define CAMSS_VFE_CPP_AHB_CLK 86 | ||
| 104 | #define CAMSS_VFE_CPP_CLK 87 | ||
| 105 | #define CAMSS_VFE_VFE0_CLK 88 | ||
| 106 | #define CAMSS_VFE_VFE1_CLK 89 | ||
| 107 | #define CAMSS_VFE_VFE_AHB_CLK 90 | ||
| 108 | #define CAMSS_VFE_VFE_AXI_CLK 91 | ||
| 109 | #define CAMSS_VFE_VFE_OCMEMNOC_CLK 92 | ||
| 110 | #define MDSS_AHB_CLK 93 | ||
| 111 | #define MDSS_AXI_CLK 94 | ||
| 112 | #define MDSS_BYTE0_CLK 95 | ||
| 113 | #define MDSS_BYTE1_CLK 96 | ||
| 114 | #define MDSS_EDPAUX_CLK 97 | ||
| 115 | #define MDSS_EDPLINK_CLK 98 | ||
| 116 | #define MDSS_EDPPIXEL_CLK 99 | ||
| 117 | #define MDSS_ESC0_CLK 100 | ||
| 118 | #define MDSS_ESC1_CLK 101 | ||
| 119 | #define MDSS_EXTPCLK_CLK 102 | ||
| 120 | #define MDSS_HDMI_AHB_CLK 103 | ||
| 121 | #define MDSS_HDMI_CLK 104 | ||
| 122 | #define MDSS_MDP_CLK 105 | ||
| 123 | #define MDSS_MDP_LUT_CLK 106 | ||
| 124 | #define MDSS_PCLK0_CLK 107 | ||
| 125 | #define MDSS_PCLK1_CLK 108 | ||
| 126 | #define MDSS_VSYNC_CLK 109 | ||
| 127 | #define MMSS_MISC_AHB_CLK 110 | ||
| 128 | #define MMSS_MMSSNOC_AHB_CLK 111 | ||
| 129 | #define MMSS_MMSSNOC_BTO_AHB_CLK 112 | ||
| 130 | #define MMSS_MMSSNOC_AXI_CLK 113 | ||
| 131 | #define MMSS_S0_AXI_CLK 114 | ||
| 132 | #define OCMEMCX_AHB_CLK 115 | ||
| 133 | #define OCMEMCX_OCMEMNOC_CLK 116 | ||
| 134 | #define OXILI_OCMEMGX_CLK 117 | ||
| 135 | #define OCMEMNOC_CLK 118 | ||
| 136 | #define OXILI_GFX3D_CLK 119 | ||
| 137 | #define OXILICX_AHB_CLK 120 | ||
| 138 | #define OXILICX_AXI_CLK 121 | ||
| 139 | #define VENUS0_AHB_CLK 122 | ||
| 140 | #define VENUS0_AXI_CLK 123 | ||
| 141 | #define VENUS0_OCMEMNOC_CLK 124 | ||
| 142 | #define VENUS0_VCODEC0_CLK 125 | ||
| 143 | #define OCMEMNOC_CLK_SRC 126 | ||
| 144 | #define SPDM_JPEG0 127 | ||
| 145 | #define SPDM_JPEG1 128 | ||
| 146 | #define SPDM_MDP 129 | ||
| 147 | #define SPDM_AXI 130 | ||
| 148 | #define SPDM_VCODEC0 131 | ||
| 149 | #define SPDM_VFE0 132 | ||
| 150 | #define SPDM_VFE1 133 | ||
| 151 | #define SPDM_JPEG2 134 | ||
| 152 | #define SPDM_PCLK1 135 | ||
| 153 | #define SPDM_GFX3D 136 | ||
| 154 | #define SPDM_AHB 137 | ||
| 155 | #define SPDM_PCLK0 138 | ||
| 156 | #define SPDM_OCMEMNOC 139 | ||
| 157 | #define SPDM_CSI0 140 | ||
| 158 | #define SPDM_RM_AXI 141 | ||
| 159 | #define SPDM_RM_OCMEMNOC 142 | ||
| 160 | |||
| 161 | #endif | ||
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h new file mode 100644 index 000000000000..859e9be511d9 --- /dev/null +++ b/include/dt-bindings/clock/r8a7790-clock.h | |||
| @@ -0,0 +1,107 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Ideas On Board SPRL | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ | ||
| 11 | #define __DT_BINDINGS_CLOCK_R8A7790_H__ | ||
| 12 | |||
| 13 | /* CPG */ | ||
| 14 | #define R8A7790_CLK_MAIN 0 | ||
| 15 | #define R8A7790_CLK_PLL0 1 | ||
| 16 | #define R8A7790_CLK_PLL1 2 | ||
| 17 | #define R8A7790_CLK_PLL3 3 | ||
| 18 | #define R8A7790_CLK_LB 4 | ||
| 19 | #define R8A7790_CLK_QSPI 5 | ||
| 20 | #define R8A7790_CLK_SDH 6 | ||
| 21 | #define R8A7790_CLK_SD0 7 | ||
| 22 | #define R8A7790_CLK_SD1 8 | ||
| 23 | #define R8A7790_CLK_Z 9 | ||
| 24 | |||
| 25 | /* MSTP0 */ | ||
| 26 | #define R8A7790_CLK_MSIOF0 0 | ||
| 27 | |||
| 28 | /* MSTP1 */ | ||
| 29 | #define R8A7790_CLK_TMU1 11 | ||
| 30 | #define R8A7790_CLK_TMU3 21 | ||
| 31 | #define R8A7790_CLK_TMU2 22 | ||
| 32 | #define R8A7790_CLK_CMT0 24 | ||
| 33 | #define R8A7790_CLK_TMU0 25 | ||
| 34 | #define R8A7790_CLK_VSP1_DU1 27 | ||
| 35 | #define R8A7790_CLK_VSP1_DU0 28 | ||
| 36 | #define R8A7790_CLK_VSP1_RT 30 | ||
| 37 | #define R8A7790_CLK_VSP1_SY 31 | ||
| 38 | |||
| 39 | /* MSTP2 */ | ||
| 40 | #define R8A7790_CLK_SCIFA2 2 | ||
| 41 | #define R8A7790_CLK_SCIFA1 3 | ||
| 42 | #define R8A7790_CLK_SCIFA0 4 | ||
| 43 | #define R8A7790_CLK_MSIOF2 5 | ||
| 44 | #define R8A7790_CLK_SCIFB0 6 | ||
| 45 | #define R8A7790_CLK_SCIFB1 7 | ||
| 46 | #define R8A7790_CLK_MSIOF1 8 | ||
| 47 | #define R8A7790_CLK_MSIOF3 15 | ||
| 48 | #define R8A7790_CLK_SCIFB2 16 | ||
| 49 | #define R8A7790_CLK_SYS_DMAC0 18 | ||
| 50 | #define R8A7790_CLK_SYS_DMAC1 19 | ||
| 51 | |||
| 52 | /* MSTP3 */ | ||
| 53 | #define R8A7790_CLK_TPU0 4 | ||
| 54 | #define R8A7790_CLK_MMCIF1 5 | ||
| 55 | #define R8A7790_CLK_SDHI3 11 | ||
| 56 | #define R8A7790_CLK_SDHI2 12 | ||
| 57 | #define R8A7790_CLK_SDHI1 13 | ||
| 58 | #define R8A7790_CLK_SDHI0 14 | ||
| 59 | #define R8A7790_CLK_MMCIF0 15 | ||
| 60 | #define R8A7790_CLK_SSUSB 28 | ||
| 61 | #define R8A7790_CLK_CMT1 29 | ||
| 62 | #define R8A7790_CLK_USBDMAC0 30 | ||
| 63 | #define R8A7790_CLK_USBDMAC1 31 | ||
| 64 | |||
| 65 | /* MSTP5 */ | ||
| 66 | #define R8A7790_CLK_THERMAL 22 | ||
| 67 | #define R8A7790_CLK_PWM 23 | ||
| 68 | |||
| 69 | /* MSTP7 */ | ||
| 70 | #define R8A7790_CLK_EHCI 3 | ||
| 71 | #define R8A7790_CLK_HSUSB 4 | ||
| 72 | #define R8A7790_CLK_HSCIF1 16 | ||
| 73 | #define R8A7790_CLK_HSCIF0 17 | ||
| 74 | #define R8A7790_CLK_SCIF1 20 | ||
| 75 | #define R8A7790_CLK_SCIF0 21 | ||
| 76 | #define R8A7790_CLK_DU2 22 | ||
| 77 | #define R8A7790_CLK_DU1 23 | ||
| 78 | #define R8A7790_CLK_DU0 24 | ||
| 79 | #define R8A7790_CLK_LVDS1 25 | ||
| 80 | #define R8A7790_CLK_LVDS0 26 | ||
| 81 | |||
| 82 | /* MSTP8 */ | ||
| 83 | #define R8A7790_CLK_VIN3 8 | ||
| 84 | #define R8A7790_CLK_VIN2 9 | ||
| 85 | #define R8A7790_CLK_VIN1 10 | ||
| 86 | #define R8A7790_CLK_VIN0 11 | ||
| 87 | #define R8A7790_CLK_ETHER 13 | ||
| 88 | #define R8A7790_CLK_SATA1 14 | ||
| 89 | #define R8A7790_CLK_SATA0 15 | ||
| 90 | |||
| 91 | /* MSTP9 */ | ||
| 92 | #define R8A7790_CLK_GPIO5 7 | ||
| 93 | #define R8A7790_CLK_GPIO4 8 | ||
| 94 | #define R8A7790_CLK_GPIO3 9 | ||
| 95 | #define R8A7790_CLK_GPIO2 10 | ||
| 96 | #define R8A7790_CLK_GPIO1 11 | ||
| 97 | #define R8A7790_CLK_GPIO0 12 | ||
| 98 | #define R8A7790_CLK_RCAN1 15 | ||
| 99 | #define R8A7790_CLK_RCAN0 16 | ||
| 100 | #define R8A7790_CLK_QSPI_MOD 17 | ||
| 101 | #define R8A7790_CLK_IICDVFS 26 | ||
| 102 | #define R8A7790_CLK_I2C3 28 | ||
| 103 | #define R8A7790_CLK_I2C2 29 | ||
| 104 | #define R8A7790_CLK_I2C1 30 | ||
| 105 | #define R8A7790_CLK_I2C0 31 | ||
| 106 | |||
| 107 | #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ | ||
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h new file mode 100644 index 000000000000..30f82f286e29 --- /dev/null +++ b/include/dt-bindings/clock/r8a7791-clock.h | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2013 Ideas On Board SPRL | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ | ||
| 11 | #define __DT_BINDINGS_CLOCK_R8A7791_H__ | ||
| 12 | |||
| 13 | /* CPG */ | ||
| 14 | #define R8A7791_CLK_MAIN 0 | ||
| 15 | #define R8A7791_CLK_PLL0 1 | ||
| 16 | #define R8A7791_CLK_PLL1 2 | ||
| 17 | #define R8A7791_CLK_PLL3 3 | ||
| 18 | #define R8A7791_CLK_LB 4 | ||
| 19 | #define R8A7791_CLK_QSPI 5 | ||
| 20 | #define R8A7791_CLK_SDH 6 | ||
| 21 | #define R8A7791_CLK_SD0 7 | ||
| 22 | #define R8A7791_CLK_Z 8 | ||
| 23 | |||
| 24 | /* MSTP0 */ | ||
| 25 | #define R8A7791_CLK_MSIOF0 0 | ||
| 26 | |||
| 27 | /* MSTP1 */ | ||
| 28 | #define R8A7791_CLK_TMU1 11 | ||
| 29 | #define R8A7791_CLK_TMU3 21 | ||
| 30 | #define R8A7791_CLK_TMU2 22 | ||
| 31 | #define R8A7791_CLK_CMT0 24 | ||
| 32 | #define R8A7791_CLK_TMU0 25 | ||
| 33 | #define R8A7791_CLK_VSP1_DU1 27 | ||
| 34 | #define R8A7791_CLK_VSP1_DU0 28 | ||
| 35 | #define R8A7791_CLK_VSP1_SY 31 | ||
| 36 | |||
| 37 | /* MSTP2 */ | ||
| 38 | #define R8A7791_CLK_SCIFA2 2 | ||
| 39 | #define R8A7791_CLK_SCIFA1 3 | ||
| 40 | #define R8A7791_CLK_SCIFA0 4 | ||
| 41 | #define R8A7791_CLK_MSIOF2 5 | ||
| 42 | #define R8A7791_CLK_SCIFB0 6 | ||
| 43 | #define R8A7791_CLK_SCIFB1 7 | ||
| 44 | #define R8A7791_CLK_MSIOF1 8 | ||
| 45 | #define R8A7791_CLK_SCIFB2 16 | ||
| 46 | #define R8A7791_CLK_DMAC 18 | ||
| 47 | |||
| 48 | /* MSTP3 */ | ||
| 49 | #define R8A7791_CLK_TPU0 4 | ||
| 50 | #define R8A7791_CLK_SDHI2 11 | ||
| 51 | #define R8A7791_CLK_SDHI1 12 | ||
| 52 | #define R8A7791_CLK_SDHI0 14 | ||
| 53 | #define R8A7791_CLK_MMCIF0 15 | ||
| 54 | #define R8A7791_CLK_SSUSB 28 | ||
| 55 | #define R8A7791_CLK_CMT1 29 | ||
| 56 | #define R8A7791_CLK_USBDMAC0 30 | ||
| 57 | #define R8A7791_CLK_USBDMAC1 31 | ||
| 58 | |||
| 59 | /* MSTP5 */ | ||
| 60 | #define R8A7791_CLK_THERMAL 22 | ||
| 61 | #define R8A7791_CLK_PWM 23 | ||
| 62 | |||
| 63 | /* MSTP7 */ | ||
| 64 | #define R8A7791_CLK_HSUSB 4 | ||
| 65 | #define R8A7791_CLK_HSCIF2 13 | ||
| 66 | #define R8A7791_CLK_SCIF5 14 | ||
| 67 | #define R8A7791_CLK_SCIF4 15 | ||
| 68 | #define R8A7791_CLK_HSCIF1 16 | ||
| 69 | #define R8A7791_CLK_HSCIF0 17 | ||
| 70 | #define R8A7791_CLK_SCIF3 18 | ||
| 71 | #define R8A7791_CLK_SCIF2 19 | ||
| 72 | #define R8A7791_CLK_SCIF1 20 | ||
| 73 | #define R8A7791_CLK_SCIF0 21 | ||
| 74 | #define R8A7791_CLK_DU1 23 | ||
| 75 | #define R8A7791_CLK_DU0 24 | ||
| 76 | #define R8A7791_CLK_LVDS0 26 | ||
| 77 | |||
| 78 | /* MSTP8 */ | ||
| 79 | #define R8A7791_CLK_VIN2 9 | ||
| 80 | #define R8A7791_CLK_VIN1 10 | ||
| 81 | #define R8A7791_CLK_VIN0 11 | ||
| 82 | #define R8A7791_CLK_ETHER 13 | ||
| 83 | #define R8A7791_CLK_SATA1 14 | ||
| 84 | #define R8A7791_CLK_SATA0 15 | ||
| 85 | |||
| 86 | /* MSTP9 */ | ||
| 87 | #define R8A7791_CLK_GPIO7 4 | ||
| 88 | #define R8A7791_CLK_GPIO6 5 | ||
| 89 | #define R8A7791_CLK_GPIO5 7 | ||
| 90 | #define R8A7791_CLK_GPIO4 8 | ||
| 91 | #define R8A7791_CLK_GPIO3 9 | ||
| 92 | #define R8A7791_CLK_GPIO2 10 | ||
| 93 | #define R8A7791_CLK_GPIO1 11 | ||
| 94 | #define R8A7791_CLK_GPIO0 12 | ||
| 95 | #define R8A7791_CLK_RCAN1 15 | ||
| 96 | #define R8A7791_CLK_RCAN0 16 | ||
| 97 | #define R8A7791_CLK_QSPI_MOD 17 | ||
| 98 | #define R8A7791_CLK_I2C5 25 | ||
| 99 | #define R8A7791_CLK_IICDVFS 26 | ||
| 100 | #define R8A7791_CLK_I2C4 27 | ||
| 101 | #define R8A7791_CLK_I2C3 28 | ||
| 102 | #define R8A7791_CLK_I2C2 29 | ||
| 103 | #define R8A7791_CLK_I2C1 30 | ||
| 104 | #define R8A7791_CLK_I2C0 31 | ||
| 105 | |||
| 106 | /* MSTP11 */ | ||
| 107 | #define R8A7791_CLK_SCIFA3 6 | ||
| 108 | #define R8A7791_CLK_SCIFA4 7 | ||
| 109 | #define R8A7791_CLK_SCIFA5 8 | ||
| 110 | |||
| 111 | #endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */ | ||
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index 614aec417902..6d0d8d8ef31e 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h | |||
| @@ -37,10 +37,10 @@ | |||
| 37 | #define TEGRA114_CLK_I2S2 18 | 37 | #define TEGRA114_CLK_I2S2 18 |
| 38 | #define TEGRA114_CLK_EPP 19 | 38 | #define TEGRA114_CLK_EPP 19 |
| 39 | /* 20 (register bit affects vi and vi_sensor) */ | 39 | /* 20 (register bit affects vi and vi_sensor) */ |
| 40 | #define TEGRA114_CLK_GR_2D 21 | 40 | #define TEGRA114_CLK_GR2D 21 |
| 41 | #define TEGRA114_CLK_USBD 22 | 41 | #define TEGRA114_CLK_USBD 22 |
| 42 | #define TEGRA114_CLK_ISP 23 | 42 | #define TEGRA114_CLK_ISP 23 |
| 43 | #define TEGRA114_CLK_GR_3D 24 | 43 | #define TEGRA114_CLK_GR3D 24 |
| 44 | /* 25 */ | 44 | /* 25 */ |
| 45 | #define TEGRA114_CLK_DISP2 26 | 45 | #define TEGRA114_CLK_DISP2 26 |
| 46 | #define TEGRA114_CLK_DISP1 27 | 46 | #define TEGRA114_CLK_DISP1 27 |
| @@ -289,8 +289,8 @@ | |||
| 289 | #define TEGRA114_CLK_PCLK 261 | 289 | #define TEGRA114_CLK_PCLK 261 |
| 290 | #define TEGRA114_CLK_CCLK_G 262 | 290 | #define TEGRA114_CLK_CCLK_G 262 |
| 291 | #define TEGRA114_CLK_CCLK_LP 263 | 291 | #define TEGRA114_CLK_CCLK_LP 263 |
| 292 | /* 264 */ | 292 | #define TEGRA114_CLK_DFLL_REF 264 |
| 293 | /* 265 */ | 293 | #define TEGRA114_CLK_DFLL_SOC 265 |
| 294 | /* 266 */ | 294 | /* 266 */ |
| 295 | /* 267 */ | 295 | /* 267 */ |
| 296 | /* 268 */ | 296 | /* 268 */ |
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h new file mode 100644 index 000000000000..a1116a3b54ef --- /dev/null +++ b/include/dt-bindings/clock/tegra124-car.h | |||
| @@ -0,0 +1,341 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for binding nvidia,tegra124-car. | ||
| 3 | * | ||
| 4 | * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB | ||
| 5 | * registers. These IDs often match those in the CAR's RST_DEVICES registers, | ||
| 6 | * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In | ||
| 7 | * this case, those clocks are assigned IDs above 185 in order to highlight | ||
| 8 | * this issue. Implementations that interpret these clock IDs as bit values | ||
| 9 | * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to | ||
| 10 | * explicitly handle these special cases. | ||
| 11 | * | ||
| 12 | * The balance of the clocks controlled by the CAR are assigned IDs of 185 and | ||
| 13 | * above. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H | ||
| 17 | #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H | ||
| 18 | |||
| 19 | /* 0 */ | ||
| 20 | /* 1 */ | ||
| 21 | /* 2 */ | ||
| 22 | #define TEGRA124_CLK_ISPB 3 | ||
| 23 | #define TEGRA124_CLK_RTC 4 | ||
| 24 | #define TEGRA124_CLK_TIMER 5 | ||
| 25 | #define TEGRA124_CLK_UARTA 6 | ||
| 26 | /* 7 (register bit affects uartb and vfir) */ | ||
| 27 | /* 8 */ | ||
| 28 | #define TEGRA124_CLK_SDMMC2 9 | ||
| 29 | /* 10 (register bit affects spdif_in and spdif_out) */ | ||
| 30 | #define TEGRA124_CLK_I2S1 11 | ||
| 31 | #define TEGRA124_CLK_I2C1 12 | ||
| 32 | #define TEGRA124_CLK_NDFLASH 13 | ||
| 33 | #define TEGRA124_CLK_SDMMC1 14 | ||
| 34 | #define TEGRA124_CLK_SDMMC4 15 | ||
| 35 | /* 16 */ | ||
| 36 | #define TEGRA124_CLK_PWM 17 | ||
| 37 | #define TEGRA124_CLK_I2S2 18 | ||
| 38 | /* 20 (register bit affects vi and vi_sensor) */ | ||
| 39 | #define TEGRA124_CLK_GR_2D 21 | ||
| 40 | #define TEGRA124_CLK_USBD 22 | ||
| 41 | #define TEGRA124_CLK_ISP 23 | ||
| 42 | #define TEGRA124_CLK_GR_3D 24 | ||
| 43 | /* 25 */ | ||
| 44 | #define TEGRA124_CLK_DISP2 26 | ||
| 45 | #define TEGRA124_CLK_DISP1 27 | ||
| 46 | #define TEGRA124_CLK_HOST1X 28 | ||
| 47 | #define TEGRA124_CLK_VCP 29 | ||
| 48 | #define TEGRA124_CLK_I2S0 30 | ||
| 49 | /* 31 */ | ||
| 50 | |||
| 51 | /* 32 */ | ||
| 52 | /* 33 */ | ||
| 53 | #define TEGRA124_CLK_APBDMA 34 | ||
| 54 | /* 35 */ | ||
| 55 | #define TEGRA124_CLK_KBC 36 | ||
| 56 | /* 37 */ | ||
| 57 | /* 38 */ | ||
| 58 | /* 39 (register bit affects fuse and fuse_burn) */ | ||
| 59 | #define TEGRA124_CLK_KFUSE 40 | ||
| 60 | #define TEGRA124_CLK_SBC1 41 | ||
| 61 | #define TEGRA124_CLK_NOR 42 | ||
| 62 | /* 43 */ | ||
| 63 | #define TEGRA124_CLK_SBC2 44 | ||
| 64 | /* 45 */ | ||
| 65 | #define TEGRA124_CLK_SBC3 46 | ||
| 66 | #define TEGRA124_CLK_I2C5 47 | ||
| 67 | #define TEGRA124_CLK_DSIA 48 | ||
| 68 | /* 49 */ | ||
| 69 | #define TEGRA124_CLK_MIPI 50 | ||
| 70 | #define TEGRA124_CLK_HDMI 51 | ||
| 71 | #define TEGRA124_CLK_CSI 52 | ||
| 72 | /* 53 */ | ||
| 73 | #define TEGRA124_CLK_I2C2 54 | ||
| 74 | #define TEGRA124_CLK_UARTC 55 | ||
| 75 | #define TEGRA124_CLK_MIPI_CAL 56 | ||
| 76 | #define TEGRA124_CLK_EMC 57 | ||
| 77 | #define TEGRA124_CLK_USB2 58 | ||
| 78 | #define TEGRA124_CLK_USB3 59 | ||
| 79 | /* 60 */ | ||
| 80 | #define TEGRA124_CLK_VDE 61 | ||
| 81 | #define TEGRA124_CLK_BSEA 62 | ||
| 82 | #define TEGRA124_CLK_BSEV 63 | ||
| 83 | |||
| 84 | /* 64 */ | ||
| 85 | #define TEGRA124_CLK_UARTD 65 | ||
| 86 | #define TEGRA124_CLK_UARTE 66 | ||
| 87 | #define TEGRA124_CLK_I2C3 67 | ||
| 88 | #define TEGRA124_CLK_SBC4 68 | ||
| 89 | #define TEGRA124_CLK_SDMMC3 69 | ||
| 90 | #define TEGRA124_CLK_PCIE 70 | ||
| 91 | #define TEGRA124_CLK_OWR 71 | ||
| 92 | #define TEGRA124_CLK_AFI 72 | ||
| 93 | #define TEGRA124_CLK_CSITE 73 | ||
| 94 | /* 74 */ | ||
| 95 | /* 75 */ | ||
| 96 | #define TEGRA124_CLK_LA 76 | ||
| 97 | #define TEGRA124_CLK_TRACE 77 | ||
| 98 | #define TEGRA124_CLK_SOC_THERM 78 | ||
| 99 | #define TEGRA124_CLK_DTV 79 | ||
| 100 | #define TEGRA124_CLK_NDSPEED 80 | ||
| 101 | #define TEGRA124_CLK_I2CSLOW 81 | ||
| 102 | #define TEGRA124_CLK_DSIB 82 | ||
| 103 | #define TEGRA124_CLK_TSEC 83 | ||
| 104 | /* 84 */ | ||
| 105 | /* 85 */ | ||
| 106 | /* 86 */ | ||
| 107 | /* 87 */ | ||
| 108 | /* 88 */ | ||
| 109 | #define TEGRA124_CLK_XUSB_HOST 89 | ||
| 110 | /* 90 */ | ||
| 111 | #define TEGRA124_CLK_MSENC 91 | ||
| 112 | #define TEGRA124_CLK_CSUS 92 | ||
| 113 | /* 93 */ | ||
| 114 | /* 94 */ | ||
| 115 | /* 95 (bit affects xusb_dev and xusb_dev_src) */ | ||
| 116 | |||
| 117 | /* 96 */ | ||
| 118 | /* 97 */ | ||
| 119 | /* 98 */ | ||
| 120 | #define TEGRA124_CLK_MSELECT 99 | ||
| 121 | #define TEGRA124_CLK_TSENSOR 100 | ||
| 122 | #define TEGRA124_CLK_I2S3 101 | ||
| 123 | #define TEGRA124_CLK_I2S4 102 | ||
| 124 | #define TEGRA124_CLK_I2C4 103 | ||
| 125 | #define TEGRA124_CLK_SBC5 104 | ||
| 126 | #define TEGRA124_CLK_SBC6 105 | ||
| 127 | #define TEGRA124_CLK_D_AUDIO 106 | ||
| 128 | #define TEGRA124_CLK_APBIF 107 | ||
| 129 | #define TEGRA124_CLK_DAM0 108 | ||
| 130 | #define TEGRA124_CLK_DAM1 109 | ||
| 131 | #define TEGRA124_CLK_DAM2 110 | ||
| 132 | #define TEGRA124_CLK_HDA2CODEC_2X 111 | ||
| 133 | /* 112 */ | ||
| 134 | #define TEGRA124_CLK_AUDIO0_2X 113 | ||
| 135 | #define TEGRA124_CLK_AUDIO1_2X 114 | ||
| 136 | #define TEGRA124_CLK_AUDIO2_2X 115 | ||
| 137 | #define TEGRA124_CLK_AUDIO3_2X 116 | ||
| 138 | #define TEGRA124_CLK_AUDIO4_2X 117 | ||
| 139 | #define TEGRA124_CLK_SPDIF_2X 118 | ||
| 140 | #define TEGRA124_CLK_ACTMON 119 | ||
| 141 | #define TEGRA124_CLK_EXTERN1 120 | ||
| 142 | #define TEGRA124_CLK_EXTERN2 121 | ||
| 143 | #define TEGRA124_CLK_EXTERN3 122 | ||
| 144 | #define TEGRA124_CLK_SATA_OOB 123 | ||
| 145 | #define TEGRA124_CLK_SATA 124 | ||
| 146 | #define TEGRA124_CLK_HDA 125 | ||
| 147 | /* 126 */ | ||
| 148 | #define TEGRA124_CLK_SE 127 | ||
| 149 | |||
| 150 | #define TEGRA124_CLK_HDA2HDMI 128 | ||
| 151 | #define TEGRA124_CLK_SATA_COLD 129 | ||
| 152 | /* 130 */ | ||
| 153 | /* 131 */ | ||
| 154 | /* 132 */ | ||
| 155 | /* 133 */ | ||
| 156 | /* 134 */ | ||
| 157 | /* 135 */ | ||
| 158 | /* 136 */ | ||
| 159 | /* 137 */ | ||
| 160 | /* 138 */ | ||
| 161 | /* 139 */ | ||
| 162 | /* 140 */ | ||
| 163 | /* 141 */ | ||
| 164 | /* 142 */ | ||
| 165 | /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ | ||
| 166 | /* xusb_host_src and xusb_ss_src) */ | ||
| 167 | #define TEGRA124_CLK_CILAB 144 | ||
| 168 | #define TEGRA124_CLK_CILCD 145 | ||
| 169 | #define TEGRA124_CLK_CILE 146 | ||
| 170 | #define TEGRA124_CLK_DSIALP 147 | ||
| 171 | #define TEGRA124_CLK_DSIBLP 148 | ||
| 172 | #define TEGRA124_CLK_ENTROPY 149 | ||
| 173 | #define TEGRA124_CLK_DDS 150 | ||
| 174 | /* 151 */ | ||
| 175 | #define TEGRA124_CLK_DP2 152 | ||
| 176 | #define TEGRA124_CLK_AMX 153 | ||
| 177 | #define TEGRA124_CLK_ADX 154 | ||
| 178 | /* 155 (bit affects dfll_ref and dfll_soc) */ | ||
| 179 | #define TEGRA124_CLK_XUSB_SS 156 | ||
| 180 | /* 157 */ | ||
| 181 | /* 158 */ | ||
| 182 | /* 159 */ | ||
| 183 | |||
| 184 | /* 160 */ | ||
| 185 | /* 161 */ | ||
| 186 | /* 162 */ | ||
| 187 | /* 163 */ | ||
| 188 | /* 164 */ | ||
| 189 | /* 165 */ | ||
| 190 | #define TEGRA124_CLK_I2C6 166 | ||
| 191 | /* 167 */ | ||
| 192 | /* 168 */ | ||
| 193 | /* 169 */ | ||
| 194 | /* 170 */ | ||
| 195 | #define TEGRA124_CLK_VIM2_CLK 171 | ||
| 196 | /* 172 */ | ||
| 197 | /* 173 */ | ||
| 198 | /* 174 */ | ||
| 199 | /* 175 */ | ||
| 200 | #define TEGRA124_CLK_HDMI_AUDIO 176 | ||
| 201 | #define TEGRA124_CLK_CLK72MHZ 177 | ||
| 202 | #define TEGRA124_CLK_VIC03 178 | ||
| 203 | /* 179 */ | ||
| 204 | #define TEGRA124_CLK_ADX1 180 | ||
| 205 | #define TEGRA124_CLK_DPAUX 181 | ||
| 206 | #define TEGRA124_CLK_SOR0 182 | ||
| 207 | /* 183 */ | ||
| 208 | #define TEGRA124_CLK_GPU 184 | ||
| 209 | #define TEGRA124_CLK_AMX1 185 | ||
| 210 | /* 186 */ | ||
| 211 | /* 187 */ | ||
| 212 | /* 188 */ | ||
| 213 | /* 189 */ | ||
| 214 | /* 190 */ | ||
| 215 | /* 191 */ | ||
| 216 | #define TEGRA124_CLK_UARTB 192 | ||
| 217 | #define TEGRA124_CLK_VFIR 193 | ||
| 218 | #define TEGRA124_CLK_SPDIF_IN 194 | ||
| 219 | #define TEGRA124_CLK_SPDIF_OUT 195 | ||
| 220 | #define TEGRA124_CLK_VI 196 | ||
| 221 | #define TEGRA124_CLK_VI_SENSOR 197 | ||
| 222 | #define TEGRA124_CLK_FUSE 198 | ||
| 223 | #define TEGRA124_CLK_FUSE_BURN 199 | ||
| 224 | #define TEGRA124_CLK_CLK_32K 200 | ||
| 225 | #define TEGRA124_CLK_CLK_M 201 | ||
| 226 | #define TEGRA124_CLK_CLK_M_DIV2 202 | ||
| 227 | #define TEGRA124_CLK_CLK_M_DIV4 203 | ||
| 228 | #define TEGRA124_CLK_PLL_REF 204 | ||
| 229 | #define TEGRA124_CLK_PLL_C 205 | ||
| 230 | #define TEGRA124_CLK_PLL_C_OUT1 206 | ||
| 231 | #define TEGRA124_CLK_PLL_C2 207 | ||
| 232 | #define TEGRA124_CLK_PLL_C3 208 | ||
| 233 | #define TEGRA124_CLK_PLL_M 209 | ||
| 234 | #define TEGRA124_CLK_PLL_M_OUT1 210 | ||
| 235 | #define TEGRA124_CLK_PLL_P 211 | ||
| 236 | #define TEGRA124_CLK_PLL_P_OUT1 212 | ||
| 237 | #define TEGRA124_CLK_PLL_P_OUT2 213 | ||
| 238 | #define TEGRA124_CLK_PLL_P_OUT3 214 | ||
| 239 | #define TEGRA124_CLK_PLL_P_OUT4 215 | ||
| 240 | #define TEGRA124_CLK_PLL_A 216 | ||
| 241 | #define TEGRA124_CLK_PLL_A_OUT0 217 | ||
| 242 | #define TEGRA124_CLK_PLL_D 218 | ||
| 243 | #define TEGRA124_CLK_PLL_D_OUT0 219 | ||
| 244 | #define TEGRA124_CLK_PLL_D2 220 | ||
| 245 | #define TEGRA124_CLK_PLL_D2_OUT0 221 | ||
| 246 | #define TEGRA124_CLK_PLL_U 222 | ||
| 247 | #define TEGRA124_CLK_PLL_U_480M 223 | ||
| 248 | |||
| 249 | #define TEGRA124_CLK_PLL_U_60M 224 | ||
| 250 | #define TEGRA124_CLK_PLL_U_48M 225 | ||
| 251 | #define TEGRA124_CLK_PLL_U_12M 226 | ||
| 252 | #define TEGRA124_CLK_PLL_X 227 | ||
| 253 | #define TEGRA124_CLK_PLL_X_OUT0 228 | ||
| 254 | #define TEGRA124_CLK_PLL_RE_VCO 229 | ||
| 255 | #define TEGRA124_CLK_PLL_RE_OUT 230 | ||
| 256 | #define TEGRA124_CLK_PLL_E 231 | ||
| 257 | #define TEGRA124_CLK_SPDIF_IN_SYNC 232 | ||
| 258 | #define TEGRA124_CLK_I2S0_SYNC 233 | ||
| 259 | #define TEGRA124_CLK_I2S1_SYNC 234 | ||
| 260 | #define TEGRA124_CLK_I2S2_SYNC 235 | ||
| 261 | #define TEGRA124_CLK_I2S3_SYNC 236 | ||
| 262 | #define TEGRA124_CLK_I2S4_SYNC 237 | ||
| 263 | #define TEGRA124_CLK_VIMCLK_SYNC 238 | ||
| 264 | #define TEGRA124_CLK_AUDIO0 239 | ||
| 265 | #define TEGRA124_CLK_AUDIO1 240 | ||
| 266 | #define TEGRA124_CLK_AUDIO2 241 | ||
| 267 | #define TEGRA124_CLK_AUDIO3 242 | ||
| 268 | #define TEGRA124_CLK_AUDIO4 243 | ||
| 269 | #define TEGRA124_CLK_SPDIF 244 | ||
| 270 | #define TEGRA124_CLK_CLK_OUT_1 245 | ||
| 271 | #define TEGRA124_CLK_CLK_OUT_2 246 | ||
| 272 | #define TEGRA124_CLK_CLK_OUT_3 247 | ||
| 273 | #define TEGRA124_CLK_BLINK 248 | ||
| 274 | /* 249 */ | ||
| 275 | /* 250 */ | ||
| 276 | /* 251 */ | ||
| 277 | #define TEGRA124_CLK_XUSB_HOST_SRC 252 | ||
| 278 | #define TEGRA124_CLK_XUSB_FALCON_SRC 253 | ||
| 279 | #define TEGRA124_CLK_XUSB_FS_SRC 254 | ||
| 280 | #define TEGRA124_CLK_XUSB_SS_SRC 255 | ||
| 281 | |||
| 282 | #define TEGRA124_CLK_XUSB_DEV_SRC 256 | ||
| 283 | #define TEGRA124_CLK_XUSB_DEV 257 | ||
| 284 | #define TEGRA124_CLK_XUSB_HS_SRC 258 | ||
| 285 | #define TEGRA124_CLK_SCLK 259 | ||
| 286 | #define TEGRA124_CLK_HCLK 260 | ||
| 287 | #define TEGRA124_CLK_PCLK 261 | ||
| 288 | #define TEGRA124_CLK_CCLK_G 262 | ||
| 289 | #define TEGRA124_CLK_CCLK_LP 263 | ||
| 290 | #define TEGRA124_CLK_DFLL_REF 264 | ||
| 291 | #define TEGRA124_CLK_DFLL_SOC 265 | ||
| 292 | #define TEGRA124_CLK_VI_SENSOR2 266 | ||
| 293 | #define TEGRA124_CLK_PLL_P_OUT5 267 | ||
| 294 | #define TEGRA124_CLK_CML0 268 | ||
| 295 | #define TEGRA124_CLK_CML1 269 | ||
| 296 | #define TEGRA124_CLK_PLL_C4 270 | ||
| 297 | #define TEGRA124_CLK_PLL_DP 271 | ||
| 298 | #define TEGRA124_CLK_PLL_E_MUX 272 | ||
| 299 | /* 273 */ | ||
| 300 | /* 274 */ | ||
| 301 | /* 275 */ | ||
| 302 | /* 276 */ | ||
| 303 | /* 277 */ | ||
| 304 | /* 278 */ | ||
| 305 | /* 279 */ | ||
| 306 | /* 280 */ | ||
| 307 | /* 281 */ | ||
| 308 | /* 282 */ | ||
| 309 | /* 283 */ | ||
| 310 | /* 284 */ | ||
| 311 | /* 285 */ | ||
| 312 | /* 286 */ | ||
| 313 | /* 287 */ | ||
| 314 | |||
| 315 | /* 288 */ | ||
| 316 | /* 289 */ | ||
| 317 | /* 290 */ | ||
| 318 | /* 291 */ | ||
| 319 | /* 292 */ | ||
| 320 | /* 293 */ | ||
| 321 | /* 294 */ | ||
| 322 | /* 295 */ | ||
| 323 | /* 296 */ | ||
| 324 | /* 297 */ | ||
| 325 | /* 298 */ | ||
| 326 | /* 299 */ | ||
| 327 | #define TEGRA124_CLK_AUDIO0_MUX 300 | ||
| 328 | #define TEGRA124_CLK_AUDIO1_MUX 301 | ||
| 329 | #define TEGRA124_CLK_AUDIO2_MUX 302 | ||
| 330 | #define TEGRA124_CLK_AUDIO3_MUX 303 | ||
| 331 | #define TEGRA124_CLK_AUDIO4_MUX 304 | ||
| 332 | #define TEGRA124_CLK_SPDIF_MUX 305 | ||
| 333 | #define TEGRA124_CLK_CLK_OUT_1_MUX 306 | ||
| 334 | #define TEGRA124_CLK_CLK_OUT_2_MUX 307 | ||
| 335 | #define TEGRA124_CLK_CLK_OUT_3_MUX 308 | ||
| 336 | #define TEGRA124_CLK_DSIA_MUX 309 | ||
| 337 | #define TEGRA124_CLK_DSIB_MUX 310 | ||
| 338 | #define TEGRA124_CLK_SOR0_LVDS 311 | ||
| 339 | #define TEGRA124_CLK_CLK_MAX 312 | ||
| 340 | |||
| 341 | #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ | ||
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h index a1ae9a8fdd6c..9406207cfac8 100644 --- a/include/dt-bindings/clock/tegra20-car.h +++ b/include/dt-bindings/clock/tegra20-car.h | |||
| @@ -92,7 +92,7 @@ | |||
| 92 | #define TEGRA20_CLK_OWR 71 | 92 | #define TEGRA20_CLK_OWR 71 |
| 93 | #define TEGRA20_CLK_AFI 72 | 93 | #define TEGRA20_CLK_AFI 72 |
| 94 | #define TEGRA20_CLK_CSITE 73 | 94 | #define TEGRA20_CLK_CSITE 73 |
| 95 | #define TEGRA20_CLK_PCIE_XCLK 74 | 95 | /* 74 */ |
| 96 | #define TEGRA20_CLK_AVPUCQ 75 | 96 | #define TEGRA20_CLK_AVPUCQ 75 |
| 97 | #define TEGRA20_CLK_LA 76 | 97 | #define TEGRA20_CLK_LA 76 |
| 98 | /* 77 */ | 98 | /* 77 */ |
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index e40fae8f9a8d..889e49ba0aa3 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h | |||
| @@ -92,7 +92,7 @@ | |||
| 92 | #define TEGRA30_CLK_OWR 71 | 92 | #define TEGRA30_CLK_OWR 71 |
| 93 | #define TEGRA30_CLK_AFI 72 | 93 | #define TEGRA30_CLK_AFI 72 |
| 94 | #define TEGRA30_CLK_CSITE 73 | 94 | #define TEGRA30_CLK_CSITE 73 |
| 95 | #define TEGRA30_CLK_PCIEX 74 | 95 | /* 74 */ |
| 96 | #define TEGRA30_CLK_AVPUCQ 75 | 96 | #define TEGRA30_CLK_AVPUCQ 75 |
| 97 | #define TEGRA30_CLK_LA 76 | 97 | #define TEGRA30_CLK_LA 76 |
| 98 | /* 77 */ | 98 | /* 77 */ |
| @@ -260,6 +260,14 @@ | |||
| 260 | /* 298 */ | 260 | /* 298 */ |
| 261 | /* 299 */ | 261 | /* 299 */ |
| 262 | #define TEGRA30_CLK_CLK_OUT_1_MUX 300 | 262 | #define TEGRA30_CLK_CLK_OUT_1_MUX 300 |
| 263 | #define TEGRA30_CLK_CLK_MAX 301 | 263 | #define TEGRA30_CLK_CLK_OUT_2_MUX 301 |
| 264 | #define TEGRA30_CLK_CLK_OUT_3_MUX 302 | ||
| 265 | #define TEGRA30_CLK_AUDIO0_MUX 303 | ||
| 266 | #define TEGRA30_CLK_AUDIO1_MUX 304 | ||
| 267 | #define TEGRA30_CLK_AUDIO2_MUX 305 | ||
| 268 | #define TEGRA30_CLK_AUDIO3_MUX 306 | ||
| 269 | #define TEGRA30_CLK_AUDIO4_MUX 307 | ||
| 270 | #define TEGRA30_CLK_SPDIF_MUX 308 | ||
| 271 | #define TEGRA30_CLK_CLK_MAX 309 | ||
| 264 | 272 | ||
| 265 | #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ | 273 | #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ |
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 4aa2b48cd151..a91602951d3d 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h | |||
| @@ -160,6 +160,10 @@ | |||
| 160 | #define VF610_CLK_GPU2D 147 | 160 | #define VF610_CLK_GPU2D 147 |
| 161 | #define VF610_CLK_ENET0 148 | 161 | #define VF610_CLK_ENET0 148 |
| 162 | #define VF610_CLK_ENET1 149 | 162 | #define VF610_CLK_ENET1 149 |
| 163 | #define VF610_CLK_END 150 | 163 | #define VF610_CLK_DMAMUX0 150 |
| 164 | #define VF610_CLK_DMAMUX1 151 | ||
| 165 | #define VF610_CLK_DMAMUX2 152 | ||
| 166 | #define VF610_CLK_DMAMUX3 153 | ||
| 167 | #define VF610_CLK_END 154 | ||
| 164 | 168 | ||
| 165 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ | 169 | #endif /* __DT_BINDINGS_CLOCK_VF610_H */ |
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h index 4d179c00f081..197dc28b676e 100644 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ b/include/dt-bindings/gpio/tegra-gpio.h | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #define TEGRA_GPIO_BANK_ID_CC 28 | 43 | #define TEGRA_GPIO_BANK_ID_CC 28 |
| 44 | #define TEGRA_GPIO_BANK_ID_DD 29 | 44 | #define TEGRA_GPIO_BANK_ID_DD 29 |
| 45 | #define TEGRA_GPIO_BANK_ID_EE 30 | 45 | #define TEGRA_GPIO_BANK_ID_EE 30 |
| 46 | #define TEGRA_GPIO_BANK_ID_FF 31 | ||
| 46 | 47 | ||
| 47 | #define TEGRA_GPIO(bank, offset) \ | 48 | #define TEGRA_GPIO(bank, offset) \ |
| 48 | ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) | 49 | ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) |
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h index bed35e36fd27..b04528cd033c 100644 --- a/include/dt-bindings/pinctrl/omap.h +++ b/include/dt-bindings/pinctrl/omap.h | |||
| @@ -49,5 +49,25 @@ | |||
| 49 | #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) | 49 | #define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN) |
| 50 | #define PIN_OFF_WAKEUPENABLE WAKEUP_EN | 50 | #define PIN_OFF_WAKEUPENABLE WAKEUP_EN |
| 51 | 51 | ||
| 52 | /* | ||
| 53 | * Macros to allow using the absolute physical address instead of the | ||
| 54 | * padconf registers instead of the offset from padconf base. | ||
| 55 | */ | ||
| 56 | #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) | ||
| 57 | |||
| 58 | #define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) | ||
| 59 | #define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) | ||
| 60 | #define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) | ||
| 61 | #define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) | ||
| 62 | #define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) | ||
| 63 | #define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) | ||
| 64 | #define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) | ||
| 65 | #define OMAP4_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0040) (val) | ||
| 66 | #define OMAP4_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xe040) (val) | ||
| 67 | #define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) | ||
| 68 | #define OMAP5_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2840) (val) | ||
| 69 | #define OMAP5_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0xc840) (val) | ||
| 70 | #define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val) | ||
| 71 | |||
| 52 | #endif | 72 | #endif |
| 53 | 73 | ||
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 000000000000..ebafa498be0f --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for Tegra pinctrl bindings. | ||
| 3 | * | ||
| 4 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
| 5 | * | ||
| 6 | * Author: Laxman Dewangan <ldewangan@nvidia.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms and conditions of the GNU General Public License, | ||
| 10 | * version 2, as published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 15 | * more details. | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _DT_BINDINGS_PINCTRL_TEGRA_H | ||
| 19 | #define _DT_BINDINGS_PINCTRL_TEGRA_H | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Enable/disable for diffeent dt properties. This is applicable for | ||
| 23 | * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, | ||
| 24 | * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. | ||
| 25 | */ | ||
| 26 | #define TEGRA_PIN_DISABLE 0 | ||
| 27 | #define TEGRA_PIN_ENABLE 1 | ||
| 28 | |||
| 29 | #define TEGRA_PIN_PULL_NONE 0 | ||
| 30 | #define TEGRA_PIN_PULL_DOWN 1 | ||
| 31 | #define TEGRA_PIN_PULL_UP 2 | ||
| 32 | |||
| 33 | /* Low power mode driver */ | ||
| 34 | #define TEGRA_PIN_LP_DRIVE_DIV_8 0 | ||
| 35 | #define TEGRA_PIN_LP_DRIVE_DIV_4 1 | ||
| 36 | #define TEGRA_PIN_LP_DRIVE_DIV_2 2 | ||
| 37 | #define TEGRA_PIN_LP_DRIVE_DIV_1 3 | ||
| 38 | |||
| 39 | /* Rising/Falling slew rate */ | ||
| 40 | #define TEGRA_PIN_SLEW_RATE_FASTEST 0 | ||
| 41 | #define TEGRA_PIN_SLEW_RATE_FAST 1 | ||
| 42 | #define TEGRA_PIN_SLEW_RATE_SLOW 2 | ||
| 43 | #define TEGRA_PIN_SLEW_RATE_SLOWEST 3 | ||
| 44 | |||
| 45 | #endif | ||
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8660.h b/include/dt-bindings/reset/qcom,gcc-msm8660.h new file mode 100644 index 000000000000..a83282fe5465 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8660.h | |||
| @@ -0,0 +1,134 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H | ||
| 15 | #define _DT_BINDINGS_RESET_MSM_GCC_8660_H | ||
| 16 | |||
| 17 | #define AFAB_CORE_RESET 0 | ||
| 18 | #define SCSS_SYS_RESET 1 | ||
| 19 | #define SCSS_SYS_POR_RESET 2 | ||
| 20 | #define AFAB_SMPSS_S_RESET 3 | ||
| 21 | #define AFAB_SMPSS_M1_RESET 4 | ||
| 22 | #define AFAB_SMPSS_M0_RESET 5 | ||
| 23 | #define AFAB_EBI1_S_RESET 6 | ||
| 24 | #define SFAB_CORE_RESET 7 | ||
| 25 | #define SFAB_ADM0_M0_RESET 8 | ||
| 26 | #define SFAB_ADM0_M1_RESET 9 | ||
| 27 | #define SFAB_ADM0_M2_RESET 10 | ||
| 28 | #define ADM0_C2_RESET 11 | ||
| 29 | #define ADM0_C1_RESET 12 | ||
| 30 | #define ADM0_C0_RESET 13 | ||
| 31 | #define ADM0_PBUS_RESET 14 | ||
| 32 | #define ADM0_RESET 15 | ||
| 33 | #define SFAB_ADM1_M0_RESET 16 | ||
| 34 | #define SFAB_ADM1_M1_RESET 17 | ||
| 35 | #define SFAB_ADM1_M2_RESET 18 | ||
| 36 | #define MMFAB_ADM1_M3_RESET 19 | ||
| 37 | #define ADM1_C3_RESET 20 | ||
| 38 | #define ADM1_C2_RESET 21 | ||
| 39 | #define ADM1_C1_RESET 22 | ||
| 40 | #define ADM1_C0_RESET 23 | ||
| 41 | #define ADM1_PBUS_RESET 24 | ||
| 42 | #define ADM1_RESET 25 | ||
| 43 | #define IMEM0_RESET 26 | ||
| 44 | #define SFAB_LPASS_Q6_RESET 27 | ||
| 45 | #define SFAB_AFAB_M_RESET 28 | ||
| 46 | #define AFAB_SFAB_M0_RESET 29 | ||
| 47 | #define AFAB_SFAB_M1_RESET 30 | ||
| 48 | #define DFAB_CORE_RESET 31 | ||
| 49 | #define SFAB_DFAB_M_RESET 32 | ||
| 50 | #define DFAB_SFAB_M_RESET 33 | ||
| 51 | #define DFAB_SWAY0_RESET 34 | ||
| 52 | #define DFAB_SWAY1_RESET 35 | ||
| 53 | #define DFAB_ARB0_RESET 36 | ||
| 54 | #define DFAB_ARB1_RESET 37 | ||
| 55 | #define PPSS_PROC_RESET 38 | ||
| 56 | #define PPSS_RESET 39 | ||
| 57 | #define PMEM_RESET 40 | ||
| 58 | #define DMA_BAM_RESET 41 | ||
| 59 | #define SIC_RESET 42 | ||
| 60 | #define SPS_TIC_RESET 43 | ||
| 61 | #define CFBP0_RESET 44 | ||
| 62 | #define CFBP1_RESET 45 | ||
| 63 | #define CFBP2_RESET 46 | ||
| 64 | #define EBI2_RESET 47 | ||
| 65 | #define SFAB_CFPB_M_RESET 48 | ||
| 66 | #define CFPB_MASTER_RESET 49 | ||
| 67 | #define SFAB_CFPB_S_RESET 50 | ||
| 68 | #define CFPB_SPLITTER_RESET 51 | ||
| 69 | #define TSIF_RESET 52 | ||
| 70 | #define CE1_RESET 53 | ||
| 71 | #define CE2_RESET 54 | ||
| 72 | #define SFAB_SFPB_M_RESET 55 | ||
| 73 | #define SFAB_SFPB_S_RESET 56 | ||
| 74 | #define RPM_PROC_RESET 57 | ||
| 75 | #define RPM_BUS_RESET 58 | ||
| 76 | #define RPM_MSG_RAM_RESET 59 | ||
| 77 | #define PMIC_ARB0_RESET 60 | ||
| 78 | #define PMIC_ARB1_RESET 61 | ||
| 79 | #define PMIC_SSBI2_RESET 62 | ||
| 80 | #define SDC1_RESET 63 | ||
| 81 | #define SDC2_RESET 64 | ||
| 82 | #define SDC3_RESET 65 | ||
| 83 | #define SDC4_RESET 66 | ||
| 84 | #define SDC5_RESET 67 | ||
| 85 | #define USB_HS1_RESET 68 | ||
| 86 | #define USB_HS2_XCVR_RESET 69 | ||
| 87 | #define USB_HS2_RESET 70 | ||
| 88 | #define USB_FS1_XCVR_RESET 71 | ||
| 89 | #define USB_FS1_RESET 72 | ||
| 90 | #define USB_FS2_XCVR_RESET 73 | ||
| 91 | #define USB_FS2_RESET 74 | ||
| 92 | #define GSBI1_RESET 75 | ||
| 93 | #define GSBI2_RESET 76 | ||
| 94 | #define GSBI3_RESET 77 | ||
| 95 | #define GSBI4_RESET 78 | ||
| 96 | #define GSBI5_RESET 79 | ||
| 97 | #define GSBI6_RESET 80 | ||
| 98 | #define GSBI7_RESET 81 | ||
| 99 | #define GSBI8_RESET 82 | ||
| 100 | #define GSBI9_RESET 83 | ||
| 101 | #define GSBI10_RESET 84 | ||
| 102 | #define GSBI11_RESET 85 | ||
| 103 | #define GSBI12_RESET 86 | ||
| 104 | #define SPDM_RESET 87 | ||
| 105 | #define SEC_CTRL_RESET 88 | ||
| 106 | #define TLMM_H_RESET 89 | ||
| 107 | #define TLMM_RESET 90 | ||
| 108 | #define MARRM_PWRON_RESET 91 | ||
| 109 | #define MARM_RESET 92 | ||
| 110 | #define MAHB1_RESET 93 | ||
| 111 | #define SFAB_MSS_S_RESET 94 | ||
| 112 | #define MAHB2_RESET 95 | ||
| 113 | #define MODEM_SW_AHB_RESET 96 | ||
| 114 | #define MODEM_RESET 97 | ||
| 115 | #define SFAB_MSS_MDM1_RESET 98 | ||
| 116 | #define SFAB_MSS_MDM0_RESET 99 | ||
| 117 | #define MSS_SLP_RESET 100 | ||
| 118 | #define MSS_MARM_SAW_RESET 101 | ||
| 119 | #define MSS_WDOG_RESET 102 | ||
| 120 | #define TSSC_RESET 103 | ||
| 121 | #define PDM_RESET 104 | ||
| 122 | #define SCSS_CORE0_RESET 105 | ||
| 123 | #define SCSS_CORE0_POR_RESET 106 | ||
| 124 | #define SCSS_CORE1_RESET 107 | ||
| 125 | #define SCSS_CORE1_POR_RESET 108 | ||
| 126 | #define MPM_RESET 109 | ||
| 127 | #define EBI1_1X_DIV_RESET 110 | ||
| 128 | #define EBI1_RESET 111 | ||
| 129 | #define SFAB_SMPSS_S_RESET 112 | ||
| 130 | #define USB_PHY0_RESET 113 | ||
| 131 | #define USB_PHY1_RESET 114 | ||
| 132 | #define PRNG_RESET 115 | ||
| 133 | |||
| 134 | #endif | ||
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h new file mode 100644 index 000000000000..a840e680323c --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h | |||
| @@ -0,0 +1,118 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H | ||
| 15 | #define _DT_BINDINGS_RESET_MSM_GCC_8960_H | ||
| 16 | |||
| 17 | #define SFAB_MSS_Q6_SW_RESET 0 | ||
| 18 | #define SFAB_MSS_Q6_FW_RESET 1 | ||
| 19 | #define QDSS_STM_RESET 2 | ||
| 20 | #define AFAB_SMPSS_S_RESET 3 | ||
| 21 | #define AFAB_SMPSS_M1_RESET 4 | ||
| 22 | #define AFAB_SMPSS_M0_RESET 5 | ||
| 23 | #define AFAB_EBI1_CH0_RESET 6 | ||
| 24 | #define AFAB_EBI1_CH1_RESET 7 | ||
| 25 | #define SFAB_ADM0_M0_RESET 8 | ||
| 26 | #define SFAB_ADM0_M1_RESET 9 | ||
| 27 | #define SFAB_ADM0_M2_RESET 10 | ||
| 28 | #define ADM0_C2_RESET 11 | ||
| 29 | #define ADM0_C1_RESET 12 | ||
| 30 | #define ADM0_C0_RESET 13 | ||
| 31 | #define ADM0_PBUS_RESET 14 | ||
| 32 | #define ADM0_RESET 15 | ||
| 33 | #define QDSS_CLKS_SW_RESET 16 | ||
| 34 | #define QDSS_POR_RESET 17 | ||
| 35 | #define QDSS_TSCTR_RESET 18 | ||
| 36 | #define QDSS_HRESET_RESET 19 | ||
| 37 | #define QDSS_AXI_RESET 20 | ||
| 38 | #define QDSS_DBG_RESET 21 | ||
| 39 | #define PCIE_A_RESET 22 | ||
| 40 | #define PCIE_AUX_RESET 23 | ||
| 41 | #define PCIE_H_RESET 24 | ||
| 42 | #define SFAB_PCIE_M_RESET 25 | ||
| 43 | #define SFAB_PCIE_S_RESET 26 | ||
| 44 | #define SFAB_MSS_M_RESET 27 | ||
| 45 | #define SFAB_USB3_M_RESET 28 | ||
| 46 | #define SFAB_RIVA_M_RESET 29 | ||
| 47 | #define SFAB_LPASS_RESET 30 | ||
| 48 | #define SFAB_AFAB_M_RESET 31 | ||
| 49 | #define AFAB_SFAB_M0_RESET 32 | ||
| 50 | #define AFAB_SFAB_M1_RESET 33 | ||
| 51 | #define SFAB_SATA_S_RESET 34 | ||
| 52 | #define SFAB_DFAB_M_RESET 35 | ||
| 53 | #define DFAB_SFAB_M_RESET 36 | ||
| 54 | #define DFAB_SWAY0_RESET 37 | ||
| 55 | #define DFAB_SWAY1_RESET 38 | ||
| 56 | #define DFAB_ARB0_RESET 39 | ||
| 57 | #define DFAB_ARB1_RESET 40 | ||
| 58 | #define PPSS_PROC_RESET 41 | ||
| 59 | #define PPSS_RESET 42 | ||
| 60 | #define DMA_BAM_RESET 43 | ||
| 61 | #define SIC_TIC_RESET 44 | ||
| 62 | #define SLIMBUS_H_RESET 45 | ||
| 63 | #define SFAB_CFPB_M_RESET 46 | ||
| 64 | #define SFAB_CFPB_S_RESET 47 | ||
| 65 | #define TSIF_H_RESET 48 | ||
| 66 | #define CE1_H_RESET 49 | ||
| 67 | #define CE1_CORE_RESET 50 | ||
| 68 | #define CE1_SLEEP_RESET 51 | ||
| 69 | #define CE2_H_RESET 52 | ||
| 70 | #define CE2_CORE_RESET 53 | ||
| 71 | #define SFAB_SFPB_M_RESET 54 | ||
| 72 | #define SFAB_SFPB_S_RESET 55 | ||
| 73 | #define RPM_PROC_RESET 56 | ||
| 74 | #define PMIC_SSBI2_RESET 57 | ||
| 75 | #define SDC1_RESET 58 | ||
| 76 | #define SDC2_RESET 59 | ||
| 77 | #define SDC3_RESET 60 | ||
| 78 | #define SDC4_RESET 61 | ||
| 79 | #define SDC5_RESET 62 | ||
| 80 | #define DFAB_A2_RESET 63 | ||
| 81 | #define USB_HS1_RESET 64 | ||
| 82 | #define USB_HSIC_RESET 65 | ||
| 83 | #define USB_FS1_XCVR_RESET 66 | ||
| 84 | #define USB_FS1_RESET 67 | ||
| 85 | #define USB_FS2_XCVR_RESET 68 | ||
| 86 | #define USB_FS2_RESET 69 | ||
| 87 | #define GSBI1_RESET 70 | ||
| 88 | #define GSBI2_RESET 71 | ||
| 89 | #define GSBI3_RESET 72 | ||
| 90 | #define GSBI4_RESET 73 | ||
| 91 | #define GSBI5_RESET 74 | ||
| 92 | #define GSBI6_RESET 75 | ||
| 93 | #define GSBI7_RESET 76 | ||
| 94 | #define GSBI8_RESET 77 | ||
| 95 | #define GSBI9_RESET 78 | ||
| 96 | #define GSBI10_RESET 79 | ||
| 97 | #define GSBI11_RESET 80 | ||
| 98 | #define GSBI12_RESET 81 | ||
| 99 | #define SPDM_RESET 82 | ||
| 100 | #define TLMM_H_RESET 83 | ||
| 101 | #define SFAB_MSS_S_RESET 84 | ||
| 102 | #define MSS_SLP_RESET 85 | ||
| 103 | #define MSS_Q6SW_JTAG_RESET 86 | ||
| 104 | #define MSS_Q6FW_JTAG_RESET 87 | ||
| 105 | #define MSS_RESET 88 | ||
| 106 | #define SATA_H_RESET 89 | ||
| 107 | #define SATA_RXOOB_RESE 90 | ||
| 108 | #define SATA_PMALIVE_RESET 91 | ||
| 109 | #define SATA_SFAB_M_RESET 92 | ||
| 110 | #define TSSC_RESET 93 | ||
| 111 | #define PDM_RESET 94 | ||
| 112 | #define MPM_H_RESET 95 | ||
| 113 | #define MPM_RESET 96 | ||
| 114 | #define SFAB_SMPSS_S_RESET 97 | ||
| 115 | #define PRNG_RESET 98 | ||
| 116 | #define RIVA_RESET 99 | ||
| 117 | |||
| 118 | #endif | ||
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8974.h b/include/dt-bindings/reset/qcom,gcc-msm8974.h new file mode 100644 index 000000000000..9bdf54322938 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8974.h | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H | ||
| 15 | #define _DT_BINDINGS_RESET_MSM_GCC_8974_H | ||
| 16 | |||
| 17 | #define GCC_SYSTEM_NOC_BCR 0 | ||
| 18 | #define GCC_CONFIG_NOC_BCR 1 | ||
| 19 | #define GCC_PERIPH_NOC_BCR 2 | ||
| 20 | #define GCC_IMEM_BCR 3 | ||
| 21 | #define GCC_MMSS_BCR 4 | ||
| 22 | #define GCC_QDSS_BCR 5 | ||
| 23 | #define GCC_USB_30_BCR 6 | ||
| 24 | #define GCC_USB3_PHY_BCR 7 | ||
| 25 | #define GCC_USB_HS_HSIC_BCR 8 | ||
| 26 | #define GCC_USB_HS_BCR 9 | ||
| 27 | #define GCC_USB2A_PHY_BCR 10 | ||
| 28 | #define GCC_USB2B_PHY_BCR 11 | ||
| 29 | #define GCC_SDCC1_BCR 12 | ||
| 30 | #define GCC_SDCC2_BCR 13 | ||
| 31 | #define GCC_SDCC3_BCR 14 | ||
| 32 | #define GCC_SDCC4_BCR 15 | ||
| 33 | #define GCC_BLSP1_BCR 16 | ||
| 34 | #define GCC_BLSP1_QUP1_BCR 17 | ||
| 35 | #define GCC_BLSP1_UART1_BCR 18 | ||
| 36 | #define GCC_BLSP1_QUP2_BCR 19 | ||
| 37 | #define GCC_BLSP1_UART2_BCR 20 | ||
| 38 | #define GCC_BLSP1_QUP3_BCR 21 | ||
| 39 | #define GCC_BLSP1_UART3_BCR 22 | ||
| 40 | #define GCC_BLSP1_QUP4_BCR 23 | ||
| 41 | #define GCC_BLSP1_UART4_BCR 24 | ||
| 42 | #define GCC_BLSP1_QUP5_BCR 25 | ||
| 43 | #define GCC_BLSP1_UART5_BCR 26 | ||
| 44 | #define GCC_BLSP1_QUP6_BCR 27 | ||
| 45 | #define GCC_BLSP1_UART6_BCR 28 | ||
| 46 | #define GCC_BLSP2_BCR 29 | ||
| 47 | #define GCC_BLSP2_QUP1_BCR 30 | ||
| 48 | #define GCC_BLSP2_UART1_BCR 31 | ||
| 49 | #define GCC_BLSP2_QUP2_BCR 32 | ||
| 50 | #define GCC_BLSP2_UART2_BCR 33 | ||
| 51 | #define GCC_BLSP2_QUP3_BCR 34 | ||
| 52 | #define GCC_BLSP2_UART3_BCR 35 | ||
| 53 | #define GCC_BLSP2_QUP4_BCR 36 | ||
| 54 | #define GCC_BLSP2_UART4_BCR 37 | ||
| 55 | #define GCC_BLSP2_QUP5_BCR 38 | ||
| 56 | #define GCC_BLSP2_UART5_BCR 39 | ||
| 57 | #define GCC_BLSP2_QUP6_BCR 40 | ||
| 58 | #define GCC_BLSP2_UART6_BCR 41 | ||
| 59 | #define GCC_PDM_BCR 42 | ||
| 60 | #define GCC_BAM_DMA_BCR 43 | ||
| 61 | #define GCC_TSIF_BCR 44 | ||
| 62 | #define GCC_TCSR_BCR 45 | ||
| 63 | #define GCC_BOOT_ROM_BCR 46 | ||
| 64 | #define GCC_MSG_RAM_BCR 47 | ||
| 65 | #define GCC_TLMM_BCR 48 | ||
| 66 | #define GCC_MPM_BCR 49 | ||
| 67 | #define GCC_SEC_CTRL_BCR 50 | ||
| 68 | #define GCC_SPMI_BCR 51 | ||
| 69 | #define GCC_SPDM_BCR 52 | ||
| 70 | #define GCC_CE1_BCR 53 | ||
| 71 | #define GCC_CE2_BCR 54 | ||
| 72 | #define GCC_BIMC_BCR 55 | ||
| 73 | #define GCC_MPM_NON_AHB_RESET 56 | ||
| 74 | #define GCC_MPM_AHB_RESET 57 | ||
| 75 | #define GCC_SNOC_BUS_TIMEOUT0_BCR 58 | ||
| 76 | #define GCC_SNOC_BUS_TIMEOUT2_BCR 59 | ||
| 77 | #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 | ||
| 78 | #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 | ||
| 79 | #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 | ||
| 80 | #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 | ||
| 81 | #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 | ||
| 82 | #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 | ||
| 83 | #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 | ||
| 84 | #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 | ||
| 85 | #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 | ||
| 86 | #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 | ||
| 87 | #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 | ||
| 88 | #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 | ||
| 89 | #define GCC_DEHR_BCR 72 | ||
| 90 | #define GCC_RBCPR_BCR 73 | ||
| 91 | #define GCC_MSS_RESTART 74 | ||
| 92 | #define GCC_LPASS_RESTART 75 | ||
| 93 | #define GCC_WCSS_RESTART 76 | ||
| 94 | #define GCC_VENUS_RESTART 77 | ||
| 95 | |||
| 96 | #endif | ||
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h new file mode 100644 index 000000000000..ba36ec680118 --- /dev/null +++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H | ||
| 15 | #define _DT_BINDINGS_RESET_MSM_MMCC_8960_H | ||
| 16 | |||
| 17 | #define VPE_AXI_RESET 0 | ||
| 18 | #define IJPEG_AXI_RESET 1 | ||
| 19 | #define MPD_AXI_RESET 2 | ||
| 20 | #define VFE_AXI_RESET 3 | ||
| 21 | #define SP_AXI_RESET 4 | ||
| 22 | #define VCODEC_AXI_RESET 5 | ||
| 23 | #define ROT_AXI_RESET 6 | ||
| 24 | #define VCODEC_AXI_A_RESET 7 | ||
| 25 | #define VCODEC_AXI_B_RESET 8 | ||
| 26 | #define FAB_S3_AXI_RESET 9 | ||
| 27 | #define FAB_S2_AXI_RESET 10 | ||
| 28 | #define FAB_S1_AXI_RESET 11 | ||
| 29 | #define FAB_S0_AXI_RESET 12 | ||
| 30 | #define SMMU_GFX3D_ABH_RESET 13 | ||
| 31 | #define SMMU_VPE_AHB_RESET 14 | ||
| 32 | #define SMMU_VFE_AHB_RESET 15 | ||
| 33 | #define SMMU_ROT_AHB_RESET 16 | ||
| 34 | #define SMMU_VCODEC_B_AHB_RESET 17 | ||
| 35 | #define SMMU_VCODEC_A_AHB_RESET 18 | ||
| 36 | #define SMMU_MDP1_AHB_RESET 19 | ||
| 37 | #define SMMU_MDP0_AHB_RESET 20 | ||
| 38 | #define SMMU_JPEGD_AHB_RESET 21 | ||
| 39 | #define SMMU_IJPEG_AHB_RESET 22 | ||
| 40 | #define SMMU_GFX2D0_AHB_RESET 23 | ||
| 41 | #define SMMU_GFX2D1_AHB_RESET 24 | ||
| 42 | #define APU_AHB_RESET 25 | ||
| 43 | #define CSI_AHB_RESET 26 | ||
| 44 | #define TV_ENC_AHB_RESET 27 | ||
| 45 | #define VPE_AHB_RESET 28 | ||
| 46 | #define FABRIC_AHB_RESET 29 | ||
| 47 | #define GFX2D0_AHB_RESET 30 | ||
| 48 | #define GFX2D1_AHB_RESET 31 | ||
| 49 | #define GFX3D_AHB_RESET 32 | ||
| 50 | #define HDMI_AHB_RESET 33 | ||
| 51 | #define MSSS_IMEM_AHB_RESET 34 | ||
| 52 | #define IJPEG_AHB_RESET 35 | ||
| 53 | #define DSI_M_AHB_RESET 36 | ||
| 54 | #define DSI_S_AHB_RESET 37 | ||
| 55 | #define JPEGD_AHB_RESET 38 | ||
| 56 | #define MDP_AHB_RESET 39 | ||
| 57 | #define ROT_AHB_RESET 40 | ||
| 58 | #define VCODEC_AHB_RESET 41 | ||
| 59 | #define VFE_AHB_RESET 42 | ||
| 60 | #define DSI2_M_AHB_RESET 43 | ||
| 61 | #define DSI2_S_AHB_RESET 44 | ||
| 62 | #define CSIPHY2_RESET 45 | ||
| 63 | #define CSI_PIX1_RESET 46 | ||
| 64 | #define CSIPHY0_RESET 47 | ||
| 65 | #define CSIPHY1_RESET 48 | ||
| 66 | #define DSI2_RESET 49 | ||
| 67 | #define VFE_CSI_RESET 50 | ||
| 68 | #define MDP_RESET 51 | ||
| 69 | #define AMP_RESET 52 | ||
| 70 | #define JPEGD_RESET 53 | ||
| 71 | #define CSI1_RESET 54 | ||
| 72 | #define VPE_RESET 55 | ||
| 73 | #define MMSS_FABRIC_RESET 56 | ||
| 74 | #define VFE_RESET 57 | ||
| 75 | #define GFX2D0_RESET 58 | ||
| 76 | #define GFX2D1_RESET 59 | ||
| 77 | #define GFX3D_RESET 60 | ||
| 78 | #define HDMI_RESET 61 | ||
| 79 | #define MMSS_IMEM_RESET 62 | ||
| 80 | #define IJPEG_RESET 63 | ||
| 81 | #define CSI0_RESET 64 | ||
| 82 | #define DSI_RESET 65 | ||
| 83 | #define VCODEC_RESET 66 | ||
| 84 | #define MDP_TV_RESET 67 | ||
| 85 | #define MDP_VSYNC_RESET 68 | ||
| 86 | #define ROT_RESET 69 | ||
| 87 | #define TV_HDMI_RESET 70 | ||
| 88 | #define TV_ENC_RESET 71 | ||
| 89 | #define CSI2_RESET 72 | ||
| 90 | #define CSI_RDI1_RESET 73 | ||
| 91 | #define CSI_RDI2_RESET 74 | ||
| 92 | |||
| 93 | #endif | ||
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/include/dt-bindings/reset/qcom,mmcc-msm8974.h new file mode 100644 index 000000000000..da3ec37f1b1e --- /dev/null +++ b/include/dt-bindings/reset/qcom,mmcc-msm8974.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H | ||
| 15 | #define _DT_BINDINGS_RESET_MSM_MMCC_8974_H | ||
| 16 | |||
| 17 | #define SPDM_RESET 0 | ||
| 18 | #define SPDM_RM_RESET 1 | ||
| 19 | #define VENUS0_RESET 2 | ||
| 20 | #define MDSS_RESET 3 | ||
| 21 | #define CAMSS_PHY0_RESET 4 | ||
| 22 | #define CAMSS_PHY1_RESET 5 | ||
| 23 | #define CAMSS_PHY2_RESET 6 | ||
| 24 | #define CAMSS_CSI0_RESET 7 | ||
| 25 | #define CAMSS_CSI0PHY_RESET 8 | ||
| 26 | #define CAMSS_CSI0RDI_RESET 9 | ||
| 27 | #define CAMSS_CSI0PIX_RESET 10 | ||
| 28 | #define CAMSS_CSI1_RESET 11 | ||
| 29 | #define CAMSS_CSI1PHY_RESET 12 | ||
| 30 | #define CAMSS_CSI1RDI_RESET 13 | ||
| 31 | #define CAMSS_CSI1PIX_RESET 14 | ||
| 32 | #define CAMSS_CSI2_RESET 15 | ||
| 33 | #define CAMSS_CSI2PHY_RESET 16 | ||
| 34 | #define CAMSS_CSI2RDI_RESET 17 | ||
| 35 | #define CAMSS_CSI2PIX_RESET 18 | ||
| 36 | #define CAMSS_CSI3_RESET 19 | ||
| 37 | #define CAMSS_CSI3PHY_RESET 20 | ||
| 38 | #define CAMSS_CSI3RDI_RESET 21 | ||
| 39 | #define CAMSS_CSI3PIX_RESET 22 | ||
| 40 | #define CAMSS_ISPIF_RESET 23 | ||
| 41 | #define CAMSS_CCI_RESET 24 | ||
| 42 | #define CAMSS_MCLK0_RESET 25 | ||
| 43 | #define CAMSS_MCLK1_RESET 26 | ||
| 44 | #define CAMSS_MCLK2_RESET 27 | ||
| 45 | #define CAMSS_MCLK3_RESET 28 | ||
| 46 | #define CAMSS_GP0_RESET 29 | ||
| 47 | #define CAMSS_GP1_RESET 30 | ||
| 48 | #define CAMSS_TOP_RESET 31 | ||
| 49 | #define CAMSS_MICRO_RESET 32 | ||
| 50 | #define CAMSS_JPEG_RESET 33 | ||
| 51 | #define CAMSS_VFE_RESET 34 | ||
| 52 | #define CAMSS_CSI_VFE0_RESET 35 | ||
| 53 | #define CAMSS_CSI_VFE1_RESET 36 | ||
| 54 | #define OXILI_RESET 37 | ||
| 55 | #define OXILICX_RESET 38 | ||
| 56 | #define OCMEMCX_RESET 39 | ||
| 57 | #define MMSS_RBCRP_RESET 40 | ||
| 58 | #define MMSSNOCAHB_RESET 41 | ||
| 59 | #define MMSSNOCAXI_RESET 42 | ||
| 60 | #define OCMEMNOC_RESET 43 | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h new file mode 100644 index 000000000000..59822a995858 --- /dev/null +++ b/include/dt-bindings/thermal/thermal.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* | ||
| 2 | * This header provides constants for most thermal bindings. | ||
| 3 | * | ||
| 4 | * Copyright (C) 2013 Texas Instruments | ||
| 5 | * Eduardo Valentin <eduardo.valentin@ti.com> | ||
| 6 | * | ||
| 7 | * GPLv2 only | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _DT_BINDINGS_THERMAL_THERMAL_H | ||
| 11 | #define _DT_BINDINGS_THERMAL_THERMAL_H | ||
| 12 | |||
| 13 | /* On cooling devices upper and lower limits */ | ||
| 14 | #define THERMAL_NO_LIMIT (-1UL) | ||
| 15 | |||
| 16 | #endif | ||
| 17 | |||