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-rw-r--r--include/dt-bindings/arm/ux500_pm_domains.h15
-rw-r--r--include/dt-bindings/clock/imx5-clock.h5
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h8
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-apq8084.h2
-rw-r--r--include/dt-bindings/clock/r8a7740-clock.h1
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h14
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h11
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h9
-rw-r--r--include/dt-bindings/clock/stih407-clks.h86
-rw-r--r--include/dt-bindings/clock/stih410-clks.h25
-rw-r--r--include/dt-bindings/clock/tegra114-car.h2
-rw-r--r--include/dt-bindings/clock/tegra124-car.h2
-rw-r--r--include/dt-bindings/clock/tegra20-car.h2
-rw-r--r--include/dt-bindings/clock/vf610-clock.h39
-rw-r--r--include/dt-bindings/memory/tegra114-mc.h25
-rw-r--r--include/dt-bindings/memory/tegra124-mc.h31
-rw-r--r--include/dt-bindings/memory/tegra30-mc.h24
-rw-r--r--include/dt-bindings/pinctrl/dra.h4
-rw-r--r--include/dt-bindings/regulator/maxim,max77802.h18
-rw-r--r--include/dt-bindings/reset-controller/stih407-resets.h61
20 files changed, 363 insertions, 21 deletions
diff --git a/include/dt-bindings/arm/ux500_pm_domains.h b/include/dt-bindings/arm/ux500_pm_domains.h
new file mode 100644
index 000000000000..398a6c0288d1
--- /dev/null
+++ b/include/dt-bindings/arm/ux500_pm_domains.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) 2014 Linaro Ltd.
3 *
4 * Author: Ulf Hansson <ulf.hansson@linaro.org>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
8#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
9
10#define DOMAIN_VAPE 0
11
12/* Number of PM domains. */
13#define NR_DOMAINS (DOMAIN_VAPE + 1)
14
15#endif
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 5f2667ecd98e..f4b7478e23c8 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -198,6 +198,9 @@
198#define IMX5_CLK_OCRAM 186 198#define IMX5_CLK_OCRAM 186
199#define IMX5_CLK_SAHARA_IPG_GATE 187 199#define IMX5_CLK_SAHARA_IPG_GATE 187
200#define IMX5_CLK_SATA_REF 188 200#define IMX5_CLK_SATA_REF 188
201#define IMX5_CLK_END 189 201#define IMX5_CLK_STEP_SEL 189
202#define IMX5_CLK_CPU_PODF_SEL 190
203#define IMX5_CLK_ARM 191
204#define IMX5_CLK_END 192
202 205
203#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 206#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index ddaef8620b2c..b690cdba163b 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -62,8 +62,8 @@
62#define IMX6QDL_CLK_USDHC3_SEL 50 62#define IMX6QDL_CLK_USDHC3_SEL 50
63#define IMX6QDL_CLK_USDHC4_SEL 51 63#define IMX6QDL_CLK_USDHC4_SEL 51
64#define IMX6QDL_CLK_ENFC_SEL 52 64#define IMX6QDL_CLK_ENFC_SEL 52
65#define IMX6QDL_CLK_EMI_SEL 53 65#define IMX6QDL_CLK_EIM_SEL 53
66#define IMX6QDL_CLK_EMI_SLOW_SEL 54 66#define IMX6QDL_CLK_EIM_SLOW_SEL 54
67#define IMX6QDL_CLK_VDO_AXI_SEL 55 67#define IMX6QDL_CLK_VDO_AXI_SEL 55
68#define IMX6QDL_CLK_VPU_AXI_SEL 56 68#define IMX6QDL_CLK_VPU_AXI_SEL 56
69#define IMX6QDL_CLK_CKO1_SEL 57 69#define IMX6QDL_CLK_CKO1_SEL 57
@@ -106,8 +106,8 @@
106#define IMX6QDL_CLK_USDHC4_PODF 94 106#define IMX6QDL_CLK_USDHC4_PODF 94
107#define IMX6QDL_CLK_ENFC_PRED 95 107#define IMX6QDL_CLK_ENFC_PRED 95
108#define IMX6QDL_CLK_ENFC_PODF 96 108#define IMX6QDL_CLK_ENFC_PODF 96
109#define IMX6QDL_CLK_EMI_PODF 97 109#define IMX6QDL_CLK_EIM_PODF 97
110#define IMX6QDL_CLK_EMI_SLOW_PODF 98 110#define IMX6QDL_CLK_EIM_SLOW_PODF 98
111#define IMX6QDL_CLK_VPU_AXI_PODF 99 111#define IMX6QDL_CLK_VPU_AXI_PODF 99
112#define IMX6QDL_CLK_CKO1_PODF 100 112#define IMX6QDL_CLK_CKO1_PODF 100
113#define IMX6QDL_CLK_AXI 101 113#define IMX6QDL_CLK_AXI 101
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
index a929f86d0ddd..d72b5b35f15e 100644
--- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -60,7 +60,7 @@
60#define ESC1_CLK_SRC 43 60#define ESC1_CLK_SRC 43
61#define HDMI_CLK_SRC 44 61#define HDMI_CLK_SRC 44
62#define VSYNC_CLK_SRC 45 62#define VSYNC_CLK_SRC 45
63#define RBCPR_CLK_SRC 46 63#define MMSS_RBCPR_CLK_SRC 46
64#define RBBMTIMER_CLK_SRC 47 64#define RBBMTIMER_CLK_SRC 47
65#define MAPLE_CLK_SRC 48 65#define MAPLE_CLK_SRC 48
66#define VDP_CLK_SRC 49 66#define VDP_CLK_SRC 49
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
index f6b4b0fe7a43..476135da0f23 100644
--- a/include/dt-bindings/clock/r8a7740-clock.h
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -40,6 +40,7 @@
40 40
41/* MSTP2 */ 41/* MSTP2 */
42#define R8A7740_CLK_SCIFA6 30 42#define R8A7740_CLK_SCIFA6 30
43#define R8A7740_CLK_INTCA 29
43#define R8A7740_CLK_SCIFA7 22 44#define R8A7740_CLK_SCIFA7 22
44#define R8A7740_CLK_DMAC1 18 45#define R8A7740_CLK_DMAC1 18
45#define R8A7740_CLK_DMAC2 17 46#define R8A7740_CLK_DMAC2 17
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 8ea7ab0346ad..c27b3b5133b9 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,8 +26,18 @@
26#define R8A7790_CLK_MSIOF0 0 26#define R8A7790_CLK_MSIOF0 0
27 27
28/* MSTP1 */ 28/* MSTP1 */
29#define R8A7790_CLK_JPU 6 29#define R8A7790_CLK_VCP1 0
30#define R8A7790_CLK_VCP0 1
31#define R8A7790_CLK_VPC1 2
32#define R8A7790_CLK_VPC0 3
33#define R8A7790_CLK_JPU 6
34#define R8A7790_CLK_SSP1 9
30#define R8A7790_CLK_TMU1 11 35#define R8A7790_CLK_TMU1 11
36#define R8A7790_CLK_3DG 12
37#define R8A7790_CLK_2DDMAC 15
38#define R8A7790_CLK_FDP1_2 17
39#define R8A7790_CLK_FDP1_1 18
40#define R8A7790_CLK_FDP1_0 19
31#define R8A7790_CLK_TMU3 21 41#define R8A7790_CLK_TMU3 21
32#define R8A7790_CLK_TMU2 22 42#define R8A7790_CLK_TMU2 22
33#define R8A7790_CLK_CMT0 24 43#define R8A7790_CLK_CMT0 24
@@ -68,6 +78,8 @@
68#define R8A7790_CLK_USBDMAC1 31 78#define R8A7790_CLK_USBDMAC1 31
69 79
70/* MSTP5 */ 80/* MSTP5 */
81#define R8A7790_CLK_AUDIO_DMAC1 1
82#define R8A7790_CLK_AUDIO_DMAC0 2
71#define R8A7790_CLK_THERMAL 22 83#define R8A7790_CLK_THERMAL 22
72#define R8A7790_CLK_PWM 23 84#define R8A7790_CLK_PWM 23
73 85
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index 58c3f49d068c..3ea2bbc0da3f 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -25,8 +25,15 @@
25#define R8A7791_CLK_MSIOF0 0 25#define R8A7791_CLK_MSIOF0 0
26 26
27/* MSTP1 */ 27/* MSTP1 */
28#define R8A7791_CLK_JPU 6 28#define R8A7791_CLK_VCP0 1
29#define R8A7791_CLK_VPC0 3
30#define R8A7791_CLK_JPU 6
31#define R8A7791_CLK_SSP1 9
29#define R8A7791_CLK_TMU1 11 32#define R8A7791_CLK_TMU1 11
33#define R8A7791_CLK_3DG 12
34#define R8A7791_CLK_2DDMAC 15
35#define R8A7791_CLK_FDP1_1 18
36#define R8A7791_CLK_FDP1_0 19
30#define R8A7791_CLK_TMU3 21 37#define R8A7791_CLK_TMU3 21
31#define R8A7791_CLK_TMU2 22 38#define R8A7791_CLK_TMU2 22
32#define R8A7791_CLK_CMT0 24 39#define R8A7791_CLK_CMT0 24
@@ -62,6 +69,8 @@
62#define R8A7791_CLK_USBDMAC1 31 69#define R8A7791_CLK_USBDMAC1 31
63 70
64/* MSTP5 */ 71/* MSTP5 */
72#define R8A7791_CLK_AUDIO_DMAC1 1
73#define R8A7791_CLK_AUDIO_DMAC0 2
65#define R8A7791_CLK_THERMAL 22 74#define R8A7791_CLK_THERMAL 22
66#define R8A7791_CLK_PWM 23 75#define R8A7791_CLK_PWM 23
67 76
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 9ac1043e25bc..aa9c286e60c0 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -26,11 +26,18 @@
26#define R8A7794_CLK_MSIOF0 0 26#define R8A7794_CLK_MSIOF0 0
27 27
28/* MSTP1 */ 28/* MSTP1 */
29#define R8A7794_CLK_VCP0 1
30#define R8A7794_CLK_VPC0 3
29#define R8A7794_CLK_TMU1 11 31#define R8A7794_CLK_TMU1 11
32#define R8A7794_CLK_3DG 12
33#define R8A7794_CLK_2DDMAC 15
34#define R8A7794_CLK_FDP1_0 19
30#define R8A7794_CLK_TMU3 21 35#define R8A7794_CLK_TMU3 21
31#define R8A7794_CLK_TMU2 22 36#define R8A7794_CLK_TMU2 22
32#define R8A7794_CLK_CMT0 24 37#define R8A7794_CLK_CMT0 24
33#define R8A7794_CLK_TMU0 25 38#define R8A7794_CLK_TMU0 25
39#define R8A7794_CLK_VSP1_DU0 28
40#define R8A7794_CLK_VSP1_S 31
34 41
35/* MSTP2 */ 42/* MSTP2 */
36#define R8A7794_CLK_SCIFA2 2 43#define R8A7794_CLK_SCIFA2 2
@@ -61,6 +68,8 @@
61#define R8A7794_CLK_SCIF0 21 68#define R8A7794_CLK_SCIF0 21
62 69
63/* MSTP8 */ 70/* MSTP8 */
71#define R8A7794_CLK_VIN1 10
72#define R8A7794_CLK_VIN0 11
64#define R8A7794_CLK_ETHER 13 73#define R8A7794_CLK_ETHER 13
65 74
66/* MSTP9 */ 75/* MSTP9 */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000000..7af2b717b3b2
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,86 @@
1/*
2 * This header provides constants clk index STMicroelectronics
3 * STiH407 SoC.
4 */
5#ifndef _DT_BINDINGS_CLK_STIH407
6#define _DT_BINDINGS_CLK_STIH407
7
8/* CLOCKGEN C0 */
9#define CLK_ICN_GPU 0
10#define CLK_FDMA 1
11#define CLK_NAND 2
12#define CLK_HVA 3
13#define CLK_PROC_STFE 4
14#define CLK_PROC_TP 5
15#define CLK_RX_ICN_DMU 6
16#define CLK_RX_ICN_DISP_0 6
17#define CLK_RX_ICN_DISP_1 6
18#define CLK_RX_ICN_HVA 7
19#define CLK_RX_ICN_TS 7
20#define CLK_ICN_CPU 8
21#define CLK_TX_ICN_DMU 9
22#define CLK_TX_ICN_HVA 9
23#define CLK_TX_ICN_TS 9
24#define CLK_ICN_COMPO 9
25#define CLK_MMC_0 10
26#define CLK_MMC_1 11
27#define CLK_JPEGDEC 12
28#define CLK_ICN_REG 13
29#define CLK_TRACE_A9 13
30#define CLK_PTI_STM 13
31#define CLK_EXT2F_A9 13
32#define CLK_IC_BDISP_0 14
33#define CLK_IC_BDISP_1 15
34#define CLK_PP_DMU 16
35#define CLK_VID_DMU 17
36#define CLK_DSS_LPC 18
37#define CLK_ST231_AUD_0 19
38#define CLK_ST231_GP_0 19
39#define CLK_ST231_GP_1 20
40#define CLK_ST231_DMU 21
41#define CLK_ICN_LMI 22
42#define CLK_TX_ICN_DISP_0 23
43#define CLK_TX_ICN_DISP_1 23
44#define CLK_ICN_SBC 24
45#define CLK_STFE_FRC2 25
46#define CLK_ETH_PHY 26
47#define CLK_ETH_REF_PHYCLK 27
48#define CLK_FLASH_PROMIP 28
49#define CLK_MAIN_DISP 29
50#define CLK_AUX_DISP 30
51#define CLK_COMPO_DVP 31
52
53/* CLOCKGEN D0 */
54#define CLK_PCM_0 0
55#define CLK_PCM_1 1
56#define CLK_PCM_2 2
57#define CLK_SPDIFF 3
58
59/* CLOCKGEN D2 */
60#define CLK_PIX_MAIN_DISP 0
61#define CLK_PIX_PIP 1
62#define CLK_PIX_GDP1 2
63#define CLK_PIX_GDP2 3
64#define CLK_PIX_GDP3 4
65#define CLK_PIX_GDP4 5
66#define CLK_PIX_AUX_DISP 6
67#define CLK_DENC 7
68#define CLK_PIX_HDDAC 8
69#define CLK_HDDAC 9
70#define CLK_SDDAC 10
71#define CLK_PIX_DVO 11
72#define CLK_DVO 12
73#define CLK_PIX_HDMI 13
74#define CLK_TMDS_HDMI 14
75#define CLK_REF_HDMIPHY 15
76
77/* CLOCKGEN D3 */
78#define CLK_STFE_FRC1 0
79#define CLK_TSOUT_0 1
80#define CLK_TSOUT_1 2
81#define CLK_MCHI 3
82#define CLK_VSENS_COMPO 4
83#define CLK_FRC1_REMOTE 5
84#define CLK_LPC_0 6
85#define CLK_LPC_1 7
86#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 000000000000..2097a4bbe155
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
1/*
2 * This header provides constants clk index STMicroelectronics
3 * STiH410 SoC.
4 */
5#ifndef _DT_BINDINGS_CLK_STIH410
6#define _DT_BINDINGS_CLK_STIH410
7
8#include "stih407-clks.h"
9
10/* STiH410 introduces new clock outputs compared to STiH407 */
11
12/* CLOCKGEN C0 */
13#define CLK_TX_ICN_HADES 32
14#define CLK_RX_ICN_HADES 33
15#define CLK_ICN_REG_16 34
16#define CLK_PP_HADES 35
17#define CLK_CLUST_HADES 36
18#define CLK_HWPE_HADES 37
19#define CLK_FC_HADES 38
20
21/* CLOCKGEN D0 */
22#define CLK_PCMR10_MASTER 4
23#define CLK_USB2_PHY 5
24
25#endif
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index fc12621fb432..534c03f8ad72 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -49,7 +49,7 @@
49#define TEGRA114_CLK_I2S0 30 49#define TEGRA114_CLK_I2S0 30
50/* 31 */ 50/* 31 */
51 51
52/* 32 */ 52#define TEGRA114_CLK_MC 32
53/* 33 */ 53/* 33 */
54#define TEGRA114_CLK_APBDMA 34 54#define TEGRA114_CLK_APBDMA 34
55/* 35 */ 55/* 35 */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
index 6bac637fd635..af9bc9a3ddbc 100644
--- a/include/dt-bindings/clock/tegra124-car.h
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -48,7 +48,7 @@
48#define TEGRA124_CLK_I2S0 30 48#define TEGRA124_CLK_I2S0 30
49/* 31 */ 49/* 31 */
50 50
51/* 32 */ 51#define TEGRA124_CLK_MC 32
52/* 33 */ 52/* 33 */
53#define TEGRA124_CLK_APBDMA 34 53#define TEGRA124_CLK_APBDMA 34
54/* 35 */ 54/* 35 */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
index 9406207cfac8..04500b243a4d 100644
--- a/include/dt-bindings/clock/tegra20-car.h
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -49,7 +49,7 @@
49/* 30 */ 49/* 30 */
50#define TEGRA20_CLK_CACHE2 31 50#define TEGRA20_CLK_CACHE2 31
51 51
52#define TEGRA20_CLK_MEM 32 52#define TEGRA20_CLK_MC 32
53#define TEGRA20_CLK_AHBDMA 33 53#define TEGRA20_CLK_AHBDMA 33
54#define TEGRA20_CLK_APBDMA 34 54#define TEGRA20_CLK_APBDMA 34
55/* 35 */ 55/* 35 */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index d6b56b21539b..801c0ac50c47 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -21,24 +21,24 @@
21#define VF610_CLK_FASK_CLK_SEL 8 21#define VF610_CLK_FASK_CLK_SEL 8
22#define VF610_CLK_AUDIO_EXT 9 22#define VF610_CLK_AUDIO_EXT 9
23#define VF610_CLK_ENET_EXT 10 23#define VF610_CLK_ENET_EXT 10
24#define VF610_CLK_PLL1_MAIN 11 24#define VF610_CLK_PLL1_SYS 11
25#define VF610_CLK_PLL1_PFD1 12 25#define VF610_CLK_PLL1_PFD1 12
26#define VF610_CLK_PLL1_PFD2 13 26#define VF610_CLK_PLL1_PFD2 13
27#define VF610_CLK_PLL1_PFD3 14 27#define VF610_CLK_PLL1_PFD3 14
28#define VF610_CLK_PLL1_PFD4 15 28#define VF610_CLK_PLL1_PFD4 15
29#define VF610_CLK_PLL2_MAIN 16 29#define VF610_CLK_PLL2_BUS 16
30#define VF610_CLK_PLL2_PFD1 17 30#define VF610_CLK_PLL2_PFD1 17
31#define VF610_CLK_PLL2_PFD2 18 31#define VF610_CLK_PLL2_PFD2 18
32#define VF610_CLK_PLL2_PFD3 19 32#define VF610_CLK_PLL2_PFD3 19
33#define VF610_CLK_PLL2_PFD4 20 33#define VF610_CLK_PLL2_PFD4 20
34#define VF610_CLK_PLL3_MAIN 21 34#define VF610_CLK_PLL3_USB_OTG 21
35#define VF610_CLK_PLL3_PFD1 22 35#define VF610_CLK_PLL3_PFD1 22
36#define VF610_CLK_PLL3_PFD2 23 36#define VF610_CLK_PLL3_PFD2 23
37#define VF610_CLK_PLL3_PFD3 24 37#define VF610_CLK_PLL3_PFD3 24
38#define VF610_CLK_PLL3_PFD4 25 38#define VF610_CLK_PLL3_PFD4 25
39#define VF610_CLK_PLL4_MAIN 26 39#define VF610_CLK_PLL4_AUDIO 26
40#define VF610_CLK_PLL5_MAIN 27 40#define VF610_CLK_PLL5_ENET 27
41#define VF610_CLK_PLL6_MAIN 28 41#define VF610_CLK_PLL6_VIDEO 28
42#define VF610_CLK_PLL3_MAIN_DIV 29 42#define VF610_CLK_PLL3_MAIN_DIV 29
43#define VF610_CLK_PLL4_MAIN_DIV 30 43#define VF610_CLK_PLL4_MAIN_DIV 30
44#define VF610_CLK_PLL6_MAIN_DIV 31 44#define VF610_CLK_PLL6_MAIN_DIV 31
@@ -166,9 +166,32 @@
166#define VF610_CLK_DMAMUX3 153 166#define VF610_CLK_DMAMUX3 153
167#define VF610_CLK_FLEXCAN0_EN 154 167#define VF610_CLK_FLEXCAN0_EN 154
168#define VF610_CLK_FLEXCAN1_EN 155 168#define VF610_CLK_FLEXCAN1_EN 155
169#define VF610_CLK_PLL7_MAIN 156 169#define VF610_CLK_PLL7_USB_HOST 156
170#define VF610_CLK_USBPHY0 157 170#define VF610_CLK_USBPHY0 157
171#define VF610_CLK_USBPHY1 158 171#define VF610_CLK_USBPHY1 158
172#define VF610_CLK_END 159 172#define VF610_CLK_LVDS1_IN 159
173#define VF610_CLK_ANACLK1 160
174#define VF610_CLK_PLL1_BYPASS_SRC 161
175#define VF610_CLK_PLL2_BYPASS_SRC 162
176#define VF610_CLK_PLL3_BYPASS_SRC 163
177#define VF610_CLK_PLL4_BYPASS_SRC 164
178#define VF610_CLK_PLL5_BYPASS_SRC 165
179#define VF610_CLK_PLL6_BYPASS_SRC 166
180#define VF610_CLK_PLL7_BYPASS_SRC 167
181#define VF610_CLK_PLL1 168
182#define VF610_CLK_PLL2 169
183#define VF610_CLK_PLL3 170
184#define VF610_CLK_PLL4 171
185#define VF610_CLK_PLL5 172
186#define VF610_CLK_PLL6 173
187#define VF610_CLK_PLL7 174
188#define VF610_PLL1_BYPASS 175
189#define VF610_PLL2_BYPASS 176
190#define VF610_PLL3_BYPASS 177
191#define VF610_PLL4_BYPASS 178
192#define VF610_PLL5_BYPASS 179
193#define VF610_PLL6_BYPASS 180
194#define VF610_PLL7_BYPASS 181
195#define VF610_CLK_END 182
173 196
174#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 197#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
new file mode 100644
index 000000000000..8f48985a3139
--- /dev/null
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -0,0 +1,25 @@
1#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
2#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
3
4#define TEGRA_SWGROUP_PTC 0
5#define TEGRA_SWGROUP_DC 1
6#define TEGRA_SWGROUP_DCB 2
7#define TEGRA_SWGROUP_EPP 3
8#define TEGRA_SWGROUP_G2 4
9#define TEGRA_SWGROUP_AVPC 5
10#define TEGRA_SWGROUP_NV 6
11#define TEGRA_SWGROUP_HDA 7
12#define TEGRA_SWGROUP_HC 8
13#define TEGRA_SWGROUP_MSENC 9
14#define TEGRA_SWGROUP_PPCS 10
15#define TEGRA_SWGROUP_VDE 11
16#define TEGRA_SWGROUP_MPCORELP 12
17#define TEGRA_SWGROUP_MPCORE 13
18#define TEGRA_SWGROUP_VI 14
19#define TEGRA_SWGROUP_ISP 15
20#define TEGRA_SWGROUP_XUSB_HOST 16
21#define TEGRA_SWGROUP_XUSB_DEV 17
22#define TEGRA_SWGROUP_EMUCIF 18
23#define TEGRA_SWGROUP_TSEC 19
24
25#endif
diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h
new file mode 100644
index 000000000000..7d8ee798f34e
--- /dev/null
+++ b/include/dt-bindings/memory/tegra124-mc.h
@@ -0,0 +1,31 @@
1#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
2#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
3
4#define TEGRA_SWGROUP_PTC 0
5#define TEGRA_SWGROUP_DC 1
6#define TEGRA_SWGROUP_DCB 2
7#define TEGRA_SWGROUP_AFI 3
8#define TEGRA_SWGROUP_AVPC 4
9#define TEGRA_SWGROUP_HDA 5
10#define TEGRA_SWGROUP_HC 6
11#define TEGRA_SWGROUP_MSENC 7
12#define TEGRA_SWGROUP_PPCS 8
13#define TEGRA_SWGROUP_SATA 9
14#define TEGRA_SWGROUP_VDE 10
15#define TEGRA_SWGROUP_MPCORELP 11
16#define TEGRA_SWGROUP_MPCORE 12
17#define TEGRA_SWGROUP_ISP2 13
18#define TEGRA_SWGROUP_XUSB_HOST 14
19#define TEGRA_SWGROUP_XUSB_DEV 15
20#define TEGRA_SWGROUP_ISP2B 16
21#define TEGRA_SWGROUP_TSEC 17
22#define TEGRA_SWGROUP_A9AVP 18
23#define TEGRA_SWGROUP_GPU 19
24#define TEGRA_SWGROUP_SDMMC1A 20
25#define TEGRA_SWGROUP_SDMMC2A 21
26#define TEGRA_SWGROUP_SDMMC3A 22
27#define TEGRA_SWGROUP_SDMMC4A 23
28#define TEGRA_SWGROUP_VIC 24
29#define TEGRA_SWGROUP_VI 25
30
31#endif
diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h
new file mode 100644
index 000000000000..502beb03d777
--- /dev/null
+++ b/include/dt-bindings/memory/tegra30-mc.h
@@ -0,0 +1,24 @@
1#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
2#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
3
4#define TEGRA_SWGROUP_PTC 0
5#define TEGRA_SWGROUP_DC 1
6#define TEGRA_SWGROUP_DCB 2
7#define TEGRA_SWGROUP_EPP 3
8#define TEGRA_SWGROUP_G2 4
9#define TEGRA_SWGROUP_MPE 5
10#define TEGRA_SWGROUP_VI 6
11#define TEGRA_SWGROUP_AFI 7
12#define TEGRA_SWGROUP_AVPC 8
13#define TEGRA_SWGROUP_NV 9
14#define TEGRA_SWGROUP_NV2 10
15#define TEGRA_SWGROUP_HDA 11
16#define TEGRA_SWGROUP_HC 12
17#define TEGRA_SWGROUP_PPCS 13
18#define TEGRA_SWGROUP_SATA 14
19#define TEGRA_SWGROUP_VDE 15
20#define TEGRA_SWGROUP_MPCORELP 16
21#define TEGRA_SWGROUP_MPCORE 17
22#define TEGRA_SWGROUP_ISP 18
23
24#endif
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
index 3d33794e4f3e..7448edff4723 100644
--- a/include/dt-bindings/pinctrl/dra.h
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -40,8 +40,8 @@
40 40
41/* Active pin states */ 41/* Active pin states */
42#define PIN_OUTPUT (0 | PULL_DIS) 42#define PIN_OUTPUT (0 | PULL_DIS)
43#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) 43#define PIN_OUTPUT_PULLUP (PULL_UP)
44#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) 44#define PIN_OUTPUT_PULLDOWN (0)
45#define PIN_INPUT (INPUT_EN | PULL_DIS) 45#define PIN_INPUT (INPUT_EN | PULL_DIS)
46#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) 46#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
47#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) 47#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
new file mode 100644
index 000000000000..cf28631d7109
--- /dev/null
+++ b/include/dt-bindings/regulator/maxim,max77802.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 2014 Google, Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Device Tree binding constants for the Maxim 77802 PMIC regulators
9 */
10
11#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
12#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
13
14/* Regulator operating modes */
15#define MAX77802_OPMODE_LP 1
16#define MAX77802_OPMODE_NORMAL 3
17
18#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
diff --git a/include/dt-bindings/reset-controller/stih407-resets.h b/include/dt-bindings/reset-controller/stih407-resets.h
new file mode 100644
index 000000000000..02d4328fe479
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih407-resets.h
@@ -0,0 +1,61 @@
1/*
2 * This header provides constants for the reset controller
3 * based peripheral powerdown requests on the STMicroelectronics
4 * STiH407 SoC.
5 */
6#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
7#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
8
9/* Powerdown requests control 0 */
10#define STIH407_EMISS_POWERDOWN 0
11#define STIH407_NAND_POWERDOWN 1
12
13/* Synp GMAC PowerDown */
14#define STIH407_ETH1_POWERDOWN 2
15
16/* Powerdown requests control 1 */
17#define STIH407_USB3_POWERDOWN 3
18#define STIH407_USB2_PORT1_POWERDOWN 4
19#define STIH407_USB2_PORT0_POWERDOWN 5
20#define STIH407_PCIE1_POWERDOWN 6
21#define STIH407_PCIE0_POWERDOWN 7
22#define STIH407_SATA1_POWERDOWN 8
23#define STIH407_SATA0_POWERDOWN 9
24
25/* Reset defines */
26#define STIH407_ETH1_SOFTRESET 0
27#define STIH407_MMC1_SOFTRESET 1
28#define STIH407_PICOPHY_SOFTRESET 2
29#define STIH407_IRB_SOFTRESET 3
30#define STIH407_PCIE0_SOFTRESET 4
31#define STIH407_PCIE1_SOFTRESET 5
32#define STIH407_SATA0_SOFTRESET 6
33#define STIH407_SATA1_SOFTRESET 7
34#define STIH407_MIPHY0_SOFTRESET 8
35#define STIH407_MIPHY1_SOFTRESET 9
36#define STIH407_MIPHY2_SOFTRESET 10
37#define STIH407_SATA0_PWR_SOFTRESET 11
38#define STIH407_SATA1_PWR_SOFTRESET 12
39#define STIH407_DELTA_SOFTRESET 13
40#define STIH407_BLITTER_SOFTRESET 14
41#define STIH407_HDTVOUT_SOFTRESET 15
42#define STIH407_HDQVDP_SOFTRESET 16
43#define STIH407_VDP_AUX_SOFTRESET 17
44#define STIH407_COMPO_SOFTRESET 18
45#define STIH407_HDMI_TX_PHY_SOFTRESET 19
46#define STIH407_JPEG_DEC_SOFTRESET 20
47#define STIH407_VP8_DEC_SOFTRESET 21
48#define STIH407_GPU_SOFTRESET 22
49#define STIH407_HVA_SOFTRESET 23
50#define STIH407_ERAM_HVA_SOFTRESET 24
51#define STIH407_LPM_SOFTRESET 25
52#define STIH407_KEYSCAN_SOFTRESET 26
53#define STIH407_USB2_PORT0_SOFTRESET 27
54#define STIH407_USB2_PORT1_SOFTRESET 28
55
56/* Picophy reset defines */
57#define STIH407_PICOPHY0_RESET 0
58#define STIH407_PICOPHY1_RESET 1
59#define STIH407_PICOPHY2_RESET 2
60
61#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 05:18:21 -0500