4 files changed, 176 insertions, 4 deletions

diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index ddaef8620b2c..b690cdba163b 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -62,8 +62,8 @@
 #define IMX6QDL_CLK_USDHC3_SEL                  50
 #define IMX6QDL_CLK_USDHC4_SEL                  51
 #define IMX6QDL_CLK_ENFC_SEL                    52
-#define IMX6QDL_CLK_EMI_SEL                     53
-#define IMX6QDL_CLK_EMI_SLOW_SEL                54
+#define IMX6QDL_CLK_EIM_SEL                     53
+#define IMX6QDL_CLK_EIM_SLOW_SEL                54
 #define IMX6QDL_CLK_VDO_AXI_SEL                 55
 #define IMX6QDL_CLK_VPU_AXI_SEL                 56
 #define IMX6QDL_CLK_CKO1_SEL                    57
@@ -106,8 +106,8 @@
 #define IMX6QDL_CLK_USDHC4_PODF                 94
 #define IMX6QDL_CLK_ENFC_PRED                   95
 #define IMX6QDL_CLK_ENFC_PODF                   96
-#define IMX6QDL_CLK_EMI_PODF                    97
-#define IMX6QDL_CLK_EMI_SLOW_PODF               98
+#define IMX6QDL_CLK_EIM_PODF                    97
+#define IMX6QDL_CLK_EIM_SLOW_PODF               98
 #define IMX6QDL_CLK_VPU_AXI_PODF                99
 #define IMX6QDL_CLK_CKO1_PODF                   100
 #define IMX6QDL_CLK_AXI                         101
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000000..7af2b717b3b2
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,86 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU             0
+#define CLK_FDMA                1
+#define CLK_NAND                2
+#define CLK_HVA                 3
+#define CLK_PROC_STFE           4
+#define CLK_PROC_TP             5
+#define CLK_RX_ICN_DMU          6
+#define CLK_RX_ICN_DISP_0       6
+#define CLK_RX_ICN_DISP_1       6
+#define CLK_RX_ICN_HVA          7
+#define CLK_RX_ICN_TS           7
+#define CLK_ICN_CPU             8
+#define CLK_TX_ICN_DMU          9
+#define CLK_TX_ICN_HVA          9
+#define CLK_TX_ICN_TS           9
+#define CLK_ICN_COMPO           9
+#define CLK_MMC_0               10
+#define CLK_MMC_1               11
+#define CLK_JPEGDEC             12
+#define CLK_ICN_REG             13
+#define CLK_TRACE_A9            13
+#define CLK_PTI_STM             13
+#define CLK_EXT2F_A9            13
+#define CLK_IC_BDISP_0          14
+#define CLK_IC_BDISP_1          15
+#define CLK_PP_DMU              16
+#define CLK_VID_DMU             17
+#define CLK_DSS_LPC             18
+#define CLK_ST231_AUD_0         19
+#define CLK_ST231_GP_0          19
+#define CLK_ST231_GP_1          20
+#define CLK_ST231_DMU           21
+#define CLK_ICN_LMI             22
+#define CLK_TX_ICN_DISP_0       23
+#define CLK_TX_ICN_DISP_1       23
+#define CLK_ICN_SBC             24
+#define CLK_STFE_FRC2           25
+#define CLK_ETH_PHY             26
+#define CLK_ETH_REF_PHYCLK      27
+#define CLK_FLASH_PROMIP        28
+#define CLK_MAIN_DISP           29
+#define CLK_AUX_DISP            30
+#define CLK_COMPO_DVP           31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0               0
+#define CLK_PCM_1               1
+#define CLK_PCM_2               2
+#define CLK_SPDIFF              3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP       0
+#define CLK_PIX_PIP             1
+#define CLK_PIX_GDP1            2
+#define CLK_PIX_GDP2            3
+#define CLK_PIX_GDP3            4
+#define CLK_PIX_GDP4            5
+#define CLK_PIX_AUX_DISP        6
+#define CLK_DENC                7
+#define CLK_PIX_HDDAC           8
+#define CLK_HDDAC               9
+#define CLK_SDDAC               10
+#define CLK_PIX_DVO             11
+#define CLK_DVO                 12
+#define CLK_PIX_HDMI            13
+#define CLK_TMDS_HDMI           14
+#define CLK_REF_HDMIPHY         15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1           0
+#define CLK_TSOUT_0             1
+#define CLK_TSOUT_1             2
+#define CLK_MCHI                3
+#define CLK_VSENS_COMPO         4
+#define CLK_FRC1_REMOTE         5
+#define CLK_LPC_0               6
+#define CLK_LPC_1               7
+#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 000000000000..2097a4bbe155
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES        32
+#define CLK_RX_ICN_HADES        33
+#define CLK_ICN_REG_16          34
+#define CLK_PP_HADES            35
+#define CLK_CLUST_HADES         36
+#define CLK_HWPE_HADES          37
+#define CLK_FC_HADES            38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER       4
+#define CLK_USB2_PHY            5
+
+#endif
diff --git a/include/dt-bindings/reset-controller/stih407-resets.h b/include/dt-bindings/reset-controller/stih407-resets.h
new file mode 100644
index 000000000000..02d4328fe479
--- /dev/null
+++ b/include/dt-bindings/reset-controller/stih407-resets.h
@@ -0,0 +1,61 @@
+/*
+ * This header provides constants for the reset controller
+ * based peripheral powerdown requests on the STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
+#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
+
+/* Powerdown requests control 0 */
+#define STIH407_EMISS_POWERDOWN         0
+#define STIH407_NAND_POWERDOWN          1
+
+/* Synp GMAC PowerDown */
+#define STIH407_ETH1_POWERDOWN          2
+
+/* Powerdown requests control 1 */
+#define STIH407_USB3_POWERDOWN          3
+#define STIH407_USB2_PORT1_POWERDOWN    4
+#define STIH407_USB2_PORT0_POWERDOWN    5
+#define STIH407_PCIE1_POWERDOWN         6
+#define STIH407_PCIE0_POWERDOWN         7
+#define STIH407_SATA1_POWERDOWN         8
+#define STIH407_SATA0_POWERDOWN         9
+
+/* Reset defines */
+#define STIH407_ETH1_SOFTRESET          0
+#define STIH407_MMC1_SOFTRESET          1
+#define STIH407_PICOPHY_SOFTRESET       2
+#define STIH407_IRB_SOFTRESET           3
+#define STIH407_PCIE0_SOFTRESET         4
+#define STIH407_PCIE1_SOFTRESET         5
+#define STIH407_SATA0_SOFTRESET         6
+#define STIH407_SATA1_SOFTRESET         7
+#define STIH407_MIPHY0_SOFTRESET        8
+#define STIH407_MIPHY1_SOFTRESET        9
+#define STIH407_MIPHY2_SOFTRESET        10
+#define STIH407_SATA0_PWR_SOFTRESET     11
+#define STIH407_SATA1_PWR_SOFTRESET     12
+#define STIH407_DELTA_SOFTRESET         13
+#define STIH407_BLITTER_SOFTRESET       14
+#define STIH407_HDTVOUT_SOFTRESET       15
+#define STIH407_HDQVDP_SOFTRESET        16
+#define STIH407_VDP_AUX_SOFTRESET       17
+#define STIH407_COMPO_SOFTRESET         18
+#define STIH407_HDMI_TX_PHY_SOFTRESET   19
+#define STIH407_JPEG_DEC_SOFTRESET      20
+#define STIH407_VP8_DEC_SOFTRESET       21
+#define STIH407_GPU_SOFTRESET           22
+#define STIH407_HVA_SOFTRESET           23
+#define STIH407_ERAM_HVA_SOFTRESET      24
+#define STIH407_LPM_SOFTRESET           25
+#define STIH407_KEYSCAN_SOFTRESET       26
+#define STIH407_USB2_PORT0_SOFTRESET    27
+#define STIH407_USB2_PORT1_SOFTRESET    28
+
+/* Picophy reset defines */
+#define STIH407_PICOPHY0_RESET          0
+#define STIH407_PICOPHY1_RESET          1
+#define STIH407_PICOPHY2_RESET          2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */