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-rw-r--r--include/drm/Kbuild15
-rw-r--r--include/drm/drm.h830
-rw-r--r--include/drm/drm_fourcc.h135
-rw-r--r--include/drm/drm_mode.h463
-rw-r--r--include/drm/drm_sarea.h86
-rw-r--r--include/drm/exynos_drm.h174
-rw-r--r--include/drm/i810_drm.h281
-rw-r--r--include/drm/i915_drm.h920
-rw-r--r--include/drm/mga_drm.h419
-rw-r--r--include/drm/nouveau_drm.h138
-rw-r--r--include/drm/r128_drm.h326
-rw-r--r--include/drm/radeon_drm.h976
-rw-r--r--include/drm/savage_drm.h210
-rw-r--r--include/drm/sis_drm.h71
-rw-r--r--include/drm/via_drm.h281
-rw-r--r--include/drm/vmwgfx_drm.h790
16 files changed, 2 insertions, 6113 deletions
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
index 1e38a19d68f6..e69de29bb2d1 100644
--- a/include/drm/Kbuild
+++ b/include/drm/Kbuild
@@ -1,15 +0,0 @@
1header-y += drm.h
2header-y += drm_fourcc.h
3header-y += drm_mode.h
4header-y += drm_sarea.h
5header-y += exynos_drm.h
6header-y += i810_drm.h
7header-y += i915_drm.h
8header-y += mga_drm.h
9header-y += nouveau_drm.h
10header-y += r128_drm.h
11header-y += radeon_drm.h
12header-y += savage_drm.h
13header-y += sis_drm.h
14header-y += via_drm.h
15header-y += vmwgfx_drm.h
diff --git a/include/drm/drm.h b/include/drm/drm.h
deleted file mode 100644
index 1e3481edf062..000000000000
--- a/include/drm/drm.h
+++ /dev/null
@@ -1,830 +0,0 @@
1/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
11/*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
39#if defined(__linux__)
40
41#include <linux/types.h>
42#include <asm/ioctl.h>
43typedef unsigned int drm_handle_t;
44
45#else /* One of the BSDs */
46
47#include <sys/ioccom.h>
48#include <sys/types.h>
49typedef int8_t __s8;
50typedef uint8_t __u8;
51typedef int16_t __s16;
52typedef uint16_t __u16;
53typedef int32_t __s32;
54typedef uint32_t __u32;
55typedef int64_t __s64;
56typedef uint64_t __u64;
57typedef unsigned long drm_handle_t;
58
59#endif
60
61#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
62#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
63#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
64#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
65
66#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
67#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
68#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
69#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
70#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
71
72typedef unsigned int drm_context_t;
73typedef unsigned int drm_drawable_t;
74typedef unsigned int drm_magic_t;
75
76/**
77 * Cliprect.
78 *
79 * \warning: If you change this structure, make sure you change
80 * XF86DRIClipRectRec in the server as well
81 *
82 * \note KW: Actually it's illegal to change either for
83 * backwards-compatibility reasons.
84 */
85struct drm_clip_rect {
86 unsigned short x1;
87 unsigned short y1;
88 unsigned short x2;
89 unsigned short y2;
90};
91
92/**
93 * Drawable information.
94 */
95struct drm_drawable_info {
96 unsigned int num_rects;
97 struct drm_clip_rect *rects;
98};
99
100/**
101 * Texture region,
102 */
103struct drm_tex_region {
104 unsigned char next;
105 unsigned char prev;
106 unsigned char in_use;
107 unsigned char padding;
108 unsigned int age;
109};
110
111/**
112 * Hardware lock.
113 *
114 * The lock structure is a simple cache-line aligned integer. To avoid
115 * processor bus contention on a multiprocessor system, there should not be any
116 * other data stored in the same cache line.
117 */
118struct drm_hw_lock {
119 __volatile__ unsigned int lock; /**< lock variable */
120 char padding[60]; /**< Pad to cache line */
121};
122
123/**
124 * DRM_IOCTL_VERSION ioctl argument type.
125 *
126 * \sa drmGetVersion().
127 */
128struct drm_version {
129 int version_major; /**< Major version */
130 int version_minor; /**< Minor version */
131 int version_patchlevel; /**< Patch level */
132 size_t name_len; /**< Length of name buffer */
133 char __user *name; /**< Name of driver */
134 size_t date_len; /**< Length of date buffer */
135 char __user *date; /**< User-space buffer to hold date */
136 size_t desc_len; /**< Length of desc buffer */
137 char __user *desc; /**< User-space buffer to hold desc */
138};
139
140/**
141 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
142 *
143 * \sa drmGetBusid() and drmSetBusId().
144 */
145struct drm_unique {
146 size_t unique_len; /**< Length of unique */
147 char __user *unique; /**< Unique name for driver instantiation */
148};
149
150struct drm_list {
151 int count; /**< Length of user-space structures */
152 struct drm_version __user *version;
153};
154
155struct drm_block {
156 int unused;
157};
158
159/**
160 * DRM_IOCTL_CONTROL ioctl argument type.
161 *
162 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
163 */
164struct drm_control {
165 enum {
166 DRM_ADD_COMMAND,
167 DRM_RM_COMMAND,
168 DRM_INST_HANDLER,
169 DRM_UNINST_HANDLER
170 } func;
171 int irq;
172};
173
174/**
175 * Type of memory to map.
176 */
177enum drm_map_type {
178 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
179 _DRM_REGISTERS = 1, /**< no caching, no core dump */
180 _DRM_SHM = 2, /**< shared, cached */
181 _DRM_AGP = 3, /**< AGP/GART */
182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
184 _DRM_GEM = 6, /**< GEM object */
185};
186
187/**
188 * Memory mapping flags.
189 */
190enum drm_map_flags {
191 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
192 _DRM_READ_ONLY = 0x02,
193 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
194 _DRM_KERNEL = 0x08, /**< kernel requires access */
195 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
196 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
197 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
198 _DRM_DRIVER = 0x80 /**< Managed by driver */
199};
200
201struct drm_ctx_priv_map {
202 unsigned int ctx_id; /**< Context requesting private mapping */
203 void *handle; /**< Handle of map */
204};
205
206/**
207 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
208 * argument type.
209 *
210 * \sa drmAddMap().
211 */
212struct drm_map {
213 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
214 unsigned long size; /**< Requested physical size (bytes) */
215 enum drm_map_type type; /**< Type of memory to map */
216 enum drm_map_flags flags; /**< Flags */
217 void *handle; /**< User-space: "Handle" to pass to mmap() */
218 /**< Kernel-space: kernel-virtual address */
219 int mtrr; /**< MTRR slot used */
220 /* Private data */
221};
222
223/**
224 * DRM_IOCTL_GET_CLIENT ioctl argument type.
225 */
226struct drm_client {
227 int idx; /**< Which client desired? */
228 int auth; /**< Is client authenticated? */
229 unsigned long pid; /**< Process ID */
230 unsigned long uid; /**< User ID */
231 unsigned long magic; /**< Magic */
232 unsigned long iocs; /**< Ioctl count */
233};
234
235enum drm_stat_type {
236 _DRM_STAT_LOCK,
237 _DRM_STAT_OPENS,
238 _DRM_STAT_CLOSES,
239 _DRM_STAT_IOCTLS,
240 _DRM_STAT_LOCKS,
241 _DRM_STAT_UNLOCKS,
242 _DRM_STAT_VALUE, /**< Generic value */
243 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
244 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
245
246 _DRM_STAT_IRQ, /**< IRQ */
247 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
248 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
249 _DRM_STAT_DMA, /**< DMA */
250 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
251 _DRM_STAT_MISSED /**< Missed DMA opportunity */
252 /* Add to the *END* of the list */
253};
254
255/**
256 * DRM_IOCTL_GET_STATS ioctl argument type.
257 */
258struct drm_stats {
259 unsigned long count;
260 struct {
261 unsigned long value;
262 enum drm_stat_type type;
263 } data[15];
264};
265
266/**
267 * Hardware locking flags.
268 */
269enum drm_lock_flags {
270 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
271 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
272 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
273 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
274 /* These *HALT* flags aren't supported yet
275 -- they will be used to support the
276 full-screen DGA-like mode. */
277 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
278 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
279};
280
281/**
282 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
283 *
284 * \sa drmGetLock() and drmUnlock().
285 */
286struct drm_lock {
287 int context;
288 enum drm_lock_flags flags;
289};
290
291/**
292 * DMA flags
293 *
294 * \warning
295 * These values \e must match xf86drm.h.
296 *
297 * \sa drm_dma.
298 */
299enum drm_dma_flags {
300 /* Flags for DMA buffer dispatch */
301 _DRM_DMA_BLOCK = 0x01, /**<
302 * Block until buffer dispatched.
303 *
304 * \note The buffer may not yet have
305 * been processed by the hardware --
306 * getting a hardware lock with the
307 * hardware quiescent will ensure
308 * that the buffer has been
309 * processed.
310 */
311 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
312 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
313
314 /* Flags for DMA buffer request */
315 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
316 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
317 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
318};
319
320/**
321 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
322 *
323 * \sa drmAddBufs().
324 */
325struct drm_buf_desc {
326 int count; /**< Number of buffers of this size */
327 int size; /**< Size in bytes */
328 int low_mark; /**< Low water mark */
329 int high_mark; /**< High water mark */
330 enum {
331 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
332 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
333 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
334 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
335 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
336 } flags;
337 unsigned long agp_start; /**<
338 * Start address of where the AGP buffers are
339 * in the AGP aperture
340 */
341};
342
343/**
344 * DRM_IOCTL_INFO_BUFS ioctl argument type.
345 */
346struct drm_buf_info {
347 int count; /**< Entries in list */
348 struct drm_buf_desc __user *list;
349};
350
351/**
352 * DRM_IOCTL_FREE_BUFS ioctl argument type.
353 */
354struct drm_buf_free {
355 int count;
356 int __user *list;
357};
358
359/**
360 * Buffer information
361 *
362 * \sa drm_buf_map.
363 */
364struct drm_buf_pub {
365 int idx; /**< Index into the master buffer list */
366 int total; /**< Buffer size */
367 int used; /**< Amount of buffer in use (for DMA) */
368 void __user *address; /**< Address of buffer */
369};
370
371/**
372 * DRM_IOCTL_MAP_BUFS ioctl argument type.
373 */
374struct drm_buf_map {
375 int count; /**< Length of the buffer list */
376 void __user *virtual; /**< Mmap'd area in user-virtual */
377 struct drm_buf_pub __user *list; /**< Buffer information */
378};
379
380/**
381 * DRM_IOCTL_DMA ioctl argument type.
382 *
383 * Indices here refer to the offset into the buffer list in drm_buf_get.
384 *
385 * \sa drmDMA().
386 */
387struct drm_dma {
388 int context; /**< Context handle */
389 int send_count; /**< Number of buffers to send */
390 int __user *send_indices; /**< List of handles to buffers */
391 int __user *send_sizes; /**< Lengths of data to send */
392 enum drm_dma_flags flags; /**< Flags */
393 int request_count; /**< Number of buffers requested */
394 int request_size; /**< Desired size for buffers */
395 int __user *request_indices; /**< Buffer information */
396 int __user *request_sizes;
397 int granted_count; /**< Number of buffers granted */
398};
399
400enum drm_ctx_flags {
401 _DRM_CONTEXT_PRESERVED = 0x01,
402 _DRM_CONTEXT_2DONLY = 0x02
403};
404
405/**
406 * DRM_IOCTL_ADD_CTX ioctl argument type.
407 *
408 * \sa drmCreateContext() and drmDestroyContext().
409 */
410struct drm_ctx {
411 drm_context_t handle;
412 enum drm_ctx_flags flags;
413};
414
415/**
416 * DRM_IOCTL_RES_CTX ioctl argument type.
417 */
418struct drm_ctx_res {
419 int count;
420 struct drm_ctx __user *contexts;
421};
422
423/**
424 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
425 */
426struct drm_draw {
427 drm_drawable_t handle;
428};
429
430/**
431 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
432 */
433typedef enum {
434 DRM_DRAWABLE_CLIPRECTS,
435} drm_drawable_info_type_t;
436
437struct drm_update_draw {
438 drm_drawable_t handle;
439 unsigned int type;
440 unsigned int num;
441 unsigned long long data;
442};
443
444/**
445 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
446 */
447struct drm_auth {
448 drm_magic_t magic;
449};
450
451/**
452 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
453 *
454 * \sa drmGetInterruptFromBusID().
455 */
456struct drm_irq_busid {
457 int irq; /**< IRQ number */
458 int busnum; /**< bus number */
459 int devnum; /**< device number */
460 int funcnum; /**< function number */
461};
462
463enum drm_vblank_seq_type {
464 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
465 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
466 /* bits 1-6 are reserved for high crtcs */
467 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
468 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
469 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
470 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
471 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
472 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
473};
474#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
475
476#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
477#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
478 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
479
480struct drm_wait_vblank_request {
481 enum drm_vblank_seq_type type;
482 unsigned int sequence;
483 unsigned long signal;
484};
485
486struct drm_wait_vblank_reply {
487 enum drm_vblank_seq_type type;
488 unsigned int sequence;
489 long tval_sec;
490 long tval_usec;
491};
492
493/**
494 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
495 *
496 * \sa drmWaitVBlank().
497 */
498union drm_wait_vblank {
499 struct drm_wait_vblank_request request;
500 struct drm_wait_vblank_reply reply;
501};
502
503#define _DRM_PRE_MODESET 1
504#define _DRM_POST_MODESET 2
505
506/**
507 * DRM_IOCTL_MODESET_CTL ioctl argument type
508 *
509 * \sa drmModesetCtl().
510 */
511struct drm_modeset_ctl {
512 __u32 crtc;
513 __u32 cmd;
514};
515
516/**
517 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
518 *
519 * \sa drmAgpEnable().
520 */
521struct drm_agp_mode {
522 unsigned long mode; /**< AGP mode */
523};
524
525/**
526 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
527 *
528 * \sa drmAgpAlloc() and drmAgpFree().
529 */
530struct drm_agp_buffer {
531 unsigned long size; /**< In bytes -- will round to page boundary */
532 unsigned long handle; /**< Used for binding / unbinding */
533 unsigned long type; /**< Type of memory to allocate */
534 unsigned long physical; /**< Physical used by i810 */
535};
536
537/**
538 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
539 *
540 * \sa drmAgpBind() and drmAgpUnbind().
541 */
542struct drm_agp_binding {
543 unsigned long handle; /**< From drm_agp_buffer */
544 unsigned long offset; /**< In bytes -- will round to page boundary */
545};
546
547/**
548 * DRM_IOCTL_AGP_INFO ioctl argument type.
549 *
550 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
551 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
552 * drmAgpVendorId() and drmAgpDeviceId().
553 */
554struct drm_agp_info {
555 int agp_version_major;
556 int agp_version_minor;
557 unsigned long mode;
558 unsigned long aperture_base; /* physical address */
559 unsigned long aperture_size; /* bytes */
560 unsigned long memory_allowed; /* bytes */
561 unsigned long memory_used;
562
563 /* PCI information */
564 unsigned short id_vendor;
565 unsigned short id_device;
566};
567
568/**
569 * DRM_IOCTL_SG_ALLOC ioctl argument type.
570 */
571struct drm_scatter_gather {
572 unsigned long size; /**< In bytes -- will round to page boundary */
573 unsigned long handle; /**< Used for mapping / unmapping */
574};
575
576/**
577 * DRM_IOCTL_SET_VERSION ioctl argument type.
578 */
579struct drm_set_version {
580 int drm_di_major;
581 int drm_di_minor;
582 int drm_dd_major;
583 int drm_dd_minor;
584};
585
586/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
587struct drm_gem_close {
588 /** Handle of the object to be closed. */
589 __u32 handle;
590 __u32 pad;
591};
592
593/** DRM_IOCTL_GEM_FLINK ioctl argument type */
594struct drm_gem_flink {
595 /** Handle for the object being named */
596 __u32 handle;
597
598 /** Returned global name */
599 __u32 name;
600};
601
602/** DRM_IOCTL_GEM_OPEN ioctl argument type */
603struct drm_gem_open {
604 /** Name of object being opened */
605 __u32 name;
606
607 /** Returned handle for the object */
608 __u32 handle;
609
610 /** Returned size of the object */
611 __u64 size;
612};
613
614/** DRM_IOCTL_GET_CAP ioctl argument type */
615struct drm_get_cap {
616 __u64 capability;
617 __u64 value;
618};
619
620#define DRM_CLOEXEC O_CLOEXEC
621struct drm_prime_handle {
622 __u32 handle;
623
624 /** Flags.. only applicable for handle->fd */
625 __u32 flags;
626
627 /** Returned dmabuf file descriptor */
628 __s32 fd;
629};
630
631#include <drm/drm_mode.h>
632
633#define DRM_IOCTL_BASE 'd'
634#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
635#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
636#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
637#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
638
639#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
640#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
641#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
642#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
643#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
644#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
645#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
646#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
647#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
648#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
649#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
650#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
651#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
652
653#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
654#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
655#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
656#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
657#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
658#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
659#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
660#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
661#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
662#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
663#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
664
665#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
666
667#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
668#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
669
670#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
671#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
672
673#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
674#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
675#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
676#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
677#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
678#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
679#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
680#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
681#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
682#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
683#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
684#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
685#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
686
687#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
688#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
689
690#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
691#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
692#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
693#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
694#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
695#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
696#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
697#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
698
699#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
700#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
701
702#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
703
704#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
705
706#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
707#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
708#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
709#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
710#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
711#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
712#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
713#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
714#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
715#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
716
717#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
718#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
719#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
720#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
721#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
722#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
723#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
724#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
725
726#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
727#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
728#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
729#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
730#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
731#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
732#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
733#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
734#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
735
736/**
737 * Device specific ioctls should only be in their respective headers
738 * The device specific ioctl range is from 0x40 to 0x99.
739 * Generic IOCTLS restart at 0xA0.
740 *
741 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
742 * drmCommandReadWrite().
743 */
744#define DRM_COMMAND_BASE 0x40
745#define DRM_COMMAND_END 0xA0
746
747/**
748 * Header for events written back to userspace on the drm fd. The
749 * type defines the type of event, the length specifies the total
750 * length of the event (including the header), and user_data is
751 * typically a 64 bit value passed with the ioctl that triggered the
752 * event. A read on the drm fd will always only return complete
753 * events, that is, if for example the read buffer is 100 bytes, and
754 * there are two 64 byte events pending, only one will be returned.
755 *
756 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
757 * up are chipset specific.
758 */
759struct drm_event {
760 __u32 type;
761 __u32 length;
762};
763
764#define DRM_EVENT_VBLANK 0x01
765#define DRM_EVENT_FLIP_COMPLETE 0x02
766
767struct drm_event_vblank {
768 struct drm_event base;
769 __u64 user_data;
770 __u32 tv_sec;
771 __u32 tv_usec;
772 __u32 sequence;
773 __u32 reserved;
774};
775
776#define DRM_CAP_DUMB_BUFFER 0x1
777#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
778#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
779#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
780#define DRM_CAP_PRIME 0x5
781
782#define DRM_PRIME_CAP_IMPORT 0x1
783#define DRM_PRIME_CAP_EXPORT 0x2
784
785/* typedef area */
786#ifndef __KERNEL__
787typedef struct drm_clip_rect drm_clip_rect_t;
788typedef struct drm_drawable_info drm_drawable_info_t;
789typedef struct drm_tex_region drm_tex_region_t;
790typedef struct drm_hw_lock drm_hw_lock_t;
791typedef struct drm_version drm_version_t;
792typedef struct drm_unique drm_unique_t;
793typedef struct drm_list drm_list_t;
794typedef struct drm_block drm_block_t;
795typedef struct drm_control drm_control_t;
796typedef enum drm_map_type drm_map_type_t;
797typedef enum drm_map_flags drm_map_flags_t;
798typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
799typedef struct drm_map drm_map_t;
800typedef struct drm_client drm_client_t;
801typedef enum drm_stat_type drm_stat_type_t;
802typedef struct drm_stats drm_stats_t;
803typedef enum drm_lock_flags drm_lock_flags_t;
804typedef struct drm_lock drm_lock_t;
805typedef enum drm_dma_flags drm_dma_flags_t;
806typedef struct drm_buf_desc drm_buf_desc_t;
807typedef struct drm_buf_info drm_buf_info_t;
808typedef struct drm_buf_free drm_buf_free_t;
809typedef struct drm_buf_pub drm_buf_pub_t;
810typedef struct drm_buf_map drm_buf_map_t;
811typedef struct drm_dma drm_dma_t;
812typedef union drm_wait_vblank drm_wait_vblank_t;
813typedef struct drm_agp_mode drm_agp_mode_t;
814typedef enum drm_ctx_flags drm_ctx_flags_t;
815typedef struct drm_ctx drm_ctx_t;
816typedef struct drm_ctx_res drm_ctx_res_t;
817typedef struct drm_draw drm_draw_t;
818typedef struct drm_update_draw drm_update_draw_t;
819typedef struct drm_auth drm_auth_t;
820typedef struct drm_irq_busid drm_irq_busid_t;
821typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
822
823typedef struct drm_agp_buffer drm_agp_buffer_t;
824typedef struct drm_agp_binding drm_agp_binding_t;
825typedef struct drm_agp_info drm_agp_info_t;
826typedef struct drm_scatter_gather drm_scatter_gather_t;
827typedef struct drm_set_version drm_set_version_t;
828#endif
829
830#endif
diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h
deleted file mode 100644
index 646ae5f39f42..000000000000
--- a/include/drm/drm_fourcc.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef DRM_FOURCC_H
25#define DRM_FOURCC_H
26
27#include <linux/types.h>
28
29#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
30 ((__u32)(c) << 16) | ((__u32)(d) << 24))
31
32#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
33
34/* color index */
35#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
36
37/* 8 bpp RGB */
38#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
39#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
40
41/* 16 bpp RGB */
42#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
43#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
44#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
45#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
46
47#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
48#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
49#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
50#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
51
52#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
53#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
54#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
55#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
56
57#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
58#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
59#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
60#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
61
62#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
63#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
64
65/* 24 bpp RGB */
66#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
67#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
68
69/* 32 bpp RGB */
70#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
71#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
72#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
73#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
74
75#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
76#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
77#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
78#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
79
80#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
81#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
82#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
83#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
84
85#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
86#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
87#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
88#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
89
90/* packed YCbCr */
91#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
92#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
93#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
94#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
95
96#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
97
98/*
99 * 2 plane YCbCr
100 * index 0 = Y plane, [7:0] Y
101 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
102 * or
103 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
104 */
105#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
106#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
107#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
108#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
109#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
110#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
111
112/* special NV12 tiled format */
113#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */
114
115/*
116 * 3 plane YCbCr
117 * index 0: Y plane, [7:0] Y
118 * index 1: Cb plane, [7:0] Cb
119 * index 2: Cr plane, [7:0] Cr
120 * or
121 * index 1: Cr plane, [7:0] Cr
122 * index 2: Cb plane, [7:0] Cb
123 */
124#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
125#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
126#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
127#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
128#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
129#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
130#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
131#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
132#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
133#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
134
135#endif /* DRM_FOURCC_H */
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
deleted file mode 100644
index 3d6301b6ec16..000000000000
--- a/include/drm/drm_mode.h
+++ /dev/null
@@ -1,463 +0,0 @@
1/*
2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
30#include <linux/types.h>
31
32#define DRM_DISPLAY_INFO_LEN 32
33#define DRM_CONNECTOR_NAME_LEN 32
34#define DRM_DISPLAY_MODE_LEN 32
35#define DRM_PROP_NAME_LEN 32
36
37#define DRM_MODE_TYPE_BUILTIN (1<<0)
38#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
39#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
40#define DRM_MODE_TYPE_PREFERRED (1<<3)
41#define DRM_MODE_TYPE_DEFAULT (1<<4)
42#define DRM_MODE_TYPE_USERDEF (1<<5)
43#define DRM_MODE_TYPE_DRIVER (1<<6)
44
45/* Video mode flags */
46/* bit compatible with the xorg definitions. */
47#define DRM_MODE_FLAG_PHSYNC (1<<0)
48#define DRM_MODE_FLAG_NHSYNC (1<<1)
49#define DRM_MODE_FLAG_PVSYNC (1<<2)
50#define DRM_MODE_FLAG_NVSYNC (1<<3)
51#define DRM_MODE_FLAG_INTERLACE (1<<4)
52#define DRM_MODE_FLAG_DBLSCAN (1<<5)
53#define DRM_MODE_FLAG_CSYNC (1<<6)
54#define DRM_MODE_FLAG_PCSYNC (1<<7)
55#define DRM_MODE_FLAG_NCSYNC (1<<8)
56#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
57#define DRM_MODE_FLAG_BCAST (1<<10)
58#define DRM_MODE_FLAG_PIXMUX (1<<11)
59#define DRM_MODE_FLAG_DBLCLK (1<<12)
60#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
61
62/* DPMS flags */
63/* bit compatible with the xorg definitions. */
64#define DRM_MODE_DPMS_ON 0
65#define DRM_MODE_DPMS_STANDBY 1
66#define DRM_MODE_DPMS_SUSPEND 2
67#define DRM_MODE_DPMS_OFF 3
68
69/* Scaling mode options */
70#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
71 software can still scale) */
72#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
73#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
74#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
75
76/* Dithering mode options */
77#define DRM_MODE_DITHERING_OFF 0
78#define DRM_MODE_DITHERING_ON 1
79#define DRM_MODE_DITHERING_AUTO 2
80
81/* Dirty info options */
82#define DRM_MODE_DIRTY_OFF 0
83#define DRM_MODE_DIRTY_ON 1
84#define DRM_MODE_DIRTY_ANNOTATE 2
85
86struct drm_mode_modeinfo {
87 __u32 clock;
88 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
89 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
90
91 __u32 vrefresh;
92
93 __u32 flags;
94 __u32 type;
95 char name[DRM_DISPLAY_MODE_LEN];
96};
97
98struct drm_mode_card_res {
99 __u64 fb_id_ptr;
100 __u64 crtc_id_ptr;
101 __u64 connector_id_ptr;
102 __u64 encoder_id_ptr;
103 __u32 count_fbs;
104 __u32 count_crtcs;
105 __u32 count_connectors;
106 __u32 count_encoders;
107 __u32 min_width, max_width;
108 __u32 min_height, max_height;
109};
110
111struct drm_mode_crtc {
112 __u64 set_connectors_ptr;
113 __u32 count_connectors;
114
115 __u32 crtc_id; /**< Id */
116 __u32 fb_id; /**< Id of framebuffer */
117
118 __u32 x, y; /**< Position on the frameuffer */
119
120 __u32 gamma_size;
121 __u32 mode_valid;
122 struct drm_mode_modeinfo mode;
123};
124
125#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
126#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
127
128/* Planes blend with or override other bits on the CRTC */
129struct drm_mode_set_plane {
130 __u32 plane_id;
131 __u32 crtc_id;
132 __u32 fb_id; /* fb object contains surface format type */
133 __u32 flags; /* see above flags */
134
135 /* Signed dest location allows it to be partially off screen */
136 __s32 crtc_x, crtc_y;
137 __u32 crtc_w, crtc_h;
138
139 /* Source values are 16.16 fixed point */
140 __u32 src_x, src_y;
141 __u32 src_h, src_w;
142};
143
144struct drm_mode_get_plane {
145 __u32 plane_id;
146
147 __u32 crtc_id;
148 __u32 fb_id;
149
150 __u32 possible_crtcs;
151 __u32 gamma_size;
152
153 __u32 count_format_types;
154 __u64 format_type_ptr;
155};
156
157struct drm_mode_get_plane_res {
158 __u64 plane_id_ptr;
159 __u32 count_planes;
160};
161
162#define DRM_MODE_ENCODER_NONE 0
163#define DRM_MODE_ENCODER_DAC 1
164#define DRM_MODE_ENCODER_TMDS 2
165#define DRM_MODE_ENCODER_LVDS 3
166#define DRM_MODE_ENCODER_TVDAC 4
167#define DRM_MODE_ENCODER_VIRTUAL 5
168
169struct drm_mode_get_encoder {
170 __u32 encoder_id;
171 __u32 encoder_type;
172
173 __u32 crtc_id; /**< Id of crtc */
174
175 __u32 possible_crtcs;
176 __u32 possible_clones;
177};
178
179/* This is for connectors with multiple signal types. */
180/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
181#define DRM_MODE_SUBCONNECTOR_Automatic 0
182#define DRM_MODE_SUBCONNECTOR_Unknown 0
183#define DRM_MODE_SUBCONNECTOR_DVID 3
184#define DRM_MODE_SUBCONNECTOR_DVIA 4
185#define DRM_MODE_SUBCONNECTOR_Composite 5
186#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
187#define DRM_MODE_SUBCONNECTOR_Component 8
188#define DRM_MODE_SUBCONNECTOR_SCART 9
189
190#define DRM_MODE_CONNECTOR_Unknown 0
191#define DRM_MODE_CONNECTOR_VGA 1
192#define DRM_MODE_CONNECTOR_DVII 2
193#define DRM_MODE_CONNECTOR_DVID 3
194#define DRM_MODE_CONNECTOR_DVIA 4
195#define DRM_MODE_CONNECTOR_Composite 5
196#define DRM_MODE_CONNECTOR_SVIDEO 6
197#define DRM_MODE_CONNECTOR_LVDS 7
198#define DRM_MODE_CONNECTOR_Component 8
199#define DRM_MODE_CONNECTOR_9PinDIN 9
200#define DRM_MODE_CONNECTOR_DisplayPort 10
201#define DRM_MODE_CONNECTOR_HDMIA 11
202#define DRM_MODE_CONNECTOR_HDMIB 12
203#define DRM_MODE_CONNECTOR_TV 13
204#define DRM_MODE_CONNECTOR_eDP 14
205#define DRM_MODE_CONNECTOR_VIRTUAL 15
206
207struct drm_mode_get_connector {
208
209 __u64 encoders_ptr;
210 __u64 modes_ptr;
211 __u64 props_ptr;
212 __u64 prop_values_ptr;
213
214 __u32 count_modes;
215 __u32 count_props;
216 __u32 count_encoders;
217
218 __u32 encoder_id; /**< Current Encoder */
219 __u32 connector_id; /**< Id */
220 __u32 connector_type;
221 __u32 connector_type_id;
222
223 __u32 connection;
224 __u32 mm_width, mm_height; /**< HxW in millimeters */
225 __u32 subpixel;
226};
227
228#define DRM_MODE_PROP_PENDING (1<<0)
229#define DRM_MODE_PROP_RANGE (1<<1)
230#define DRM_MODE_PROP_IMMUTABLE (1<<2)
231#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
232#define DRM_MODE_PROP_BLOB (1<<4)
233#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
234
235struct drm_mode_property_enum {
236 __u64 value;
237 char name[DRM_PROP_NAME_LEN];
238};
239
240struct drm_mode_get_property {
241 __u64 values_ptr; /* values and blob lengths */
242 __u64 enum_blob_ptr; /* enum and blob id ptrs */
243
244 __u32 prop_id;
245 __u32 flags;
246 char name[DRM_PROP_NAME_LEN];
247
248 __u32 count_values;
249 __u32 count_enum_blobs;
250};
251
252struct drm_mode_connector_set_property {
253 __u64 value;
254 __u32 prop_id;
255 __u32 connector_id;
256};
257
258struct drm_mode_obj_get_properties {
259 __u64 props_ptr;
260 __u64 prop_values_ptr;
261 __u32 count_props;
262 __u32 obj_id;
263 __u32 obj_type;
264};
265
266struct drm_mode_obj_set_property {
267 __u64 value;
268 __u32 prop_id;
269 __u32 obj_id;
270 __u32 obj_type;
271};
272
273struct drm_mode_get_blob {
274 __u32 blob_id;
275 __u32 length;
276 __u64 data;
277};
278
279struct drm_mode_fb_cmd {
280 __u32 fb_id;
281 __u32 width, height;
282 __u32 pitch;
283 __u32 bpp;
284 __u32 depth;
285 /* driver specific handle */
286 __u32 handle;
287};
288
289#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
290
291struct drm_mode_fb_cmd2 {
292 __u32 fb_id;
293 __u32 width, height;
294 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
295 __u32 flags; /* see above flags */
296
297 /*
298 * In case of planar formats, this ioctl allows up to 4
299 * buffer objects with offets and pitches per plane.
300 * The pitch and offset order is dictated by the fourcc,
301 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
302 *
303 * YUV 4:2:0 image with a plane of 8 bit Y samples
304 * followed by an interleaved U/V plane containing
305 * 8 bit 2x2 subsampled colour difference samples.
306 *
307 * So it would consist of Y as offset[0] and UV as
308 * offeset[1]. Note that offset[0] will generally
309 * be 0.
310 */
311 __u32 handles[4];
312 __u32 pitches[4]; /* pitch for each plane */
313 __u32 offsets[4]; /* offset of each plane */
314};
315
316#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
317#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
318#define DRM_MODE_FB_DIRTY_FLAGS 0x03
319
320#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
321
322/*
323 * Mark a region of a framebuffer as dirty.
324 *
325 * Some hardware does not automatically update display contents
326 * as a hardware or software draw to a framebuffer. This ioctl
327 * allows userspace to tell the kernel and the hardware what
328 * regions of the framebuffer have changed.
329 *
330 * The kernel or hardware is free to update more then just the
331 * region specified by the clip rects. The kernel or hardware
332 * may also delay and/or coalesce several calls to dirty into a
333 * single update.
334 *
335 * Userspace may annotate the updates, the annotates are a
336 * promise made by the caller that the change is either a copy
337 * of pixels or a fill of a single color in the region specified.
338 *
339 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
340 * the number of updated regions are half of num_clips given,
341 * where the clip rects are paired in src and dst. The width and
342 * height of each one of the pairs must match.
343 *
344 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
345 * promises that the region specified of the clip rects is filled
346 * completely with a single color as given in the color argument.
347 */
348
349struct drm_mode_fb_dirty_cmd {
350 __u32 fb_id;
351 __u32 flags;
352 __u32 color;
353 __u32 num_clips;
354 __u64 clips_ptr;
355};
356
357struct drm_mode_mode_cmd {
358 __u32 connector_id;
359 struct drm_mode_modeinfo mode;
360};
361
362#define DRM_MODE_CURSOR_BO 0x01
363#define DRM_MODE_CURSOR_MOVE 0x02
364#define DRM_MODE_CURSOR_FLAGS 0x03
365
366/*
367 * depending on the value in flags different members are used.
368 *
369 * CURSOR_BO uses
370 * crtc
371 * width
372 * height
373 * handle - if 0 turns the cursor of
374 *
375 * CURSOR_MOVE uses
376 * crtc
377 * x
378 * y
379 */
380struct drm_mode_cursor {
381 __u32 flags;
382 __u32 crtc_id;
383 __s32 x;
384 __s32 y;
385 __u32 width;
386 __u32 height;
387 /* driver specific handle */
388 __u32 handle;
389};
390
391struct drm_mode_crtc_lut {
392 __u32 crtc_id;
393 __u32 gamma_size;
394
395 /* pointers to arrays */
396 __u64 red;
397 __u64 green;
398 __u64 blue;
399};
400
401#define DRM_MODE_PAGE_FLIP_EVENT 0x01
402#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
403
404/*
405 * Request a page flip on the specified crtc.
406 *
407 * This ioctl will ask KMS to schedule a page flip for the specified
408 * crtc. Once any pending rendering targeting the specified fb (as of
409 * ioctl time) has completed, the crtc will be reprogrammed to display
410 * that fb after the next vertical refresh. The ioctl returns
411 * immediately, but subsequent rendering to the current fb will block
412 * in the execbuffer ioctl until the page flip happens. If a page
413 * flip is already pending as the ioctl is called, EBUSY will be
414 * returned.
415 *
416 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
417 * request that drm sends back a vblank event (see drm.h: struct
418 * drm_event_vblank) when the page flip is done. The user_data field
419 * passed in with this ioctl will be returned as the user_data field
420 * in the vblank event struct.
421 *
422 * The reserved field must be zero until we figure out something
423 * clever to use it for.
424 */
425
426struct drm_mode_crtc_page_flip {
427 __u32 crtc_id;
428 __u32 fb_id;
429 __u32 flags;
430 __u32 reserved;
431 __u64 user_data;
432};
433
434/* create a dumb scanout buffer */
435struct drm_mode_create_dumb {
436 uint32_t height;
437 uint32_t width;
438 uint32_t bpp;
439 uint32_t flags;
440 /* handle, pitch, size will be returned */
441 uint32_t handle;
442 uint32_t pitch;
443 uint64_t size;
444};
445
446/* set up for mmap of a dumb scanout buffer */
447struct drm_mode_map_dumb {
448 /** Handle for the object being mapped. */
449 __u32 handle;
450 __u32 pad;
451 /**
452 * Fake offset to use for subsequent mmap call
453 *
454 * This is a fixed-size type for 32/64 compatibility.
455 */
456 __u64 offset;
457};
458
459struct drm_mode_destroy_dumb {
460 uint32_t handle;
461};
462
463#endif
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h
deleted file mode 100644
index 413a5642d49f..000000000000
--- a/include/drm/drm_sarea.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/**
2 * \file drm_sarea.h
3 * \brief SAREA definitions
4 *
5 * \author Michel Dänzer <michel@daenzer.net>
6 */
7
8/*
9 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#ifndef _DRM_SAREA_H_
33#define _DRM_SAREA_H_
34
35#include <drm/drm.h>
36
37/* SAREA area needs to be at least a page */
38#if defined(__alpha__)
39#define SAREA_MAX 0x2000U
40#elif defined(__mips__)
41#define SAREA_MAX 0x4000U
42#elif defined(__ia64__)
43#define SAREA_MAX 0x10000U /* 64kB */
44#else
45/* Intel 830M driver needs at least 8k SAREA */
46#define SAREA_MAX 0x2000U
47#endif
48
49/** Maximum number of drawables in the SAREA */
50#define SAREA_MAX_DRAWABLES 256
51
52#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
53
54/** SAREA drawable */
55struct drm_sarea_drawable {
56 unsigned int stamp;
57 unsigned int flags;
58};
59
60/** SAREA frame */
61struct drm_sarea_frame {
62 unsigned int x;
63 unsigned int y;
64 unsigned int width;
65 unsigned int height;
66 unsigned int fullscreen;
67};
68
69/** SAREA */
70struct drm_sarea {
71 /** first thing is always the DRM locking structure */
72 struct drm_hw_lock lock;
73 /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
74 struct drm_hw_lock drawable_lock;
75 struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
76 struct drm_sarea_frame frame; /**< frame */
77 drm_context_t dummy_context;
78};
79
80#ifndef __KERNEL__
81typedef struct drm_sarea_drawable drm_sarea_drawable_t;
82typedef struct drm_sarea_frame drm_sarea_frame_t;
83typedef struct drm_sarea drm_sarea_t;
84#endif
85
86#endif /* _DRM_SAREA_H_ */
diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h
index 1f2acdfbfd6d..0fcc185bf147 100644
--- a/include/drm/exynos_drm.h
+++ b/include/drm/exynos_drm.h
@@ -25,182 +25,11 @@
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE. 26 * OTHER DEALINGS IN THE SOFTWARE.
27 */ 27 */
28
29#ifndef _EXYNOS_DRM_H_ 28#ifndef _EXYNOS_DRM_H_
30#define _EXYNOS_DRM_H_ 29#define _EXYNOS_DRM_H_
31 30
32#include <drm/drm.h> 31#include <uapi/drm/exynos_drm.h>
33
34/**
35 * User-desired buffer creation information structure.
36 *
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
42 */
43struct drm_exynos_gem_create {
44 uint64_t size;
45 unsigned int flags;
46 unsigned int handle;
47};
48
49/**
50 * A structure for getting buffer offset.
51 *
52 * @handle: a pointer to gem object created.
53 * @pad: just padding to be 64-bit aligned.
54 * @offset: relatived offset value of the memory region allocated.
55 * - this value should be set by user.
56 */
57struct drm_exynos_gem_map_off {
58 unsigned int handle;
59 unsigned int pad;
60 uint64_t offset;
61};
62
63/**
64 * A structure for mapping buffer.
65 *
66 * @handle: a handle to gem object created.
67 * @pad: just padding to be 64-bit aligned.
68 * @size: memory size to be mapped.
69 * @mapped: having user virtual address mmaped.
70 * - this variable would be filled by exynos gem module
71 * of kernel side with user virtual address which is allocated
72 * by do_mmap().
73 */
74struct drm_exynos_gem_mmap {
75 unsigned int handle;
76 unsigned int pad;
77 uint64_t size;
78 uint64_t mapped;
79};
80
81/**
82 * A structure to gem information.
83 *
84 * @handle: a handle to gem object created.
85 * @flags: flag value including memory type and cache attribute and
86 * this value would be set by driver.
87 * @size: size to memory region allocated by gem and this size would
88 * be set by driver.
89 */
90struct drm_exynos_gem_info {
91 unsigned int handle;
92 unsigned int flags;
93 uint64_t size;
94};
95
96/**
97 * A structure for user connection request of virtual display.
98 *
99 * @connection: indicate whether doing connetion or not by user.
100 * @extensions: if this value is 1 then the vidi driver would need additional
101 * 128bytes edid data.
102 * @edid: the edid data pointer from user side.
103 */
104struct drm_exynos_vidi_connection {
105 unsigned int connection;
106 unsigned int extensions;
107 uint64_t edid;
108};
109
110/* memory type definitions. */
111enum e_drm_exynos_gem_mem_type {
112 /* Physically Continuous memory and used as default. */
113 EXYNOS_BO_CONTIG = 0 << 0,
114 /* Physically Non-Continuous memory. */
115 EXYNOS_BO_NONCONTIG = 1 << 0,
116 /* non-cachable mapping and used as default. */
117 EXYNOS_BO_NONCACHABLE = 0 << 1,
118 /* cachable mapping. */
119 EXYNOS_BO_CACHABLE = 1 << 1,
120 /* write-combine mapping. */
121 EXYNOS_BO_WC = 1 << 2,
122 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
123 EXYNOS_BO_WC
124};
125
126struct drm_exynos_g2d_get_ver {
127 __u32 major;
128 __u32 minor;
129};
130
131struct drm_exynos_g2d_cmd {
132 __u32 offset;
133 __u32 data;
134};
135
136enum drm_exynos_g2d_event_type {
137 G2D_EVENT_NOT,
138 G2D_EVENT_NONSTOP,
139 G2D_EVENT_STOP, /* not yet */
140};
141
142struct drm_exynos_g2d_set_cmdlist {
143 __u64 cmd;
144 __u64 cmd_gem;
145 __u32 cmd_nr;
146 __u32 cmd_gem_nr;
147
148 /* for g2d event */
149 __u64 event_type;
150 __u64 user_data;
151};
152
153struct drm_exynos_g2d_exec {
154 __u64 async;
155};
156
157#define DRM_EXYNOS_GEM_CREATE 0x00
158#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
159#define DRM_EXYNOS_GEM_MMAP 0x02
160/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
161#define DRM_EXYNOS_GEM_GET 0x04
162#define DRM_EXYNOS_VIDI_CONNECTION 0x07
163
164/* G2D */
165#define DRM_EXYNOS_G2D_GET_VER 0x20
166#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
167#define DRM_EXYNOS_G2D_EXEC 0x22
168
169#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
170 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
171
172#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
173 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
174
175#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
176 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
177
178#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
179 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
180
181#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
182 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
183
184#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
185 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
186#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
187 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
188#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
189 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
190
191/* EXYNOS specific events */
192#define DRM_EXYNOS_G2D_EVENT 0x80000000
193
194struct drm_exynos_g2d_event {
195 struct drm_event base;
196 __u64 user_data;
197 __u32 tv_sec;
198 __u32 tv_usec;
199 __u32 cmdlist_no;
200 __u32 reserved;
201};
202 32
203#ifdef __KERNEL__
204 33
205/** 34/**
206 * A structure for lcd panel information. 35 * A structure for lcd panel information.
@@ -257,5 +86,4 @@ struct exynos_drm_hdmi_pdata {
257 int (*get_hpd)(void); 86 int (*get_hpd)(void);
258}; 87};
259 88
260#endif /* __KERNEL__ */
261#endif /* _EXYNOS_DRM_H_ */ 89#endif /* _EXYNOS_DRM_H_ */
diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h
deleted file mode 100644
index 7a10bb6f2c0f..000000000000
--- a/include/drm/i810_drm.h
+++ /dev/null
@@ -1,281 +0,0 @@
1#ifndef _I810_DRM_H_
2#define _I810_DRM_H_
3
4/* WARNING: These defines must be the same as what the Xserver uses.
5 * if you change them, you must change the defines in the Xserver.
6 */
7
8#ifndef _I810_DEFINES_
9#define _I810_DEFINES_
10
11#define I810_DMA_BUF_ORDER 12
12#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
13#define I810_DMA_BUF_NR 256
14#define I810_NR_SAREA_CLIPRECTS 8
15
16/* Each region is a minimum of 64k, and there are at most 64 of them.
17 */
18#define I810_NR_TEX_REGIONS 64
19#define I810_LOG_MIN_TEX_REGION_SIZE 16
20#endif
21
22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24#define I810_UPLOAD_CTX 0x4
25#define I810_UPLOAD_BUFFERS 0x8
26#define I810_UPLOAD_TEX0 0x10
27#define I810_UPLOAD_TEX1 0x20
28#define I810_UPLOAD_CLIPRECTS 0x40
29
30/* Indices into buf.Setup where various bits of state are mirrored per
31 * context and per buffer. These can be fired at the card as a unit,
32 * or in a piecewise fashion as required.
33 */
34
35/* Destbuffer state
36 * - backbuffer linear offset and pitch -- invarient in the current dri
37 * - zbuffer linear offset and pitch -- also invarient
38 * - drawing origin in back and depth buffers.
39 *
40 * Keep the depth/back buffer state here to accommodate private buffers
41 * in the future.
42 */
43#define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
44#define I810_DESTREG_DI1 1
45#define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
46#define I810_DESTREG_DV1 3
47#define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
48#define I810_DESTREG_DR1 5
49#define I810_DESTREG_DR2 6
50#define I810_DESTREG_DR3 7
51#define I810_DESTREG_DR4 8
52#define I810_DEST_SETUP_SIZE 10
53
54/* Context state
55 */
56#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
57#define I810_CTXREG_CF1 1
58#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
59#define I810_CTXREG_ST1 3
60#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
61#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
62#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
63#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
64#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
65#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
66#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
67#define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
68#define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */
69#define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */
70#define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */
71#define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */
72#define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
73#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
74#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
75#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
76#define I810_CTX_SETUP_SIZE 20
77
78/* Texture state (per tex unit)
79 */
80#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
81#define I810_TEXREG_MI1 1
82#define I810_TEXREG_MI2 2
83#define I810_TEXREG_MI3 3
84#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
85#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
86#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
87#define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */
88#define I810_TEX_SETUP_SIZE 8
89
90/* Flags for clear ioctl
91 */
92#define I810_FRONT 0x1
93#define I810_BACK 0x2
94#define I810_DEPTH 0x4
95
96typedef enum _drm_i810_init_func {
97 I810_INIT_DMA = 0x01,
98 I810_CLEANUP_DMA = 0x02,
99 I810_INIT_DMA_1_4 = 0x03
100} drm_i810_init_func_t;
101
102/* This is the init structure after v1.2 */
103typedef struct _drm_i810_init {
104 drm_i810_init_func_t func;
105 unsigned int mmio_offset;
106 unsigned int buffers_offset;
107 int sarea_priv_offset;
108 unsigned int ring_start;
109 unsigned int ring_end;
110 unsigned int ring_size;
111 unsigned int front_offset;
112 unsigned int back_offset;
113 unsigned int depth_offset;
114 unsigned int overlay_offset;
115 unsigned int overlay_physical;
116 unsigned int w;
117 unsigned int h;
118 unsigned int pitch;
119 unsigned int pitch_bits;
120} drm_i810_init_t;
121
122/* This is the init structure prior to v1.2 */
123typedef struct _drm_i810_pre12_init {
124 drm_i810_init_func_t func;
125 unsigned int mmio_offset;
126 unsigned int buffers_offset;
127 int sarea_priv_offset;
128 unsigned int ring_start;
129 unsigned int ring_end;
130 unsigned int ring_size;
131 unsigned int front_offset;
132 unsigned int back_offset;
133 unsigned int depth_offset;
134 unsigned int w;
135 unsigned int h;
136 unsigned int pitch;
137 unsigned int pitch_bits;
138} drm_i810_pre12_init_t;
139
140/* Warning: If you change the SAREA structure you must change the Xserver
141 * structure as well */
142
143typedef struct _drm_i810_tex_region {
144 unsigned char next, prev; /* indices to form a circular LRU */
145 unsigned char in_use; /* owned by a client, or free? */
146 int age; /* tracked by clients to update local LRU's */
147} drm_i810_tex_region_t;
148
149typedef struct _drm_i810_sarea {
150 unsigned int ContextState[I810_CTX_SETUP_SIZE];
151 unsigned int BufferState[I810_DEST_SETUP_SIZE];
152 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
153 unsigned int dirty;
154
155 unsigned int nbox;
156 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
157
158 /* Maintain an LRU of contiguous regions of texture space. If
159 * you think you own a region of texture memory, and it has an
160 * age different to the one you set, then you are mistaken and
161 * it has been stolen by another client. If global texAge
162 * hasn't changed, there is no need to walk the list.
163 *
164 * These regions can be used as a proxy for the fine-grained
165 * texture information of other clients - by maintaining them
166 * in the same lru which is used to age their own textures,
167 * clients have an approximate lru for the whole of global
168 * texture space, and can make informed decisions as to which
169 * areas to kick out. There is no need to choose whether to
170 * kick out your own texture or someone else's - simply eject
171 * them all in LRU order.
172 */
173
174 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
175 /* Last elt is sentinal */
176 int texAge; /* last time texture was uploaded */
177 int last_enqueue; /* last time a buffer was enqueued */
178 int last_dispatch; /* age of the most recently dispatched buffer */
179 int last_quiescent; /* */
180 int ctxOwner; /* last context to upload state */
181
182 int vertex_prim;
183
184 int pf_enabled; /* is pageflipping allowed? */
185 int pf_active;
186 int pf_current_page; /* which buffer is being displayed? */
187} drm_i810_sarea_t;
188
189/* WARNING: If you change any of these defines, make sure to change the
190 * defines in the Xserver file (xf86drmMga.h)
191 */
192
193/* i810 specific ioctls
194 * The device specific ioctl range is 0x40 to 0x79.
195 */
196#define DRM_I810_INIT 0x00
197#define DRM_I810_VERTEX 0x01
198#define DRM_I810_CLEAR 0x02
199#define DRM_I810_FLUSH 0x03
200#define DRM_I810_GETAGE 0x04
201#define DRM_I810_GETBUF 0x05
202#define DRM_I810_SWAP 0x06
203#define DRM_I810_COPY 0x07
204#define DRM_I810_DOCOPY 0x08
205#define DRM_I810_OV0INFO 0x09
206#define DRM_I810_FSTATUS 0x0a
207#define DRM_I810_OV0FLIP 0x0b
208#define DRM_I810_MC 0x0c
209#define DRM_I810_RSTATUS 0x0d
210#define DRM_I810_FLIP 0x0e
211
212#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
213#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
214#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
215#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH)
216#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE)
217#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
218#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP)
219#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
220#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY)
221#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
222#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
223#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
224#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
225#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
226#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
227
228typedef struct _drm_i810_clear {
229 int clear_color;
230 int clear_depth;
231 int flags;
232} drm_i810_clear_t;
233
234/* These may be placeholders if we have more cliprects than
235 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
236 * false, indicating that the buffer will be dispatched again with a
237 * new set of cliprects.
238 */
239typedef struct _drm_i810_vertex {
240 int idx; /* buffer index */
241 int used; /* nr bytes in use */
242 int discard; /* client is finished with the buffer? */
243} drm_i810_vertex_t;
244
245typedef struct _drm_i810_copy_t {
246 int idx; /* buffer index */
247 int used; /* nr bytes in use */
248 void *address; /* Address to copy from */
249} drm_i810_copy_t;
250
251#define PR_TRIANGLES (0x0<<18)
252#define PR_TRISTRIP_0 (0x1<<18)
253#define PR_TRISTRIP_1 (0x2<<18)
254#define PR_TRIFAN (0x3<<18)
255#define PR_POLYGON (0x4<<18)
256#define PR_LINES (0x5<<18)
257#define PR_LINESTRIP (0x6<<18)
258#define PR_RECTS (0x7<<18)
259#define PR_MASK (0x7<<18)
260
261typedef struct drm_i810_dma {
262 void *virtual;
263 int request_idx;
264 int request_size;
265 int granted;
266} drm_i810_dma_t;
267
268typedef struct _drm_i810_overlay_t {
269 unsigned int offset; /* Address of the Overlay Regs */
270 unsigned int physical;
271} drm_i810_overlay_t;
272
273typedef struct _drm_i810_mc {
274 int idx; /* buffer index */
275 int used; /* nr bytes in use */
276 int num_blocks; /* number of GFXBlocks */
277 int *length; /* List of lengths for GFXBlocks (FUTURE) */
278 unsigned int last_render; /* Last Render Request */
279} drm_i810_mc_t;
280
281#endif /* _I810_DRM_H_ */
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index a940d4e18917..63d609d8a3f6 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -23,933 +23,15 @@
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * 24 *
25 */ 25 */
26
27#ifndef _I915_DRM_H_ 26#ifndef _I915_DRM_H_
28#define _I915_DRM_H_ 27#define _I915_DRM_H_
29 28
30#include <drm/drm.h> 29#include <uapi/drm/i915_drm.h>
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35 30
36#ifdef __KERNEL__
37/* For use by IPS driver */ 31/* For use by IPS driver */
38extern unsigned long i915_read_mch_val(void); 32extern unsigned long i915_read_mch_val(void);
39extern bool i915_gpu_raise(void); 33extern bool i915_gpu_raise(void);
40extern bool i915_gpu_lower(void); 34extern bool i915_gpu_lower(void);
41extern bool i915_gpu_busy(void); 35extern bool i915_gpu_busy(void);
42extern bool i915_gpu_turbo_disable(void); 36extern bool i915_gpu_turbo_disable(void);
43#endif
44
45/* Each region is a minimum of 16k, and there are at most 255 of them.
46 */
47#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
48 * of chars for next/prev indices */
49#define I915_LOG_MIN_TEX_REGION_SIZE 14
50
51typedef struct _drm_i915_init {
52 enum {
53 I915_INIT_DMA = 0x01,
54 I915_CLEANUP_DMA = 0x02,
55 I915_RESUME_DMA = 0x03
56 } func;
57 unsigned int mmio_offset;
58 int sarea_priv_offset;
59 unsigned int ring_start;
60 unsigned int ring_end;
61 unsigned int ring_size;
62 unsigned int front_offset;
63 unsigned int back_offset;
64 unsigned int depth_offset;
65 unsigned int w;
66 unsigned int h;
67 unsigned int pitch;
68 unsigned int pitch_bits;
69 unsigned int back_pitch;
70 unsigned int depth_pitch;
71 unsigned int cpp;
72 unsigned int chipset;
73} drm_i915_init_t;
74
75typedef struct _drm_i915_sarea {
76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
77 int last_upload; /* last time texture was uploaded */
78 int last_enqueue; /* last time a buffer was enqueued */
79 int last_dispatch; /* age of the most recently dispatched buffer */
80 int ctxOwner; /* last context to upload state */
81 int texAge;
82 int pf_enabled; /* is pageflipping allowed? */
83 int pf_active;
84 int pf_current_page; /* which buffer is being displayed? */
85 int perf_boxes; /* performance boxes to be displayed */
86 int width, height; /* screen size in pixels */
87
88 drm_handle_t front_handle;
89 int front_offset;
90 int front_size;
91
92 drm_handle_t back_handle;
93 int back_offset;
94 int back_size;
95
96 drm_handle_t depth_handle;
97 int depth_offset;
98 int depth_size;
99
100 drm_handle_t tex_handle;
101 int tex_offset;
102 int tex_size;
103 int log_tex_granularity;
104 int pitch;
105 int rotation; /* 0, 90, 180 or 270 */
106 int rotated_offset;
107 int rotated_size;
108 int rotated_pitch;
109 int virtualX, virtualY;
110
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
116
117 int pipeA_x;
118 int pipeA_y;
119 int pipeA_w;
120 int pipeA_h;
121 int pipeB_x;
122 int pipeB_y;
123 int pipeB_w;
124 int pipeB_h;
125
126 /* fill out some space for old userspace triple buffer */
127 drm_handle_t unused_handle;
128 __u32 unused1, unused2, unused3;
129
130 /* buffer object handles for static buffers. May change
131 * over the lifetime of the client.
132 */
133 __u32 front_bo_handle;
134 __u32 back_bo_handle;
135 __u32 unused_bo_handle;
136 __u32 depth_bo_handle;
137
138} drm_i915_sarea_t;
139
140/* due to userspace building against these headers we need some compat here */
141#define planeA_x pipeA_x
142#define planeA_y pipeA_y
143#define planeA_w pipeA_w
144#define planeA_h pipeA_h
145#define planeB_x pipeB_x
146#define planeB_y pipeB_y
147#define planeB_w pipeB_w
148#define planeB_h pipeB_h
149
150/* Flags for perf_boxes
151 */
152#define I915_BOX_RING_EMPTY 0x1
153#define I915_BOX_FLIP 0x2
154#define I915_BOX_WAIT 0x4
155#define I915_BOX_TEXTURE_LOAD 0x8
156#define I915_BOX_LOST_CONTEXT 0x10
157
158/* I915 specific ioctls
159 * The device specific ioctl range is 0x40 to 0x79.
160 */
161#define DRM_I915_INIT 0x00
162#define DRM_I915_FLUSH 0x01
163#define DRM_I915_FLIP 0x02
164#define DRM_I915_BATCHBUFFER 0x03
165#define DRM_I915_IRQ_EMIT 0x04
166#define DRM_I915_IRQ_WAIT 0x05
167#define DRM_I915_GETPARAM 0x06
168#define DRM_I915_SETPARAM 0x07
169#define DRM_I915_ALLOC 0x08
170#define DRM_I915_FREE 0x09
171#define DRM_I915_INIT_HEAP 0x0a
172#define DRM_I915_CMDBUFFER 0x0b
173#define DRM_I915_DESTROY_HEAP 0x0c
174#define DRM_I915_SET_VBLANK_PIPE 0x0d
175#define DRM_I915_GET_VBLANK_PIPE 0x0e
176#define DRM_I915_VBLANK_SWAP 0x0f
177#define DRM_I915_HWS_ADDR 0x11
178#define DRM_I915_GEM_INIT 0x13
179#define DRM_I915_GEM_EXECBUFFER 0x14
180#define DRM_I915_GEM_PIN 0x15
181#define DRM_I915_GEM_UNPIN 0x16
182#define DRM_I915_GEM_BUSY 0x17
183#define DRM_I915_GEM_THROTTLE 0x18
184#define DRM_I915_GEM_ENTERVT 0x19
185#define DRM_I915_GEM_LEAVEVT 0x1a
186#define DRM_I915_GEM_CREATE 0x1b
187#define DRM_I915_GEM_PREAD 0x1c
188#define DRM_I915_GEM_PWRITE 0x1d
189#define DRM_I915_GEM_MMAP 0x1e
190#define DRM_I915_GEM_SET_DOMAIN 0x1f
191#define DRM_I915_GEM_SW_FINISH 0x20
192#define DRM_I915_GEM_SET_TILING 0x21
193#define DRM_I915_GEM_GET_TILING 0x22
194#define DRM_I915_GEM_GET_APERTURE 0x23
195#define DRM_I915_GEM_MMAP_GTT 0x24
196#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
197#define DRM_I915_GEM_MADVISE 0x26
198#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
199#define DRM_I915_OVERLAY_ATTRS 0x28
200#define DRM_I915_GEM_EXECBUFFER2 0x29
201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
203#define DRM_I915_GEM_WAIT 0x2c
204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
206#define DRM_I915_GEM_SET_CACHING 0x2f
207#define DRM_I915_GEM_GET_CACHING 0x30
208#define DRM_I915_REG_READ 0x31
209
210#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
211#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
212#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
213#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
214#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
215#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
216#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
217#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
218#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
219#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
220#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
221#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
222#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
223#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
224#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
225#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
226#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
227#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
228#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
229#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
230#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
231#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
232#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
233#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
234#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
235#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
236#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
237#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
238#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
239#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
240#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
241#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
242#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
243#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
244#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
245#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
246#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
247#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
248#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
249#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
250#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
251#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
252#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
253#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
254#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
255#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
256#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
257#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
258
259/* Allow drivers to submit batchbuffers directly to hardware, relying
260 * on the security mechanisms provided by hardware.
261 */
262typedef struct drm_i915_batchbuffer {
263 int start; /* agp offset */
264 int used; /* nr bytes in use */
265 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
266 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
267 int num_cliprects; /* mulitpass with multiple cliprects? */
268 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
269} drm_i915_batchbuffer_t;
270
271/* As above, but pass a pointer to userspace buffer which can be
272 * validated by the kernel prior to sending to hardware.
273 */
274typedef struct _drm_i915_cmdbuffer {
275 char __user *buf; /* pointer to userspace command buffer */
276 int sz; /* nr bytes in buf */
277 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
278 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
279 int num_cliprects; /* mulitpass with multiple cliprects? */
280 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
281} drm_i915_cmdbuffer_t;
282
283/* Userspace can request & wait on irq's:
284 */
285typedef struct drm_i915_irq_emit {
286 int __user *irq_seq;
287} drm_i915_irq_emit_t;
288
289typedef struct drm_i915_irq_wait {
290 int irq_seq;
291} drm_i915_irq_wait_t;
292
293/* Ioctl to query kernel params:
294 */
295#define I915_PARAM_IRQ_ACTIVE 1
296#define I915_PARAM_ALLOW_BATCHBUFFER 2
297#define I915_PARAM_LAST_DISPATCH 3
298#define I915_PARAM_CHIPSET_ID 4
299#define I915_PARAM_HAS_GEM 5
300#define I915_PARAM_NUM_FENCES_AVAIL 6
301#define I915_PARAM_HAS_OVERLAY 7
302#define I915_PARAM_HAS_PAGEFLIPPING 8
303#define I915_PARAM_HAS_EXECBUF2 9
304#define I915_PARAM_HAS_BSD 10
305#define I915_PARAM_HAS_BLT 11
306#define I915_PARAM_HAS_RELAXED_FENCING 12
307#define I915_PARAM_HAS_COHERENT_RINGS 13
308#define I915_PARAM_HAS_EXEC_CONSTANTS 14
309#define I915_PARAM_HAS_RELAXED_DELTA 15
310#define I915_PARAM_HAS_GEN7_SOL_RESET 16
311#define I915_PARAM_HAS_LLC 17
312#define I915_PARAM_HAS_ALIASING_PPGTT 18
313#define I915_PARAM_HAS_WAIT_TIMEOUT 19
314#define I915_PARAM_HAS_SEMAPHORES 20
315#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
316#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
317
318typedef struct drm_i915_getparam {
319 int param;
320 int __user *value;
321} drm_i915_getparam_t;
322
323/* Ioctl to set kernel params:
324 */
325#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
326#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
327#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
328#define I915_SETPARAM_NUM_USED_FENCES 4
329
330typedef struct drm_i915_setparam {
331 int param;
332 int value;
333} drm_i915_setparam_t;
334
335/* A memory manager for regions of shared memory:
336 */
337#define I915_MEM_REGION_AGP 1
338
339typedef struct drm_i915_mem_alloc {
340 int region;
341 int alignment;
342 int size;
343 int __user *region_offset; /* offset from start of fb or agp */
344} drm_i915_mem_alloc_t;
345
346typedef struct drm_i915_mem_free {
347 int region;
348 int region_offset;
349} drm_i915_mem_free_t;
350
351typedef struct drm_i915_mem_init_heap {
352 int region;
353 int size;
354 int start;
355} drm_i915_mem_init_heap_t;
356
357/* Allow memory manager to be torn down and re-initialized (eg on
358 * rotate):
359 */
360typedef struct drm_i915_mem_destroy_heap {
361 int region;
362} drm_i915_mem_destroy_heap_t;
363
364/* Allow X server to configure which pipes to monitor for vblank signals
365 */
366#define DRM_I915_VBLANK_PIPE_A 1
367#define DRM_I915_VBLANK_PIPE_B 2
368
369typedef struct drm_i915_vblank_pipe {
370 int pipe;
371} drm_i915_vblank_pipe_t;
372
373/* Schedule buffer swap at given vertical blank:
374 */
375typedef struct drm_i915_vblank_swap {
376 drm_drawable_t drawable;
377 enum drm_vblank_seq_type seqtype;
378 unsigned int sequence;
379} drm_i915_vblank_swap_t;
380
381typedef struct drm_i915_hws_addr {
382 __u64 addr;
383} drm_i915_hws_addr_t;
384
385struct drm_i915_gem_init {
386 /**
387 * Beginning offset in the GTT to be managed by the DRM memory
388 * manager.
389 */
390 __u64 gtt_start;
391 /**
392 * Ending offset in the GTT to be managed by the DRM memory
393 * manager.
394 */
395 __u64 gtt_end;
396};
397
398struct drm_i915_gem_create {
399 /**
400 * Requested size for the object.
401 *
402 * The (page-aligned) allocated size for the object will be returned.
403 */
404 __u64 size;
405 /**
406 * Returned handle for the object.
407 *
408 * Object handles are nonzero.
409 */
410 __u32 handle;
411 __u32 pad;
412};
413
414struct drm_i915_gem_pread {
415 /** Handle for the object being read. */
416 __u32 handle;
417 __u32 pad;
418 /** Offset into the object to read from */
419 __u64 offset;
420 /** Length of data to read */
421 __u64 size;
422 /**
423 * Pointer to write the data into.
424 *
425 * This is a fixed-size type for 32/64 compatibility.
426 */
427 __u64 data_ptr;
428};
429
430struct drm_i915_gem_pwrite {
431 /** Handle for the object being written to. */
432 __u32 handle;
433 __u32 pad;
434 /** Offset into the object to write to */
435 __u64 offset;
436 /** Length of data to write */
437 __u64 size;
438 /**
439 * Pointer to read the data from.
440 *
441 * This is a fixed-size type for 32/64 compatibility.
442 */
443 __u64 data_ptr;
444};
445
446struct drm_i915_gem_mmap {
447 /** Handle for the object being mapped. */
448 __u32 handle;
449 __u32 pad;
450 /** Offset in the object to map. */
451 __u64 offset;
452 /**
453 * Length of data to map.
454 *
455 * The value will be page-aligned.
456 */
457 __u64 size;
458 /**
459 * Returned pointer the data was mapped at.
460 *
461 * This is a fixed-size type for 32/64 compatibility.
462 */
463 __u64 addr_ptr;
464};
465
466struct drm_i915_gem_mmap_gtt {
467 /** Handle for the object being mapped. */
468 __u32 handle;
469 __u32 pad;
470 /**
471 * Fake offset to use for subsequent mmap call
472 *
473 * This is a fixed-size type for 32/64 compatibility.
474 */
475 __u64 offset;
476};
477
478struct drm_i915_gem_set_domain {
479 /** Handle for the object */
480 __u32 handle;
481
482 /** New read domains */
483 __u32 read_domains;
484
485 /** New write domain */
486 __u32 write_domain;
487};
488
489struct drm_i915_gem_sw_finish {
490 /** Handle for the object */
491 __u32 handle;
492};
493
494struct drm_i915_gem_relocation_entry {
495 /**
496 * Handle of the buffer being pointed to by this relocation entry.
497 *
498 * It's appealing to make this be an index into the mm_validate_entry
499 * list to refer to the buffer, but this allows the driver to create
500 * a relocation list for state buffers and not re-write it per
501 * exec using the buffer.
502 */
503 __u32 target_handle;
504
505 /**
506 * Value to be added to the offset of the target buffer to make up
507 * the relocation entry.
508 */
509 __u32 delta;
510
511 /** Offset in the buffer the relocation entry will be written into */
512 __u64 offset;
513
514 /**
515 * Offset value of the target buffer that the relocation entry was last
516 * written as.
517 *
518 * If the buffer has the same offset as last time, we can skip syncing
519 * and writing the relocation. This value is written back out by
520 * the execbuffer ioctl when the relocation is written.
521 */
522 __u64 presumed_offset;
523
524 /**
525 * Target memory domains read by this operation.
526 */
527 __u32 read_domains;
528
529 /**
530 * Target memory domains written by this operation.
531 *
532 * Note that only one domain may be written by the whole
533 * execbuffer operation, so that where there are conflicts,
534 * the application will get -EINVAL back.
535 */
536 __u32 write_domain;
537};
538
539/** @{
540 * Intel memory domains
541 *
542 * Most of these just align with the various caches in
543 * the system and are used to flush and invalidate as
544 * objects end up cached in different domains.
545 */
546/** CPU cache */
547#define I915_GEM_DOMAIN_CPU 0x00000001
548/** Render cache, used by 2D and 3D drawing */
549#define I915_GEM_DOMAIN_RENDER 0x00000002
550/** Sampler cache, used by texture engine */
551#define I915_GEM_DOMAIN_SAMPLER 0x00000004
552/** Command queue, used to load batch buffers */
553#define I915_GEM_DOMAIN_COMMAND 0x00000008
554/** Instruction cache, used by shader programs */
555#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
556/** Vertex address cache */
557#define I915_GEM_DOMAIN_VERTEX 0x00000020
558/** GTT domain - aperture and scanout */
559#define I915_GEM_DOMAIN_GTT 0x00000040
560/** @} */
561
562struct drm_i915_gem_exec_object {
563 /**
564 * User's handle for a buffer to be bound into the GTT for this
565 * operation.
566 */
567 __u32 handle;
568
569 /** Number of relocations to be performed on this buffer */
570 __u32 relocation_count;
571 /**
572 * Pointer to array of struct drm_i915_gem_relocation_entry containing
573 * the relocations to be performed in this buffer.
574 */
575 __u64 relocs_ptr;
576
577 /** Required alignment in graphics aperture */
578 __u64 alignment;
579
580 /**
581 * Returned value of the updated offset of the object, for future
582 * presumed_offset writes.
583 */
584 __u64 offset;
585};
586
587struct drm_i915_gem_execbuffer {
588 /**
589 * List of buffers to be validated with their relocations to be
590 * performend on them.
591 *
592 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
593 *
594 * These buffers must be listed in an order such that all relocations
595 * a buffer is performing refer to buffers that have already appeared
596 * in the validate list.
597 */
598 __u64 buffers_ptr;
599 __u32 buffer_count;
600
601 /** Offset in the batchbuffer to start execution from. */
602 __u32 batch_start_offset;
603 /** Bytes used in batchbuffer from batch_start_offset */
604 __u32 batch_len;
605 __u32 DR1;
606 __u32 DR4;
607 __u32 num_cliprects;
608 /** This is a struct drm_clip_rect *cliprects */
609 __u64 cliprects_ptr;
610};
611
612struct drm_i915_gem_exec_object2 {
613 /**
614 * User's handle for a buffer to be bound into the GTT for this
615 * operation.
616 */
617 __u32 handle;
618
619 /** Number of relocations to be performed on this buffer */
620 __u32 relocation_count;
621 /**
622 * Pointer to array of struct drm_i915_gem_relocation_entry containing
623 * the relocations to be performed in this buffer.
624 */
625 __u64 relocs_ptr;
626
627 /** Required alignment in graphics aperture */
628 __u64 alignment;
629
630 /**
631 * Returned value of the updated offset of the object, for future
632 * presumed_offset writes.
633 */
634 __u64 offset;
635
636#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
637 __u64 flags;
638 __u64 rsvd1;
639 __u64 rsvd2;
640};
641
642struct drm_i915_gem_execbuffer2 {
643 /**
644 * List of gem_exec_object2 structs
645 */
646 __u64 buffers_ptr;
647 __u32 buffer_count;
648
649 /** Offset in the batchbuffer to start execution from. */
650 __u32 batch_start_offset;
651 /** Bytes used in batchbuffer from batch_start_offset */
652 __u32 batch_len;
653 __u32 DR1;
654 __u32 DR4;
655 __u32 num_cliprects;
656 /** This is a struct drm_clip_rect *cliprects */
657 __u64 cliprects_ptr;
658#define I915_EXEC_RING_MASK (7<<0)
659#define I915_EXEC_DEFAULT (0<<0)
660#define I915_EXEC_RENDER (1<<0)
661#define I915_EXEC_BSD (2<<0)
662#define I915_EXEC_BLT (3<<0)
663
664/* Used for switching the constants addressing mode on gen4+ RENDER ring.
665 * Gen6+ only supports relative addressing to dynamic state (default) and
666 * absolute addressing.
667 *
668 * These flags are ignored for the BSD and BLT rings.
669 */
670#define I915_EXEC_CONSTANTS_MASK (3<<6)
671#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
672#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
673#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
674 __u64 flags;
675 __u64 rsvd1; /* now used for context info */
676 __u64 rsvd2;
677};
678
679/** Resets the SO write offset registers for transform feedback on gen7. */
680#define I915_EXEC_GEN7_SOL_RESET (1<<8)
681
682#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
683#define i915_execbuffer2_set_context_id(eb2, context) \
684 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
685#define i915_execbuffer2_get_context_id(eb2) \
686 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
687
688struct drm_i915_gem_pin {
689 /** Handle of the buffer to be pinned. */
690 __u32 handle;
691 __u32 pad;
692
693 /** alignment required within the aperture */
694 __u64 alignment;
695
696 /** Returned GTT offset of the buffer. */
697 __u64 offset;
698};
699
700struct drm_i915_gem_unpin {
701 /** Handle of the buffer to be unpinned. */
702 __u32 handle;
703 __u32 pad;
704};
705
706struct drm_i915_gem_busy {
707 /** Handle of the buffer to check for busy */
708 __u32 handle;
709
710 /** Return busy status (1 if busy, 0 if idle).
711 * The high word is used to indicate on which rings the object
712 * currently resides:
713 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
714 */
715 __u32 busy;
716};
717
718#define I915_CACHING_NONE 0
719#define I915_CACHING_CACHED 1
720
721struct drm_i915_gem_caching {
722 /**
723 * Handle of the buffer to set/get the caching level of. */
724 __u32 handle;
725
726 /**
727 * Cacheing level to apply or return value
728 *
729 * bits0-15 are for generic caching control (i.e. the above defined
730 * values). bits16-31 are reserved for platform-specific variations
731 * (e.g. l3$ caching on gen7). */
732 __u32 caching;
733};
734
735#define I915_TILING_NONE 0
736#define I915_TILING_X 1
737#define I915_TILING_Y 2
738
739#define I915_BIT_6_SWIZZLE_NONE 0
740#define I915_BIT_6_SWIZZLE_9 1
741#define I915_BIT_6_SWIZZLE_9_10 2
742#define I915_BIT_6_SWIZZLE_9_11 3
743#define I915_BIT_6_SWIZZLE_9_10_11 4
744/* Not seen by userland */
745#define I915_BIT_6_SWIZZLE_UNKNOWN 5
746/* Seen by userland. */
747#define I915_BIT_6_SWIZZLE_9_17 6
748#define I915_BIT_6_SWIZZLE_9_10_17 7
749
750struct drm_i915_gem_set_tiling {
751 /** Handle of the buffer to have its tiling state updated */
752 __u32 handle;
753
754 /**
755 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
756 * I915_TILING_Y).
757 *
758 * This value is to be set on request, and will be updated by the
759 * kernel on successful return with the actual chosen tiling layout.
760 *
761 * The tiling mode may be demoted to I915_TILING_NONE when the system
762 * has bit 6 swizzling that can't be managed correctly by GEM.
763 *
764 * Buffer contents become undefined when changing tiling_mode.
765 */
766 __u32 tiling_mode;
767
768 /**
769 * Stride in bytes for the object when in I915_TILING_X or
770 * I915_TILING_Y.
771 */
772 __u32 stride;
773
774 /**
775 * Returned address bit 6 swizzling required for CPU access through
776 * mmap mapping.
777 */
778 __u32 swizzle_mode;
779};
780
781struct drm_i915_gem_get_tiling {
782 /** Handle of the buffer to get tiling state for. */
783 __u32 handle;
784
785 /**
786 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
787 * I915_TILING_Y).
788 */
789 __u32 tiling_mode;
790
791 /**
792 * Returned address bit 6 swizzling required for CPU access through
793 * mmap mapping.
794 */
795 __u32 swizzle_mode;
796};
797
798struct drm_i915_gem_get_aperture {
799 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
800 __u64 aper_size;
801
802 /**
803 * Available space in the aperture used by i915_gem_execbuffer, in
804 * bytes
805 */
806 __u64 aper_available_size;
807};
808
809struct drm_i915_get_pipe_from_crtc_id {
810 /** ID of CRTC being requested **/
811 __u32 crtc_id;
812
813 /** pipe of requested CRTC **/
814 __u32 pipe;
815};
816
817#define I915_MADV_WILLNEED 0
818#define I915_MADV_DONTNEED 1
819#define __I915_MADV_PURGED 2 /* internal state */
820
821struct drm_i915_gem_madvise {
822 /** Handle of the buffer to change the backing store advice */
823 __u32 handle;
824
825 /* Advice: either the buffer will be needed again in the near future,
826 * or wont be and could be discarded under memory pressure.
827 */
828 __u32 madv;
829
830 /** Whether the backing store still exists. */
831 __u32 retained;
832};
833
834/* flags */
835#define I915_OVERLAY_TYPE_MASK 0xff
836#define I915_OVERLAY_YUV_PLANAR 0x01
837#define I915_OVERLAY_YUV_PACKED 0x02
838#define I915_OVERLAY_RGB 0x03
839
840#define I915_OVERLAY_DEPTH_MASK 0xff00
841#define I915_OVERLAY_RGB24 0x1000
842#define I915_OVERLAY_RGB16 0x2000
843#define I915_OVERLAY_RGB15 0x3000
844#define I915_OVERLAY_YUV422 0x0100
845#define I915_OVERLAY_YUV411 0x0200
846#define I915_OVERLAY_YUV420 0x0300
847#define I915_OVERLAY_YUV410 0x0400
848
849#define I915_OVERLAY_SWAP_MASK 0xff0000
850#define I915_OVERLAY_NO_SWAP 0x000000
851#define I915_OVERLAY_UV_SWAP 0x010000
852#define I915_OVERLAY_Y_SWAP 0x020000
853#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
854
855#define I915_OVERLAY_FLAGS_MASK 0xff000000
856#define I915_OVERLAY_ENABLE 0x01000000
857
858struct drm_intel_overlay_put_image {
859 /* various flags and src format description */
860 __u32 flags;
861 /* source picture description */
862 __u32 bo_handle;
863 /* stride values and offsets are in bytes, buffer relative */
864 __u16 stride_Y; /* stride for packed formats */
865 __u16 stride_UV;
866 __u32 offset_Y; /* offset for packet formats */
867 __u32 offset_U;
868 __u32 offset_V;
869 /* in pixels */
870 __u16 src_width;
871 __u16 src_height;
872 /* to compensate the scaling factors for partially covered surfaces */
873 __u16 src_scan_width;
874 __u16 src_scan_height;
875 /* output crtc description */
876 __u32 crtc_id;
877 __u16 dst_x;
878 __u16 dst_y;
879 __u16 dst_width;
880 __u16 dst_height;
881};
882
883/* flags */
884#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
885#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
886struct drm_intel_overlay_attrs {
887 __u32 flags;
888 __u32 color_key;
889 __s32 brightness;
890 __u32 contrast;
891 __u32 saturation;
892 __u32 gamma0;
893 __u32 gamma1;
894 __u32 gamma2;
895 __u32 gamma3;
896 __u32 gamma4;
897 __u32 gamma5;
898};
899
900/*
901 * Intel sprite handling
902 *
903 * Color keying works with a min/mask/max tuple. Both source and destination
904 * color keying is allowed.
905 *
906 * Source keying:
907 * Sprite pixels within the min & max values, masked against the color channels
908 * specified in the mask field, will be transparent. All other pixels will
909 * be displayed on top of the primary plane. For RGB surfaces, only the min
910 * and mask fields will be used; ranged compares are not allowed.
911 *
912 * Destination keying:
913 * Primary plane pixels that match the min value, masked against the color
914 * channels specified in the mask field, will be replaced by corresponding
915 * pixels from the sprite plane.
916 *
917 * Note that source & destination keying are exclusive; only one can be
918 * active on a given plane.
919 */
920
921#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
922#define I915_SET_COLORKEY_DESTINATION (1<<1)
923#define I915_SET_COLORKEY_SOURCE (1<<2)
924struct drm_intel_sprite_colorkey {
925 __u32 plane_id;
926 __u32 min_value;
927 __u32 channel_mask;
928 __u32 max_value;
929 __u32 flags;
930};
931
932struct drm_i915_gem_wait {
933 /** Handle of BO we shall wait on */
934 __u32 bo_handle;
935 __u32 flags;
936 /** Number of nanoseconds to wait, Returns time remaining. */
937 __s64 timeout_ns;
938};
939
940struct drm_i915_gem_context_create {
941 /* output: id of new context*/
942 __u32 ctx_id;
943 __u32 pad;
944};
945
946struct drm_i915_gem_context_destroy {
947 __u32 ctx_id;
948 __u32 pad;
949};
950
951struct drm_i915_reg_read {
952 __u64 offset;
953 __u64 val; /* Return value */
954};
955#endif /* _I915_DRM_H_ */ 37#endif /* _I915_DRM_H_ */
diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h
deleted file mode 100644
index 2375bfd6e5e9..000000000000
--- a/include/drm/mga_drm.h
+++ /dev/null
@@ -1,419 +0,0 @@
1/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 */
34
35#ifndef __MGA_DRM_H__
36#define __MGA_DRM_H__
37
38#include <drm/drm.h>
39
40/* WARNING: If you change any of these defines, make sure to change the
41 * defines in the Xserver file (mga_sarea.h)
42 */
43
44#ifndef __MGA_SAREA_DEFINES__
45#define __MGA_SAREA_DEFINES__
46
47/* WARP pipe flags
48 */
49#define MGA_F 0x1 /* fog */
50#define MGA_A 0x2 /* alpha */
51#define MGA_S 0x4 /* specular */
52#define MGA_T2 0x8 /* multitexture */
53
54#define MGA_WARP_TGZ 0
55#define MGA_WARP_TGZF (MGA_F)
56#define MGA_WARP_TGZA (MGA_A)
57#define MGA_WARP_TGZAF (MGA_F|MGA_A)
58#define MGA_WARP_TGZS (MGA_S)
59#define MGA_WARP_TGZSF (MGA_S|MGA_F)
60#define MGA_WARP_TGZSA (MGA_S|MGA_A)
61#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
62#define MGA_WARP_T2GZ (MGA_T2)
63#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
64#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
65#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
66#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
67#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
68#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
69#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
70
71#define MGA_MAX_G200_PIPES 8 /* no multitex */
72#define MGA_MAX_G400_PIPES 16
73#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
74#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
75
76#define MGA_CARD_TYPE_G200 1
77#define MGA_CARD_TYPE_G400 2
78#define MGA_CARD_TYPE_G450 3 /* not currently used */
79#define MGA_CARD_TYPE_G550 4
80
81#define MGA_FRONT 0x1
82#define MGA_BACK 0x2
83#define MGA_DEPTH 0x4
84
85/* What needs to be changed for the current vertex dma buffer?
86 */
87#define MGA_UPLOAD_CONTEXT 0x1
88#define MGA_UPLOAD_TEX0 0x2
89#define MGA_UPLOAD_TEX1 0x4
90#define MGA_UPLOAD_PIPE 0x8
91#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
92#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
93#define MGA_UPLOAD_2D 0x40
94#define MGA_WAIT_AGE 0x80 /* handled client-side */
95#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
96#if 0
97#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
98 quiescent */
99#endif
100
101/* 32 buffers of 64k each, total 2 meg.
102 */
103#define MGA_BUFFER_SIZE (1 << 16)
104#define MGA_NUM_BUFFERS 128
105
106/* Keep these small for testing.
107 */
108#define MGA_NR_SAREA_CLIPRECTS 8
109
110/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
111 * regions, subject to a minimum region size of (1<<16) == 64k.
112 *
113 * Clients may subdivide regions internally, but when sharing between
114 * clients, the region size is the minimum granularity.
115 */
116
117#define MGA_CARD_HEAP 0
118#define MGA_AGP_HEAP 1
119#define MGA_NR_TEX_HEAPS 2
120#define MGA_NR_TEX_REGIONS 16
121#define MGA_LOG_MIN_TEX_REGION_SIZE 16
122
123#define DRM_MGA_IDLE_RETRY 2048
124
125#endif /* __MGA_SAREA_DEFINES__ */
126
127/* Setup registers for 3D context
128 */
129typedef struct {
130 unsigned int dstorg;
131 unsigned int maccess;
132 unsigned int plnwt;
133 unsigned int dwgctl;
134 unsigned int alphactrl;
135 unsigned int fogcolor;
136 unsigned int wflag;
137 unsigned int tdualstage0;
138 unsigned int tdualstage1;
139 unsigned int fcol;
140 unsigned int stencil;
141 unsigned int stencilctl;
142} drm_mga_context_regs_t;
143
144/* Setup registers for 2D, X server
145 */
146typedef struct {
147 unsigned int pitch;
148} drm_mga_server_regs_t;
149
150/* Setup registers for each texture unit
151 */
152typedef struct {
153 unsigned int texctl;
154 unsigned int texctl2;
155 unsigned int texfilter;
156 unsigned int texbordercol;
157 unsigned int texorg;
158 unsigned int texwidth;
159 unsigned int texheight;
160 unsigned int texorg1;
161 unsigned int texorg2;
162 unsigned int texorg3;
163 unsigned int texorg4;
164} drm_mga_texture_regs_t;
165
166/* General aging mechanism
167 */
168typedef struct {
169 unsigned int head; /* Position of head pointer */
170 unsigned int wrap; /* Primary DMA wrap count */
171} drm_mga_age_t;
172
173typedef struct _drm_mga_sarea {
174 /* The channel for communication of state information to the kernel
175 * on firing a vertex dma buffer.
176 */
177 drm_mga_context_regs_t context_state;
178 drm_mga_server_regs_t server_state;
179 drm_mga_texture_regs_t tex_state[2];
180 unsigned int warp_pipe;
181 unsigned int dirty;
182 unsigned int vertsize;
183
184 /* The current cliprects, or a subset thereof.
185 */
186 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
187 unsigned int nbox;
188
189 /* Information about the most recently used 3d drawable. The
190 * client fills in the req_* fields, the server fills in the
191 * exported_ fields and puts the cliprects into boxes, above.
192 *
193 * The client clears the exported_drawable field before
194 * clobbering the boxes data.
195 */
196 unsigned int req_drawable; /* the X drawable id */
197 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
198
199 unsigned int exported_drawable;
200 unsigned int exported_index;
201 unsigned int exported_stamp;
202 unsigned int exported_buffers;
203 unsigned int exported_nfront;
204 unsigned int exported_nback;
205 int exported_back_x, exported_front_x, exported_w;
206 int exported_back_y, exported_front_y, exported_h;
207 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
208
209 /* Counters for aging textures and for client-side throttling.
210 */
211 unsigned int status[4];
212 unsigned int last_wrap;
213
214 drm_mga_age_t last_frame;
215 unsigned int last_enqueue; /* last time a buffer was enqueued */
216 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
217 unsigned int last_quiescent; /* */
218
219 /* LRU lists for texture memory in agp space and on the card.
220 */
221 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
222 unsigned int texAge[MGA_NR_TEX_HEAPS];
223
224 /* Mechanism to validate card state.
225 */
226 int ctxOwner;
227} drm_mga_sarea_t;
228
229/* MGA specific ioctls
230 * The device specific ioctl range is 0x40 to 0x79.
231 */
232#define DRM_MGA_INIT 0x00
233#define DRM_MGA_FLUSH 0x01
234#define DRM_MGA_RESET 0x02
235#define DRM_MGA_SWAP 0x03
236#define DRM_MGA_CLEAR 0x04
237#define DRM_MGA_VERTEX 0x05
238#define DRM_MGA_INDICES 0x06
239#define DRM_MGA_ILOAD 0x07
240#define DRM_MGA_BLIT 0x08
241#define DRM_MGA_GETPARAM 0x09
242
243/* 3.2:
244 * ioctls for operating on fences.
245 */
246#define DRM_MGA_SET_FENCE 0x0a
247#define DRM_MGA_WAIT_FENCE 0x0b
248#define DRM_MGA_DMA_BOOTSTRAP 0x0c
249
250#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
251#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
252#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
253#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
254#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
255#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
256#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
257#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
258#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
259#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
260#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
261#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
262#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
263
264typedef struct _drm_mga_warp_index {
265 int installed;
266 unsigned long phys_addr;
267 int size;
268} drm_mga_warp_index_t;
269
270typedef struct drm_mga_init {
271 enum {
272 MGA_INIT_DMA = 0x01,
273 MGA_CLEANUP_DMA = 0x02
274 } func;
275
276 unsigned long sarea_priv_offset;
277
278 int chipset;
279 int sgram;
280
281 unsigned int maccess;
282
283 unsigned int fb_cpp;
284 unsigned int front_offset, front_pitch;
285 unsigned int back_offset, back_pitch;
286
287 unsigned int depth_cpp;
288 unsigned int depth_offset, depth_pitch;
289
290 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
291 unsigned int texture_size[MGA_NR_TEX_HEAPS];
292
293 unsigned long fb_offset;
294 unsigned long mmio_offset;
295 unsigned long status_offset;
296 unsigned long warp_offset;
297 unsigned long primary_offset;
298 unsigned long buffers_offset;
299} drm_mga_init_t;
300
301typedef struct drm_mga_dma_bootstrap {
302 /**
303 * \name AGP texture region
304 *
305 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
306 * be filled in with the actual AGP texture settings.
307 *
308 * \warning
309 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
310 * is zero, it means that PCI memory (most likely through the use of
311 * an IOMMU) is being used for "AGP" textures.
312 */
313 /*@{ */
314 unsigned long texture_handle; /**< Handle used to map AGP textures. */
315 __u32 texture_size; /**< Size of the AGP texture region. */
316 /*@} */
317
318 /**
319 * Requested size of the primary DMA region.
320 *
321 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
322 * filled in with the actual AGP mode. If AGP was not available
323 */
324 __u32 primary_size;
325
326 /**
327 * Requested number of secondary DMA buffers.
328 *
329 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
330 * filled in with the actual number of secondary DMA buffers
331 * allocated. Particularly when PCI DMA is used, this may be
332 * (subtantially) less than the number requested.
333 */
334 __u32 secondary_bin_count;
335
336 /**
337 * Requested size of each secondary DMA buffer.
338 *
339 * While the kernel \b is free to reduce
340 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
341 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
342 */
343 __u32 secondary_bin_size;
344
345 /**
346 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
347 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
348 * zero, it means that PCI DMA should be used, even if AGP is
349 * possible.
350 *
351 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
352 * filled in with the actual AGP mode. If AGP was not available
353 * (i.e., PCI DMA was used), this value will be zero.
354 */
355 __u32 agp_mode;
356
357 /**
358 * Desired AGP GART size, measured in megabytes.
359 */
360 __u8 agp_size;
361} drm_mga_dma_bootstrap_t;
362
363typedef struct drm_mga_clear {
364 unsigned int flags;
365 unsigned int clear_color;
366 unsigned int clear_depth;
367 unsigned int color_mask;
368 unsigned int depth_mask;
369} drm_mga_clear_t;
370
371typedef struct drm_mga_vertex {
372 int idx; /* buffer to queue */
373 int used; /* bytes in use */
374 int discard; /* client finished with buffer? */
375} drm_mga_vertex_t;
376
377typedef struct drm_mga_indices {
378 int idx; /* buffer to queue */
379 unsigned int start;
380 unsigned int end;
381 int discard; /* client finished with buffer? */
382} drm_mga_indices_t;
383
384typedef struct drm_mga_iload {
385 int idx;
386 unsigned int dstorg;
387 unsigned int length;
388} drm_mga_iload_t;
389
390typedef struct _drm_mga_blit {
391 unsigned int planemask;
392 unsigned int srcorg;
393 unsigned int dstorg;
394 int src_pitch, dst_pitch;
395 int delta_sx, delta_sy;
396 int delta_dx, delta_dy;
397 int height, ydir; /* flip image vertically */
398 int source_pitch, dest_pitch;
399} drm_mga_blit_t;
400
401/* 3.1: An ioctl to get parameters that aren't available to the 3d
402 * client any other way.
403 */
404#define MGA_PARAM_IRQ_NR 1
405
406/* 3.2: Query the actual card type. The DDX only distinguishes between
407 * G200 chips and non-G200 chips, which it calls G400. It turns out that
408 * there are some very sublte differences between the G4x0 chips and the G550
409 * chips. Using this parameter query, a client-side driver can detect the
410 * difference between a G4x0 and a G550.
411 */
412#define MGA_PARAM_CARD_TYPE 2
413
414typedef struct drm_mga_getparam {
415 int param;
416 void __user *value;
417} drm_mga_getparam_t;
418
419#endif
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
deleted file mode 100644
index 2a5769fdf8ba..000000000000
--- a/include/drm/nouveau_drm.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__
27
28#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
29#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
30#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
31#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
32
33#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
34#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
35#define NOUVEAU_GEM_TILE_16BPP 0x00000001
36#define NOUVEAU_GEM_TILE_32BPP 0x00000002
37#define NOUVEAU_GEM_TILE_ZETA 0x00000004
38#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
39
40struct drm_nouveau_gem_info {
41 uint32_t handle;
42 uint32_t domain;
43 uint64_t size;
44 uint64_t offset;
45 uint64_t map_handle;
46 uint32_t tile_mode;
47 uint32_t tile_flags;
48};
49
50struct drm_nouveau_gem_new {
51 struct drm_nouveau_gem_info info;
52 uint32_t channel_hint;
53 uint32_t align;
54};
55
56#define NOUVEAU_GEM_MAX_BUFFERS 1024
57struct drm_nouveau_gem_pushbuf_bo_presumed {
58 uint32_t valid;
59 uint32_t domain;
60 uint64_t offset;
61};
62
63struct drm_nouveau_gem_pushbuf_bo {
64 uint64_t user_priv;
65 uint32_t handle;
66 uint32_t read_domains;
67 uint32_t write_domains;
68 uint32_t valid_domains;
69 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
70};
71
72#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
73#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
74#define NOUVEAU_GEM_RELOC_OR (1 << 2)
75#define NOUVEAU_GEM_MAX_RELOCS 1024
76struct drm_nouveau_gem_pushbuf_reloc {
77 uint32_t reloc_bo_index;
78 uint32_t reloc_bo_offset;
79 uint32_t bo_index;
80 uint32_t flags;
81 uint32_t data;
82 uint32_t vor;
83 uint32_t tor;
84};
85
86#define NOUVEAU_GEM_MAX_PUSH 512
87struct drm_nouveau_gem_pushbuf_push {
88 uint32_t bo_index;
89 uint32_t pad;
90 uint64_t offset;
91 uint64_t length;
92};
93
94struct drm_nouveau_gem_pushbuf {
95 uint32_t channel;
96 uint32_t nr_buffers;
97 uint64_t buffers;
98 uint32_t nr_relocs;
99 uint32_t nr_push;
100 uint64_t relocs;
101 uint64_t push;
102 uint32_t suffix0;
103 uint32_t suffix1;
104 uint64_t vram_available;
105 uint64_t gart_available;
106};
107
108#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
109#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
110struct drm_nouveau_gem_cpu_prep {
111 uint32_t handle;
112 uint32_t flags;
113};
114
115struct drm_nouveau_gem_cpu_fini {
116 uint32_t handle;
117};
118
119#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
120#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
121#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
122#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
123#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
124#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
125#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
126#define DRM_NOUVEAU_GEM_NEW 0x40
127#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
128#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
129#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
130#define DRM_NOUVEAU_GEM_INFO 0x44
131
132#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
133#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
134#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
135#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
136#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
137
138#endif /* __NOUVEAU_DRM_H__ */
diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h
deleted file mode 100644
index 8d8878b55f55..000000000000
--- a/include/drm/r128_drm.h
+++ /dev/null
@@ -1,326 +0,0 @@
1/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4/*
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All rights reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 * Kevin E. Martin <martin@valinux.com>
31 */
32
33#ifndef __R128_DRM_H__
34#define __R128_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (r128_sarea.h)
38 */
39#ifndef __R128_SAREA_DEFINES__
40#define __R128_SAREA_DEFINES__
41
42/* What needs to be changed for the current vertex buffer?
43 */
44#define R128_UPLOAD_CONTEXT 0x001
45#define R128_UPLOAD_SETUP 0x002
46#define R128_UPLOAD_TEX0 0x004
47#define R128_UPLOAD_TEX1 0x008
48#define R128_UPLOAD_TEX0IMAGES 0x010
49#define R128_UPLOAD_TEX1IMAGES 0x020
50#define R128_UPLOAD_CORE 0x040
51#define R128_UPLOAD_MASKS 0x080
52#define R128_UPLOAD_WINDOW 0x100
53#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
54#define R128_REQUIRE_QUIESCENCE 0x400
55#define R128_UPLOAD_ALL 0x7ff
56
57#define R128_FRONT 0x1
58#define R128_BACK 0x2
59#define R128_DEPTH 0x4
60
61/* Primitive types
62 */
63#define R128_POINTS 0x1
64#define R128_LINES 0x2
65#define R128_LINE_STRIP 0x3
66#define R128_TRIANGLES 0x4
67#define R128_TRIANGLE_FAN 0x5
68#define R128_TRIANGLE_STRIP 0x6
69
70/* Vertex/indirect buffer size
71 */
72#define R128_BUFFER_SIZE 16384
73
74/* Byte offsets for indirect buffer data
75 */
76#define R128_INDEX_PRIM_OFFSET 20
77#define R128_HOSTDATA_BLIT_OFFSET 32
78
79/* Keep these small for testing.
80 */
81#define R128_NR_SAREA_CLIPRECTS 12
82
83/* There are 2 heaps (local/AGP). Each region within a heap is a
84 * minimum of 64k, and there are at most 64 of them per heap.
85 */
86#define R128_LOCAL_TEX_HEAP 0
87#define R128_AGP_TEX_HEAP 1
88#define R128_NR_TEX_HEAPS 2
89#define R128_NR_TEX_REGIONS 64
90#define R128_LOG_TEX_GRANULARITY 16
91
92#define R128_NR_CONTEXT_REGS 12
93
94#define R128_MAX_TEXTURE_LEVELS 11
95#define R128_MAX_TEXTURE_UNITS 2
96
97#endif /* __R128_SAREA_DEFINES__ */
98
99typedef struct {
100 /* Context state - can be written in one large chunk */
101 unsigned int dst_pitch_offset_c;
102 unsigned int dp_gui_master_cntl_c;
103 unsigned int sc_top_left_c;
104 unsigned int sc_bottom_right_c;
105 unsigned int z_offset_c;
106 unsigned int z_pitch_c;
107 unsigned int z_sten_cntl_c;
108 unsigned int tex_cntl_c;
109 unsigned int misc_3d_state_cntl_reg;
110 unsigned int texture_clr_cmp_clr_c;
111 unsigned int texture_clr_cmp_msk_c;
112 unsigned int fog_color_c;
113
114 /* Texture state */
115 unsigned int tex_size_pitch_c;
116 unsigned int constant_color_c;
117
118 /* Setup state */
119 unsigned int pm4_vc_fpu_setup;
120 unsigned int setup_cntl;
121
122 /* Mask state */
123 unsigned int dp_write_mask;
124 unsigned int sten_ref_mask_c;
125 unsigned int plane_3d_mask_c;
126
127 /* Window state */
128 unsigned int window_xy_offset;
129
130 /* Core state */
131 unsigned int scale_3d_cntl;
132} drm_r128_context_regs_t;
133
134/* Setup registers for each texture unit
135 */
136typedef struct {
137 unsigned int tex_cntl;
138 unsigned int tex_combine_cntl;
139 unsigned int tex_size_pitch;
140 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
141 unsigned int tex_border_color;
142} drm_r128_texture_regs_t;
143
144typedef struct drm_r128_sarea {
145 /* The channel for communication of state information to the kernel
146 * on firing a vertex buffer.
147 */
148 drm_r128_context_regs_t context_state;
149 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
150 unsigned int dirty;
151 unsigned int vertsize;
152 unsigned int vc_format;
153
154 /* The current cliprects, or a subset thereof.
155 */
156 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
157 unsigned int nbox;
158
159 /* Counters for client-side throttling of rendering clients.
160 */
161 unsigned int last_frame;
162 unsigned int last_dispatch;
163
164 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
165 unsigned int tex_age[R128_NR_TEX_HEAPS];
166 int ctx_owner;
167 int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */
168 int pfCurrentPage; /* which buffer is being displayed? */
169} drm_r128_sarea_t;
170
171/* WARNING: If you change any of these defines, make sure to change the
172 * defines in the Xserver file (xf86drmR128.h)
173 */
174
175/* Rage 128 specific ioctls
176 * The device specific ioctl range is 0x40 to 0x79.
177 */
178#define DRM_R128_INIT 0x00
179#define DRM_R128_CCE_START 0x01
180#define DRM_R128_CCE_STOP 0x02
181#define DRM_R128_CCE_RESET 0x03
182#define DRM_R128_CCE_IDLE 0x04
183/* 0x05 not used */
184#define DRM_R128_RESET 0x06
185#define DRM_R128_SWAP 0x07
186#define DRM_R128_CLEAR 0x08
187#define DRM_R128_VERTEX 0x09
188#define DRM_R128_INDICES 0x0a
189#define DRM_R128_BLIT 0x0b
190#define DRM_R128_DEPTH 0x0c
191#define DRM_R128_STIPPLE 0x0d
192/* 0x0e not used */
193#define DRM_R128_INDIRECT 0x0f
194#define DRM_R128_FULLSCREEN 0x10
195#define DRM_R128_CLEAR2 0x11
196#define DRM_R128_GETPARAM 0x12
197#define DRM_R128_FLIP 0x13
198
199#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
200#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
201#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
202#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
203#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
204/* 0x05 not used */
205#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
206#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
207#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
208#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
209#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
210#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
211#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
212#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
213/* 0x0e not used */
214#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
215#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
216#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
217#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
218#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
219
220typedef struct drm_r128_init {
221 enum {
222 R128_INIT_CCE = 0x01,
223 R128_CLEANUP_CCE = 0x02
224 } func;
225 unsigned long sarea_priv_offset;
226 int is_pci;
227 int cce_mode;
228 int cce_secure;
229 int ring_size;
230 int usec_timeout;
231
232 unsigned int fb_bpp;
233 unsigned int front_offset, front_pitch;
234 unsigned int back_offset, back_pitch;
235 unsigned int depth_bpp;
236 unsigned int depth_offset, depth_pitch;
237 unsigned int span_offset;
238
239 unsigned long fb_offset;
240 unsigned long mmio_offset;
241 unsigned long ring_offset;
242 unsigned long ring_rptr_offset;
243 unsigned long buffers_offset;
244 unsigned long agp_textures_offset;
245} drm_r128_init_t;
246
247typedef struct drm_r128_cce_stop {
248 int flush;
249 int idle;
250} drm_r128_cce_stop_t;
251
252typedef struct drm_r128_clear {
253 unsigned int flags;
254 unsigned int clear_color;
255 unsigned int clear_depth;
256 unsigned int color_mask;
257 unsigned int depth_mask;
258} drm_r128_clear_t;
259
260typedef struct drm_r128_vertex {
261 int prim;
262 int idx; /* Index of vertex buffer */
263 int count; /* Number of vertices in buffer */
264 int discard; /* Client finished with buffer? */
265} drm_r128_vertex_t;
266
267typedef struct drm_r128_indices {
268 int prim;
269 int idx;
270 int start;
271 int end;
272 int discard; /* Client finished with buffer? */
273} drm_r128_indices_t;
274
275typedef struct drm_r128_blit {
276 int idx;
277 int pitch;
278 int offset;
279 int format;
280 unsigned short x, y;
281 unsigned short width, height;
282} drm_r128_blit_t;
283
284typedef struct drm_r128_depth {
285 enum {
286 R128_WRITE_SPAN = 0x01,
287 R128_WRITE_PIXELS = 0x02,
288 R128_READ_SPAN = 0x03,
289 R128_READ_PIXELS = 0x04
290 } func;
291 int n;
292 int __user *x;
293 int __user *y;
294 unsigned int __user *buffer;
295 unsigned char __user *mask;
296} drm_r128_depth_t;
297
298typedef struct drm_r128_stipple {
299 unsigned int __user *mask;
300} drm_r128_stipple_t;
301
302typedef struct drm_r128_indirect {
303 int idx;
304 int start;
305 int end;
306 int discard;
307} drm_r128_indirect_t;
308
309typedef struct drm_r128_fullscreen {
310 enum {
311 R128_INIT_FULLSCREEN = 0x01,
312 R128_CLEANUP_FULLSCREEN = 0x02
313 } func;
314} drm_r128_fullscreen_t;
315
316/* 2.3: An ioctl to get parameters that aren't available to the 3d
317 * client any other way.
318 */
319#define R128_PARAM_IRQ_NR 1
320
321typedef struct drm_r128_getparam {
322 int param;
323 void __user *value;
324} drm_r128_getparam_t;
325
326#endif
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
deleted file mode 100644
index 4766c0f6a838..000000000000
--- a/include/drm/radeon_drm.h
+++ /dev/null
@@ -1,976 +0,0 @@
1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36#include <drm/drm.h>
37
38/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the X server file (radeon_sarea.h)
40 */
41#ifndef __RADEON_SAREA_DEFINES__
42#define __RADEON_SAREA_DEFINES__
43
44/* Old style state flags, required for sarea interface (1.1 and 1.2
45 * clears) and 1.2 drm_vertex2 ioctl.
46 */
47#define RADEON_UPLOAD_CONTEXT 0x00000001
48#define RADEON_UPLOAD_VERTFMT 0x00000002
49#define RADEON_UPLOAD_LINE 0x00000004
50#define RADEON_UPLOAD_BUMPMAP 0x00000008
51#define RADEON_UPLOAD_MASKS 0x00000010
52#define RADEON_UPLOAD_VIEWPORT 0x00000020
53#define RADEON_UPLOAD_SETUP 0x00000040
54#define RADEON_UPLOAD_TCL 0x00000080
55#define RADEON_UPLOAD_MISC 0x00000100
56#define RADEON_UPLOAD_TEX0 0x00000200
57#define RADEON_UPLOAD_TEX1 0x00000400
58#define RADEON_UPLOAD_TEX2 0x00000800
59#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
60#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
61#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
62#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
63#define RADEON_REQUIRE_QUIESCENCE 0x00010000
64#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
65#define RADEON_UPLOAD_ALL 0x003effff
66#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
67
68/* New style per-packet identifiers for use in cmd_buffer ioctl with
69 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
70 * state bits and the packet size:
71 */
72#define RADEON_EMIT_PP_MISC 0 /* context/7 */
73#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
74#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
75#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
76#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
77#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
78#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
79#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
80#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
81#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
82#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
83#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
84#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
85#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
86#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
87#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
88#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
89#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
90#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
91#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
92#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
93#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
94#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
95#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
96#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
97#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
98#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
99#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
100#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
101#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
102#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
103#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
104#define R200_EMIT_VAP_CTL 32 /* vap/1 */
105#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
106#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
107#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
108#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
109#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
110#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
111#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
112#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
113#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
114#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
115#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
116#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
117#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
118#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
119#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
120#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
121#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
122#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
123#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
124#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
125#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
126#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
127#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
128#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
129#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
130#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
131#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
132#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
133#define R200_EMIT_PP_CUBIC_FACES_0 61
134#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
135#define R200_EMIT_PP_CUBIC_FACES_1 63
136#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
137#define R200_EMIT_PP_CUBIC_FACES_2 65
138#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
139#define R200_EMIT_PP_CUBIC_FACES_3 67
140#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
141#define R200_EMIT_PP_CUBIC_FACES_4 69
142#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
143#define R200_EMIT_PP_CUBIC_FACES_5 71
144#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
145#define RADEON_EMIT_PP_TEX_SIZE_0 73
146#define RADEON_EMIT_PP_TEX_SIZE_1 74
147#define RADEON_EMIT_PP_TEX_SIZE_2 75
148#define R200_EMIT_RB3D_BLENDCOLOR 76
149#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
150#define RADEON_EMIT_PP_CUBIC_FACES_0 78
151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
152#define RADEON_EMIT_PP_CUBIC_FACES_1 80
153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
154#define RADEON_EMIT_PP_CUBIC_FACES_2 82
155#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
156#define R200_EMIT_PP_TRI_PERF_CNTL 84
157#define R200_EMIT_PP_AFS_0 85
158#define R200_EMIT_PP_AFS_1 86
159#define R200_EMIT_ATF_TFACTOR 87
160#define R200_EMIT_PP_TXCTLALL_0 88
161#define R200_EMIT_PP_TXCTLALL_1 89
162#define R200_EMIT_PP_TXCTLALL_2 90
163#define R200_EMIT_PP_TXCTLALL_3 91
164#define R200_EMIT_PP_TXCTLALL_4 92
165#define R200_EMIT_PP_TXCTLALL_5 93
166#define R200_EMIT_VAP_PVS_CNTL 94
167#define RADEON_MAX_STATE_PACKETS 95
168
169/* Commands understood by cmd_buffer ioctl. More can be added but
170 * obviously these can't be removed or changed:
171 */
172#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
173#define RADEON_CMD_SCALARS 2 /* emit scalar data */
174#define RADEON_CMD_VECTORS 3 /* emit vector data */
175#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
176#define RADEON_CMD_PACKET3 5 /* emit hw packet */
177#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
178#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
179#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
180 * doesn't make the cpu wait, just
181 * the graphics hardware */
182#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
183
184typedef union {
185 int i;
186 struct {
187 unsigned char cmd_type, pad0, pad1, pad2;
188 } header;
189 struct {
190 unsigned char cmd_type, packet_id, pad0, pad1;
191 } packet;
192 struct {
193 unsigned char cmd_type, offset, stride, count;
194 } scalars;
195 struct {
196 unsigned char cmd_type, offset, stride, count;
197 } vectors;
198 struct {
199 unsigned char cmd_type, addr_lo, addr_hi, count;
200 } veclinear;
201 struct {
202 unsigned char cmd_type, buf_idx, pad0, pad1;
203 } dma;
204 struct {
205 unsigned char cmd_type, flags, pad0, pad1;
206 } wait;
207} drm_radeon_cmd_header_t;
208
209#define RADEON_WAIT_2D 0x1
210#define RADEON_WAIT_3D 0x2
211
212/* Allowed parameters for R300_CMD_PACKET3
213 */
214#define R300_CMD_PACKET3_CLEAR 0
215#define R300_CMD_PACKET3_RAW 1
216
217/* Commands understood by cmd_buffer ioctl for R300.
218 * The interface has not been stabilized, so some of these may be removed
219 * and eventually reordered before stabilization.
220 */
221#define R300_CMD_PACKET0 1
222#define R300_CMD_VPU 2 /* emit vertex program upload */
223#define R300_CMD_PACKET3 3 /* emit a packet3 */
224#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
225#define R300_CMD_CP_DELAY 5
226#define R300_CMD_DMA_DISCARD 6
227#define R300_CMD_WAIT 7
228# define R300_WAIT_2D 0x1
229# define R300_WAIT_3D 0x2
230/* these two defines are DOING IT WRONG - however
231 * we have userspace which relies on using these.
232 * The wait interface is backwards compat new
233 * code should use the NEW_WAIT defines below
234 * THESE ARE NOT BIT FIELDS
235 */
236# define R300_WAIT_2D_CLEAN 0x3
237# define R300_WAIT_3D_CLEAN 0x4
238
239# define R300_NEW_WAIT_2D_3D 0x3
240# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
241# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
242# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
243
244#define R300_CMD_SCRATCH 8
245#define R300_CMD_R500FP 9
246
247typedef union {
248 unsigned int u;
249 struct {
250 unsigned char cmd_type, pad0, pad1, pad2;
251 } header;
252 struct {
253 unsigned char cmd_type, count, reglo, reghi;
254 } packet0;
255 struct {
256 unsigned char cmd_type, count, adrlo, adrhi;
257 } vpu;
258 struct {
259 unsigned char cmd_type, packet, pad0, pad1;
260 } packet3;
261 struct {
262 unsigned char cmd_type, packet;
263 unsigned short count; /* amount of packet2 to emit */
264 } delay;
265 struct {
266 unsigned char cmd_type, buf_idx, pad0, pad1;
267 } dma;
268 struct {
269 unsigned char cmd_type, flags, pad0, pad1;
270 } wait;
271 struct {
272 unsigned char cmd_type, reg, n_bufs, flags;
273 } scratch;
274 struct {
275 unsigned char cmd_type, count, adrlo, adrhi_flags;
276 } r500fp;
277} drm_r300_cmd_header_t;
278
279#define RADEON_FRONT 0x1
280#define RADEON_BACK 0x2
281#define RADEON_DEPTH 0x4
282#define RADEON_STENCIL 0x8
283#define RADEON_CLEAR_FASTZ 0x80000000
284#define RADEON_USE_HIERZ 0x40000000
285#define RADEON_USE_COMP_ZBUF 0x20000000
286
287#define R500FP_CONSTANT_TYPE (1 << 1)
288#define R500FP_CONSTANT_CLAMP (1 << 2)
289
290/* Primitive types
291 */
292#define RADEON_POINTS 0x1
293#define RADEON_LINES 0x2
294#define RADEON_LINE_STRIP 0x3
295#define RADEON_TRIANGLES 0x4
296#define RADEON_TRIANGLE_FAN 0x5
297#define RADEON_TRIANGLE_STRIP 0x6
298
299/* Vertex/indirect buffer size
300 */
301#define RADEON_BUFFER_SIZE 65536
302
303/* Byte offsets for indirect buffer data
304 */
305#define RADEON_INDEX_PRIM_OFFSET 20
306
307#define RADEON_SCRATCH_REG_OFFSET 32
308
309#define R600_SCRATCH_REG_OFFSET 256
310
311#define RADEON_NR_SAREA_CLIPRECTS 12
312
313/* There are 2 heaps (local/GART). Each region within a heap is a
314 * minimum of 64k, and there are at most 64 of them per heap.
315 */
316#define RADEON_LOCAL_TEX_HEAP 0
317#define RADEON_GART_TEX_HEAP 1
318#define RADEON_NR_TEX_HEAPS 2
319#define RADEON_NR_TEX_REGIONS 64
320#define RADEON_LOG_TEX_GRANULARITY 16
321
322#define RADEON_MAX_TEXTURE_LEVELS 12
323#define RADEON_MAX_TEXTURE_UNITS 3
324
325#define RADEON_MAX_SURFACES 8
326
327/* Blits have strict offset rules. All blit offset must be aligned on
328 * a 1K-byte boundary.
329 */
330#define RADEON_OFFSET_SHIFT 10
331#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
332#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
333
334#endif /* __RADEON_SAREA_DEFINES__ */
335
336typedef struct {
337 unsigned int red;
338 unsigned int green;
339 unsigned int blue;
340 unsigned int alpha;
341} radeon_color_regs_t;
342
343typedef struct {
344 /* Context state */
345 unsigned int pp_misc; /* 0x1c14 */
346 unsigned int pp_fog_color;
347 unsigned int re_solid_color;
348 unsigned int rb3d_blendcntl;
349 unsigned int rb3d_depthoffset;
350 unsigned int rb3d_depthpitch;
351 unsigned int rb3d_zstencilcntl;
352
353 unsigned int pp_cntl; /* 0x1c38 */
354 unsigned int rb3d_cntl;
355 unsigned int rb3d_coloroffset;
356 unsigned int re_width_height;
357 unsigned int rb3d_colorpitch;
358 unsigned int se_cntl;
359
360 /* Vertex format state */
361 unsigned int se_coord_fmt; /* 0x1c50 */
362
363 /* Line state */
364 unsigned int re_line_pattern; /* 0x1cd0 */
365 unsigned int re_line_state;
366
367 unsigned int se_line_width; /* 0x1db8 */
368
369 /* Bumpmap state */
370 unsigned int pp_lum_matrix; /* 0x1d00 */
371
372 unsigned int pp_rot_matrix_0; /* 0x1d58 */
373 unsigned int pp_rot_matrix_1;
374
375 /* Mask state */
376 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
377 unsigned int rb3d_ropcntl;
378 unsigned int rb3d_planemask;
379
380 /* Viewport state */
381 unsigned int se_vport_xscale; /* 0x1d98 */
382 unsigned int se_vport_xoffset;
383 unsigned int se_vport_yscale;
384 unsigned int se_vport_yoffset;
385 unsigned int se_vport_zscale;
386 unsigned int se_vport_zoffset;
387
388 /* Setup state */
389 unsigned int se_cntl_status; /* 0x2140 */
390
391 /* Misc state */
392 unsigned int re_top_left; /* 0x26c0 */
393 unsigned int re_misc;
394} drm_radeon_context_regs_t;
395
396typedef struct {
397 /* Zbias state */
398 unsigned int se_zbias_factor; /* 0x1dac */
399 unsigned int se_zbias_constant;
400} drm_radeon_context2_regs_t;
401
402/* Setup registers for each texture unit
403 */
404typedef struct {
405 unsigned int pp_txfilter;
406 unsigned int pp_txformat;
407 unsigned int pp_txoffset;
408 unsigned int pp_txcblend;
409 unsigned int pp_txablend;
410 unsigned int pp_tfactor;
411 unsigned int pp_border_color;
412} drm_radeon_texture_regs_t;
413
414typedef struct {
415 unsigned int start;
416 unsigned int finish;
417 unsigned int prim:8;
418 unsigned int stateidx:8;
419 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
420 unsigned int vc_format; /* vertex format */
421} drm_radeon_prim_t;
422
423typedef struct {
424 drm_radeon_context_regs_t context;
425 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
426 drm_radeon_context2_regs_t context2;
427 unsigned int dirty;
428} drm_radeon_state_t;
429
430typedef struct {
431 /* The channel for communication of state information to the
432 * kernel on firing a vertex buffer with either of the
433 * obsoleted vertex/index ioctls.
434 */
435 drm_radeon_context_regs_t context_state;
436 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
437 unsigned int dirty;
438 unsigned int vertsize;
439 unsigned int vc_format;
440
441 /* The current cliprects, or a subset thereof.
442 */
443 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
444 unsigned int nbox;
445
446 /* Counters for client-side throttling of rendering clients.
447 */
448 unsigned int last_frame;
449 unsigned int last_dispatch;
450 unsigned int last_clear;
451
452 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
453 1];
454 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
455 int ctx_owner;
456 int pfState; /* number of 3d windows (0,1,2ormore) */
457 int pfCurrentPage; /* which buffer is being displayed? */
458 int crtc2_base; /* CRTC2 frame offset */
459 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
460} drm_radeon_sarea_t;
461
462/* WARNING: If you change any of these defines, make sure to change the
463 * defines in the Xserver file (xf86drmRadeon.h)
464 *
465 * KW: actually it's illegal to change any of this (backwards compatibility).
466 */
467
468/* Radeon specific ioctls
469 * The device specific ioctl range is 0x40 to 0x79.
470 */
471#define DRM_RADEON_CP_INIT 0x00
472#define DRM_RADEON_CP_START 0x01
473#define DRM_RADEON_CP_STOP 0x02
474#define DRM_RADEON_CP_RESET 0x03
475#define DRM_RADEON_CP_IDLE 0x04
476#define DRM_RADEON_RESET 0x05
477#define DRM_RADEON_FULLSCREEN 0x06
478#define DRM_RADEON_SWAP 0x07
479#define DRM_RADEON_CLEAR 0x08
480#define DRM_RADEON_VERTEX 0x09
481#define DRM_RADEON_INDICES 0x0A
482#define DRM_RADEON_NOT_USED
483#define DRM_RADEON_STIPPLE 0x0C
484#define DRM_RADEON_INDIRECT 0x0D
485#define DRM_RADEON_TEXTURE 0x0E
486#define DRM_RADEON_VERTEX2 0x0F
487#define DRM_RADEON_CMDBUF 0x10
488#define DRM_RADEON_GETPARAM 0x11
489#define DRM_RADEON_FLIP 0x12
490#define DRM_RADEON_ALLOC 0x13
491#define DRM_RADEON_FREE 0x14
492#define DRM_RADEON_INIT_HEAP 0x15
493#define DRM_RADEON_IRQ_EMIT 0x16
494#define DRM_RADEON_IRQ_WAIT 0x17
495#define DRM_RADEON_CP_RESUME 0x18
496#define DRM_RADEON_SETPARAM 0x19
497#define DRM_RADEON_SURF_ALLOC 0x1a
498#define DRM_RADEON_SURF_FREE 0x1b
499/* KMS ioctl */
500#define DRM_RADEON_GEM_INFO 0x1c
501#define DRM_RADEON_GEM_CREATE 0x1d
502#define DRM_RADEON_GEM_MMAP 0x1e
503#define DRM_RADEON_GEM_PREAD 0x21
504#define DRM_RADEON_GEM_PWRITE 0x22
505#define DRM_RADEON_GEM_SET_DOMAIN 0x23
506#define DRM_RADEON_GEM_WAIT_IDLE 0x24
507#define DRM_RADEON_CS 0x26
508#define DRM_RADEON_INFO 0x27
509#define DRM_RADEON_GEM_SET_TILING 0x28
510#define DRM_RADEON_GEM_GET_TILING 0x29
511#define DRM_RADEON_GEM_BUSY 0x2a
512#define DRM_RADEON_GEM_VA 0x2b
513
514#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
515#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
516#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
517#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
518#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
519#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
520#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
521#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
522#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
523#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
524#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
525#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
526#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
527#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
528#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
529#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
530#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
531#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
532#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
533#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
534#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
535#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
536#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
537#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
538#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
539#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
540#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
541/* KMS */
542#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
543#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
544#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
545#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
546#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
547#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
548#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
549#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
550#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
551#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
552#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
553#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
554#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
555
556typedef struct drm_radeon_init {
557 enum {
558 RADEON_INIT_CP = 0x01,
559 RADEON_CLEANUP_CP = 0x02,
560 RADEON_INIT_R200_CP = 0x03,
561 RADEON_INIT_R300_CP = 0x04,
562 RADEON_INIT_R600_CP = 0x05
563 } func;
564 unsigned long sarea_priv_offset;
565 int is_pci;
566 int cp_mode;
567 int gart_size;
568 int ring_size;
569 int usec_timeout;
570
571 unsigned int fb_bpp;
572 unsigned int front_offset, front_pitch;
573 unsigned int back_offset, back_pitch;
574 unsigned int depth_bpp;
575 unsigned int depth_offset, depth_pitch;
576
577 unsigned long fb_offset;
578 unsigned long mmio_offset;
579 unsigned long ring_offset;
580 unsigned long ring_rptr_offset;
581 unsigned long buffers_offset;
582 unsigned long gart_textures_offset;
583} drm_radeon_init_t;
584
585typedef struct drm_radeon_cp_stop {
586 int flush;
587 int idle;
588} drm_radeon_cp_stop_t;
589
590typedef struct drm_radeon_fullscreen {
591 enum {
592 RADEON_INIT_FULLSCREEN = 0x01,
593 RADEON_CLEANUP_FULLSCREEN = 0x02
594 } func;
595} drm_radeon_fullscreen_t;
596
597#define CLEAR_X1 0
598#define CLEAR_Y1 1
599#define CLEAR_X2 2
600#define CLEAR_Y2 3
601#define CLEAR_DEPTH 4
602
603typedef union drm_radeon_clear_rect {
604 float f[5];
605 unsigned int ui[5];
606} drm_radeon_clear_rect_t;
607
608typedef struct drm_radeon_clear {
609 unsigned int flags;
610 unsigned int clear_color;
611 unsigned int clear_depth;
612 unsigned int color_mask;
613 unsigned int depth_mask; /* misnamed field: should be stencil */
614 drm_radeon_clear_rect_t __user *depth_boxes;
615} drm_radeon_clear_t;
616
617typedef struct drm_radeon_vertex {
618 int prim;
619 int idx; /* Index of vertex buffer */
620 int count; /* Number of vertices in buffer */
621 int discard; /* Client finished with buffer? */
622} drm_radeon_vertex_t;
623
624typedef struct drm_radeon_indices {
625 int prim;
626 int idx;
627 int start;
628 int end;
629 int discard; /* Client finished with buffer? */
630} drm_radeon_indices_t;
631
632/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
633 * - allows multiple primitives and state changes in a single ioctl
634 * - supports driver change to emit native primitives
635 */
636typedef struct drm_radeon_vertex2 {
637 int idx; /* Index of vertex buffer */
638 int discard; /* Client finished with buffer? */
639 int nr_states;
640 drm_radeon_state_t __user *state;
641 int nr_prims;
642 drm_radeon_prim_t __user *prim;
643} drm_radeon_vertex2_t;
644
645/* v1.3 - obsoletes drm_radeon_vertex2
646 * - allows arbitrarily large cliprect list
647 * - allows updating of tcl packet, vector and scalar state
648 * - allows memory-efficient description of state updates
649 * - allows state to be emitted without a primitive
650 * (for clears, ctx switches)
651 * - allows more than one dma buffer to be referenced per ioctl
652 * - supports tcl driver
653 * - may be extended in future versions with new cmd types, packets
654 */
655typedef struct drm_radeon_cmd_buffer {
656 int bufsz;
657 char __user *buf;
658 int nbox;
659 struct drm_clip_rect __user *boxes;
660} drm_radeon_cmd_buffer_t;
661
662typedef struct drm_radeon_tex_image {
663 unsigned int x, y; /* Blit coordinates */
664 unsigned int width, height;
665 const void __user *data;
666} drm_radeon_tex_image_t;
667
668typedef struct drm_radeon_texture {
669 unsigned int offset;
670 int pitch;
671 int format;
672 int width; /* Texture image coordinates */
673 int height;
674 drm_radeon_tex_image_t __user *image;
675} drm_radeon_texture_t;
676
677typedef struct drm_radeon_stipple {
678 unsigned int __user *mask;
679} drm_radeon_stipple_t;
680
681typedef struct drm_radeon_indirect {
682 int idx;
683 int start;
684 int end;
685 int discard;
686} drm_radeon_indirect_t;
687
688/* enum for card type parameters */
689#define RADEON_CARD_PCI 0
690#define RADEON_CARD_AGP 1
691#define RADEON_CARD_PCIE 2
692
693/* 1.3: An ioctl to get parameters that aren't available to the 3d
694 * client any other way.
695 */
696#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
697#define RADEON_PARAM_LAST_FRAME 2
698#define RADEON_PARAM_LAST_DISPATCH 3
699#define RADEON_PARAM_LAST_CLEAR 4
700/* Added with DRM version 1.6. */
701#define RADEON_PARAM_IRQ_NR 5
702#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
703/* Added with DRM version 1.8. */
704#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
705#define RADEON_PARAM_STATUS_HANDLE 8
706#define RADEON_PARAM_SAREA_HANDLE 9
707#define RADEON_PARAM_GART_TEX_HANDLE 10
708#define RADEON_PARAM_SCRATCH_OFFSET 11
709#define RADEON_PARAM_CARD_TYPE 12
710#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
711#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
712#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
713#define RADEON_PARAM_DEVICE_ID 16
714#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
715
716typedef struct drm_radeon_getparam {
717 int param;
718 void __user *value;
719} drm_radeon_getparam_t;
720
721/* 1.6: Set up a memory manager for regions of shared memory:
722 */
723#define RADEON_MEM_REGION_GART 1
724#define RADEON_MEM_REGION_FB 2
725
726typedef struct drm_radeon_mem_alloc {
727 int region;
728 int alignment;
729 int size;
730 int __user *region_offset; /* offset from start of fb or GART */
731} drm_radeon_mem_alloc_t;
732
733typedef struct drm_radeon_mem_free {
734 int region;
735 int region_offset;
736} drm_radeon_mem_free_t;
737
738typedef struct drm_radeon_mem_init_heap {
739 int region;
740 int size;
741 int start;
742} drm_radeon_mem_init_heap_t;
743
744/* 1.6: Userspace can request & wait on irq's:
745 */
746typedef struct drm_radeon_irq_emit {
747 int __user *irq_seq;
748} drm_radeon_irq_emit_t;
749
750typedef struct drm_radeon_irq_wait {
751 int irq_seq;
752} drm_radeon_irq_wait_t;
753
754/* 1.10: Clients tell the DRM where they think the framebuffer is located in
755 * the card's address space, via a new generic ioctl to set parameters
756 */
757
758typedef struct drm_radeon_setparam {
759 unsigned int param;
760 __s64 value;
761} drm_radeon_setparam_t;
762
763#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
764#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
765#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
766#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
767#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
768#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
769/* 1.14: Clients can allocate/free a surface
770 */
771typedef struct drm_radeon_surface_alloc {
772 unsigned int address;
773 unsigned int size;
774 unsigned int flags;
775} drm_radeon_surface_alloc_t;
776
777typedef struct drm_radeon_surface_free {
778 unsigned int address;
779} drm_radeon_surface_free_t;
780
781#define DRM_RADEON_VBLANK_CRTC1 1
782#define DRM_RADEON_VBLANK_CRTC2 2
783
784/*
785 * Kernel modesetting world below.
786 */
787#define RADEON_GEM_DOMAIN_CPU 0x1
788#define RADEON_GEM_DOMAIN_GTT 0x2
789#define RADEON_GEM_DOMAIN_VRAM 0x4
790
791struct drm_radeon_gem_info {
792 uint64_t gart_size;
793 uint64_t vram_size;
794 uint64_t vram_visible;
795};
796
797#define RADEON_GEM_NO_BACKING_STORE 1
798
799struct drm_radeon_gem_create {
800 uint64_t size;
801 uint64_t alignment;
802 uint32_t handle;
803 uint32_t initial_domain;
804 uint32_t flags;
805};
806
807#define RADEON_TILING_MACRO 0x1
808#define RADEON_TILING_MICRO 0x2
809#define RADEON_TILING_SWAP_16BIT 0x4
810#define RADEON_TILING_SWAP_32BIT 0x8
811/* this object requires a surface when mapped - i.e. front buffer */
812#define RADEON_TILING_SURFACE 0x10
813#define RADEON_TILING_MICRO_SQUARE 0x20
814#define RADEON_TILING_EG_BANKW_SHIFT 8
815#define RADEON_TILING_EG_BANKW_MASK 0xf
816#define RADEON_TILING_EG_BANKH_SHIFT 12
817#define RADEON_TILING_EG_BANKH_MASK 0xf
818#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
819#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
820#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
821#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
822#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
823#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
824
825struct drm_radeon_gem_set_tiling {
826 uint32_t handle;
827 uint32_t tiling_flags;
828 uint32_t pitch;
829};
830
831struct drm_radeon_gem_get_tiling {
832 uint32_t handle;
833 uint32_t tiling_flags;
834 uint32_t pitch;
835};
836
837struct drm_radeon_gem_mmap {
838 uint32_t handle;
839 uint32_t pad;
840 uint64_t offset;
841 uint64_t size;
842 uint64_t addr_ptr;
843};
844
845struct drm_radeon_gem_set_domain {
846 uint32_t handle;
847 uint32_t read_domains;
848 uint32_t write_domain;
849};
850
851struct drm_radeon_gem_wait_idle {
852 uint32_t handle;
853 uint32_t pad;
854};
855
856struct drm_radeon_gem_busy {
857 uint32_t handle;
858 uint32_t domain;
859};
860
861struct drm_radeon_gem_pread {
862 /** Handle for the object being read. */
863 uint32_t handle;
864 uint32_t pad;
865 /** Offset into the object to read from */
866 uint64_t offset;
867 /** Length of data to read */
868 uint64_t size;
869 /** Pointer to write the data into. */
870 /* void *, but pointers are not 32/64 compatible */
871 uint64_t data_ptr;
872};
873
874struct drm_radeon_gem_pwrite {
875 /** Handle for the object being written to. */
876 uint32_t handle;
877 uint32_t pad;
878 /** Offset into the object to write to */
879 uint64_t offset;
880 /** Length of data to write */
881 uint64_t size;
882 /** Pointer to read the data from. */
883 /* void *, but pointers are not 32/64 compatible */
884 uint64_t data_ptr;
885};
886
887#define RADEON_VA_MAP 1
888#define RADEON_VA_UNMAP 2
889
890#define RADEON_VA_RESULT_OK 0
891#define RADEON_VA_RESULT_ERROR 1
892#define RADEON_VA_RESULT_VA_EXIST 2
893
894#define RADEON_VM_PAGE_VALID (1 << 0)
895#define RADEON_VM_PAGE_READABLE (1 << 1)
896#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
897#define RADEON_VM_PAGE_SYSTEM (1 << 3)
898#define RADEON_VM_PAGE_SNOOPED (1 << 4)
899
900struct drm_radeon_gem_va {
901 uint32_t handle;
902 uint32_t operation;
903 uint32_t vm_id;
904 uint32_t flags;
905 uint64_t offset;
906};
907
908#define RADEON_CHUNK_ID_RELOCS 0x01
909#define RADEON_CHUNK_ID_IB 0x02
910#define RADEON_CHUNK_ID_FLAGS 0x03
911#define RADEON_CHUNK_ID_CONST_IB 0x04
912
913/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
914#define RADEON_CS_KEEP_TILING_FLAGS 0x01
915#define RADEON_CS_USE_VM 0x02
916/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
917#define RADEON_CS_RING_GFX 0
918#define RADEON_CS_RING_COMPUTE 1
919/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
920/* 0 = normal, + = higher priority, - = lower priority */
921
922struct drm_radeon_cs_chunk {
923 uint32_t chunk_id;
924 uint32_t length_dw;
925 uint64_t chunk_data;
926};
927
928/* drm_radeon_cs_reloc.flags */
929
930struct drm_radeon_cs_reloc {
931 uint32_t handle;
932 uint32_t read_domains;
933 uint32_t write_domain;
934 uint32_t flags;
935};
936
937struct drm_radeon_cs {
938 uint32_t num_chunks;
939 uint32_t cs_id;
940 /* this points to uint64_t * which point to cs chunks */
941 uint64_t chunks;
942 /* updates to the limits after this CS ioctl */
943 uint64_t gart_limit;
944 uint64_t vram_limit;
945};
946
947#define RADEON_INFO_DEVICE_ID 0x00
948#define RADEON_INFO_NUM_GB_PIPES 0x01
949#define RADEON_INFO_NUM_Z_PIPES 0x02
950#define RADEON_INFO_ACCEL_WORKING 0x03
951#define RADEON_INFO_CRTC_FROM_ID 0x04
952#define RADEON_INFO_ACCEL_WORKING2 0x05
953#define RADEON_INFO_TILING_CONFIG 0x06
954#define RADEON_INFO_WANT_HYPERZ 0x07
955#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */
956#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
957#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
958#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
959#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
960#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
961/* virtual address start, va < start are reserved by the kernel */
962#define RADEON_INFO_VA_START 0x0e
963/* maximum size of ib using the virtual memory cs */
964#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
965/* max pipes - needed for compute shaders */
966#define RADEON_INFO_MAX_PIPES 0x10
967/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
968#define RADEON_INFO_TIMESTAMP 0x11
969
970struct drm_radeon_info {
971 uint32_t request;
972 uint32_t pad;
973 uint64_t value;
974};
975
976#endif
diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h
deleted file mode 100644
index 818d49be2e6e..000000000000
--- a/include/drm/savage_drm.h
+++ /dev/null
@@ -1,210 +0,0 @@
1/* savage_drm.h -- Public header for the savage driver
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef __SAVAGE_DRM_H__
27#define __SAVAGE_DRM_H__
28
29#ifndef __SAVAGE_SAREA_DEFINES__
30#define __SAVAGE_SAREA_DEFINES__
31
32/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
33 * regions, subject to a minimum region size of (1<<16) == 64k.
34 *
35 * Clients may subdivide regions internally, but when sharing between
36 * clients, the region size is the minimum granularity.
37 */
38
39#define SAVAGE_CARD_HEAP 0
40#define SAVAGE_AGP_HEAP 1
41#define SAVAGE_NR_TEX_HEAPS 2
42#define SAVAGE_NR_TEX_REGIONS 16
43#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
44
45#endif /* __SAVAGE_SAREA_DEFINES__ */
46
47typedef struct _drm_savage_sarea {
48 /* LRU lists for texture memory in agp space and on the card.
49 */
50 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
51 1];
52 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
53
54 /* Mechanism to validate card state.
55 */
56 int ctxOwner;
57} drm_savage_sarea_t, *drm_savage_sarea_ptr;
58
59/* Savage-specific ioctls
60 */
61#define DRM_SAVAGE_BCI_INIT 0x00
62#define DRM_SAVAGE_BCI_CMDBUF 0x01
63#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
64#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
65
66#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
67#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
68#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
69#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
70
71#define SAVAGE_DMA_PCI 1
72#define SAVAGE_DMA_AGP 3
73typedef struct drm_savage_init {
74 enum {
75 SAVAGE_INIT_BCI = 1,
76 SAVAGE_CLEANUP_BCI = 2
77 } func;
78 unsigned int sarea_priv_offset;
79
80 /* some parameters */
81 unsigned int cob_size;
82 unsigned int bci_threshold_lo, bci_threshold_hi;
83 unsigned int dma_type;
84
85 /* frame buffer layout */
86 unsigned int fb_bpp;
87 unsigned int front_offset, front_pitch;
88 unsigned int back_offset, back_pitch;
89 unsigned int depth_bpp;
90 unsigned int depth_offset, depth_pitch;
91
92 /* local textures */
93 unsigned int texture_offset;
94 unsigned int texture_size;
95
96 /* physical locations of non-permanent maps */
97 unsigned long status_offset;
98 unsigned long buffers_offset;
99 unsigned long agp_textures_offset;
100 unsigned long cmd_dma_offset;
101} drm_savage_init_t;
102
103typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
104typedef struct drm_savage_cmdbuf {
105 /* command buffer in client's address space */
106 drm_savage_cmd_header_t __user *cmd_addr;
107 unsigned int size; /* size of the command buffer in 64bit units */
108
109 unsigned int dma_idx; /* DMA buffer index to use */
110 int discard; /* discard DMA buffer when done */
111 /* vertex buffer in client's address space */
112 unsigned int __user *vb_addr;
113 unsigned int vb_size; /* size of client vertex buffer in bytes */
114 unsigned int vb_stride; /* stride of vertices in 32bit words */
115 /* boxes in client's address space */
116 struct drm_clip_rect __user *box_addr;
117 unsigned int nbox; /* number of clipping boxes */
118} drm_savage_cmdbuf_t;
119
120#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
121#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
122#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
123typedef struct drm_savage_event {
124 unsigned int count;
125 unsigned int flags;
126} drm_savage_event_emit_t, drm_savage_event_wait_t;
127
128/* Commands for the cmdbuf ioctl
129 */
130#define SAVAGE_CMD_STATE 0 /* a range of state registers */
131#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
132#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
133#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
134#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
135#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
136#define SAVAGE_CMD_SWAP 6 /* swap buffers */
137
138/* Primitive types
139*/
140#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
141#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
142#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
143#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
144 * shading on s3d */
145
146/* Skip flags (vertex format)
147 */
148#define SAVAGE_SKIP_Z 0x01
149#define SAVAGE_SKIP_W 0x02
150#define SAVAGE_SKIP_C0 0x04
151#define SAVAGE_SKIP_C1 0x08
152#define SAVAGE_SKIP_S0 0x10
153#define SAVAGE_SKIP_T0 0x20
154#define SAVAGE_SKIP_ST0 0x30
155#define SAVAGE_SKIP_S1 0x40
156#define SAVAGE_SKIP_T1 0x80
157#define SAVAGE_SKIP_ST1 0xc0
158#define SAVAGE_SKIP_ALL_S3D 0x3f
159#define SAVAGE_SKIP_ALL_S4 0xff
160
161/* Buffer names for clear command
162 */
163#define SAVAGE_FRONT 0x1
164#define SAVAGE_BACK 0x2
165#define SAVAGE_DEPTH 0x4
166
167/* 64-bit command header
168 */
169union drm_savage_cmd_header {
170 struct {
171 unsigned char cmd; /* command */
172 unsigned char pad0;
173 unsigned short pad1;
174 unsigned short pad2;
175 unsigned short pad3;
176 } cmd; /* generic */
177 struct {
178 unsigned char cmd;
179 unsigned char global; /* need idle engine? */
180 unsigned short count; /* number of consecutive registers */
181 unsigned short start; /* first register */
182 unsigned short pad3;
183 } state; /* SAVAGE_CMD_STATE */
184 struct {
185 unsigned char cmd;
186 unsigned char prim; /* primitive type */
187 unsigned short skip; /* vertex format (skip flags) */
188 unsigned short count; /* number of vertices */
189 unsigned short start; /* first vertex in DMA/vertex buffer */
190 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
191 struct {
192 unsigned char cmd;
193 unsigned char prim;
194 unsigned short skip;
195 unsigned short count; /* number of indices that follow */
196 unsigned short pad3;
197 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
198 struct {
199 unsigned char cmd;
200 unsigned char pad0;
201 unsigned short pad1;
202 unsigned int flags;
203 } clear0; /* SAVAGE_CMD_CLEAR */
204 struct {
205 unsigned int mask;
206 unsigned int value;
207 } clear1; /* SAVAGE_CMD_CLEAR data */
208};
209
210#endif
diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h
deleted file mode 100644
index df3763222d73..000000000000
--- a/include/drm/sis_drm.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
2/*
3 * Copyright 2005 Eric Anholt
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27#ifndef __SIS_DRM_H__
28#define __SIS_DRM_H__
29
30/* SiS specific ioctls */
31#define NOT_USED_0_3
32#define DRM_SIS_FB_ALLOC 0x04
33#define DRM_SIS_FB_FREE 0x05
34#define NOT_USED_6_12
35#define DRM_SIS_AGP_INIT 0x13
36#define DRM_SIS_AGP_ALLOC 0x14
37#define DRM_SIS_AGP_FREE 0x15
38#define DRM_SIS_FB_INIT 0x16
39
40#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t)
41#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
42#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t)
43#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t)
44#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
45#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
46/*
47#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
48#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49)
49#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50)
50*/
51
52typedef struct {
53 int context;
54 unsigned long offset;
55 unsigned long size;
56 unsigned long free;
57} drm_sis_mem_t;
58
59typedef struct {
60 unsigned long offset, size;
61} drm_sis_agp_t;
62
63typedef struct {
64 unsigned long offset, size;
65} drm_sis_fb_t;
66
67struct sis_file_private {
68 struct list_head obj_list;
69};
70
71#endif /* __SIS_DRM_H__ */
diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h
deleted file mode 100644
index 8b0533ccbd5a..000000000000
--- a/include/drm/via_drm.h
+++ /dev/null
@@ -1,281 +0,0 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _VIA_DRM_H_
25#define _VIA_DRM_H_
26
27#include <drm/drm.h>
28
29/* WARNING: These defines must be the same as what the Xserver uses.
30 * if you change them, you must change the defines in the Xserver.
31 */
32
33#ifndef _VIA_DEFINES_
34#define _VIA_DEFINES_
35
36#ifndef __KERNEL__
37#include "via_drmclient.h"
38#endif
39
40#define VIA_NR_SAREA_CLIPRECTS 8
41#define VIA_NR_XVMC_PORTS 10
42#define VIA_NR_XVMC_LOCKS 5
43#define VIA_MAX_CACHELINE_SIZE 64
44#define XVMCLOCKPTR(saPriv,lockNo) \
45 ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
46 (VIA_MAX_CACHELINE_SIZE - 1)) & \
47 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
48 VIA_MAX_CACHELINE_SIZE*(lockNo)))
49
50/* Each region is a minimum of 64k, and there are at most 64 of them.
51 */
52#define VIA_NR_TEX_REGIONS 64
53#define VIA_LOG_MIN_TEX_REGION_SIZE 16
54#endif
55
56#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
57#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
58#define VIA_UPLOAD_CTX 0x4
59#define VIA_UPLOAD_BUFFERS 0x8
60#define VIA_UPLOAD_TEX0 0x10
61#define VIA_UPLOAD_TEX1 0x20
62#define VIA_UPLOAD_CLIPRECTS 0x40
63#define VIA_UPLOAD_ALL 0xff
64
65/* VIA specific ioctls */
66#define DRM_VIA_ALLOCMEM 0x00
67#define DRM_VIA_FREEMEM 0x01
68#define DRM_VIA_AGP_INIT 0x02
69#define DRM_VIA_FB_INIT 0x03
70#define DRM_VIA_MAP_INIT 0x04
71#define DRM_VIA_DEC_FUTEX 0x05
72#define NOT_USED
73#define DRM_VIA_DMA_INIT 0x07
74#define DRM_VIA_CMDBUFFER 0x08
75#define DRM_VIA_FLUSH 0x09
76#define DRM_VIA_PCICMD 0x0a
77#define DRM_VIA_CMDBUF_SIZE 0x0b
78#define NOT_USED
79#define DRM_VIA_WAIT_IRQ 0x0d
80#define DRM_VIA_DMA_BLIT 0x0e
81#define DRM_VIA_BLIT_SYNC 0x0f
82
83#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
84#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
85#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
86#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
87#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
88#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
89#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
90#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
91#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
92#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
93#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
94 drm_via_cmdbuf_size_t)
95#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
96#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
97#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
98
99/* Indices into buf.Setup where various bits of state are mirrored per
100 * context and per buffer. These can be fired at the card as a unit,
101 * or in a piecewise fashion as required.
102 */
103
104#define VIA_TEX_SETUP_SIZE 8
105
106/* Flags for clear ioctl
107 */
108#define VIA_FRONT 0x1
109#define VIA_BACK 0x2
110#define VIA_DEPTH 0x4
111#define VIA_STENCIL 0x8
112#define VIA_MEM_VIDEO 0 /* matches drm constant */
113#define VIA_MEM_AGP 1 /* matches drm constant */
114#define VIA_MEM_SYSTEM 2
115#define VIA_MEM_MIXED 3
116#define VIA_MEM_UNKNOWN 4
117
118typedef struct {
119 __u32 offset;
120 __u32 size;
121} drm_via_agp_t;
122
123typedef struct {
124 __u32 offset;
125 __u32 size;
126} drm_via_fb_t;
127
128typedef struct {
129 __u32 context;
130 __u32 type;
131 __u32 size;
132 unsigned long index;
133 unsigned long offset;
134} drm_via_mem_t;
135
136typedef struct _drm_via_init {
137 enum {
138 VIA_INIT_MAP = 0x01,
139 VIA_CLEANUP_MAP = 0x02
140 } func;
141
142 unsigned long sarea_priv_offset;
143 unsigned long fb_offset;
144 unsigned long mmio_offset;
145 unsigned long agpAddr;
146} drm_via_init_t;
147
148typedef struct _drm_via_futex {
149 enum {
150 VIA_FUTEX_WAIT = 0x00,
151 VIA_FUTEX_WAKE = 0X01
152 } func;
153 __u32 ms;
154 __u32 lock;
155 __u32 val;
156} drm_via_futex_t;
157
158typedef struct _drm_via_dma_init {
159 enum {
160 VIA_INIT_DMA = 0x01,
161 VIA_CLEANUP_DMA = 0x02,
162 VIA_DMA_INITIALIZED = 0x03
163 } func;
164
165 unsigned long offset;
166 unsigned long size;
167 unsigned long reg_pause_addr;
168} drm_via_dma_init_t;
169
170typedef struct _drm_via_cmdbuffer {
171 char __user *buf;
172 unsigned long size;
173} drm_via_cmdbuffer_t;
174
175/* Warning: If you change the SAREA structure you must change the Xserver
176 * structure as well */
177
178typedef struct _drm_via_tex_region {
179 unsigned char next, prev; /* indices to form a circular LRU */
180 unsigned char inUse; /* owned by a client, or free? */
181 int age; /* tracked by clients to update local LRU's */
182} drm_via_tex_region_t;
183
184typedef struct _drm_via_sarea {
185 unsigned int dirty;
186 unsigned int nbox;
187 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
188 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
189 int texAge; /* last time texture was uploaded */
190 int ctxOwner; /* last context to upload state */
191 int vertexPrim;
192
193 /*
194 * Below is for XvMC.
195 * We want the lock integers alone on, and aligned to, a cache line.
196 * Therefore this somewhat strange construct.
197 */
198
199 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
200
201 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
202 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
203 unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
204
205 /* Used by the 3d driver only at this point, for pageflipping:
206 */
207 unsigned int pfCurrentOffset;
208} drm_via_sarea_t;
209
210typedef struct _drm_via_cmdbuf_size {
211 enum {
212 VIA_CMDBUF_SPACE = 0x01,
213 VIA_CMDBUF_LAG = 0x02
214 } func;
215 int wait;
216 __u32 size;
217} drm_via_cmdbuf_size_t;
218
219typedef enum {
220 VIA_IRQ_ABSOLUTE = 0x0,
221 VIA_IRQ_RELATIVE = 0x1,
222 VIA_IRQ_SIGNAL = 0x10000000,
223 VIA_IRQ_FORCE_SEQUENCE = 0x20000000
224} via_irq_seq_type_t;
225
226#define VIA_IRQ_FLAGS_MASK 0xF0000000
227
228enum drm_via_irqs {
229 drm_via_irq_hqv0 = 0,
230 drm_via_irq_hqv1,
231 drm_via_irq_dma0_dd,
232 drm_via_irq_dma0_td,
233 drm_via_irq_dma1_dd,
234 drm_via_irq_dma1_td,
235 drm_via_irq_num
236};
237
238struct drm_via_wait_irq_request {
239 unsigned irq;
240 via_irq_seq_type_t type;
241 __u32 sequence;
242 __u32 signal;
243};
244
245typedef union drm_via_irqwait {
246 struct drm_via_wait_irq_request request;
247 struct drm_wait_vblank_reply reply;
248} drm_via_irqwait_t;
249
250typedef struct drm_via_blitsync {
251 __u32 sync_handle;
252 unsigned engine;
253} drm_via_blitsync_t;
254
255/* - * Below,"flags" is currently unused but will be used for possible future
256 * extensions like kernel space bounce buffers for bad alignments and
257 * blit engine busy-wait polling for better latency in the absence of
258 * interrupts.
259 */
260
261typedef struct drm_via_dmablit {
262 __u32 num_lines;
263 __u32 line_length;
264
265 __u32 fb_addr;
266 __u32 fb_stride;
267
268 unsigned char *mem_addr;
269 __u32 mem_stride;
270
271 __u32 flags;
272 int to_fb;
273
274 drm_via_blitsync_t sync;
275} drm_via_dmablit_t;
276
277struct via_file_private {
278 struct list_head obj_list;
279};
280
281#endif /* _VIA_DRM_H_ */
diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h
deleted file mode 100644
index bcb0912afe7a..000000000000
--- a/include/drm/vmwgfx_drm.h
+++ /dev/null
@@ -1,790 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#ifndef __VMWGFX_DRM_H__
29#define __VMWGFX_DRM_H__
30
31#define DRM_VMW_MAX_SURFACE_FACES 6
32#define DRM_VMW_MAX_MIP_LEVELS 24
33
34
35#define DRM_VMW_GET_PARAM 0
36#define DRM_VMW_ALLOC_DMABUF 1
37#define DRM_VMW_UNREF_DMABUF 2
38#define DRM_VMW_CURSOR_BYPASS 3
39/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/
40#define DRM_VMW_CONTROL_STREAM 4
41#define DRM_VMW_CLAIM_STREAM 5
42#define DRM_VMW_UNREF_STREAM 6
43/* guarded by DRM_VMW_PARAM_3D == 1 */
44#define DRM_VMW_CREATE_CONTEXT 7
45#define DRM_VMW_UNREF_CONTEXT 8
46#define DRM_VMW_CREATE_SURFACE 9
47#define DRM_VMW_UNREF_SURFACE 10
48#define DRM_VMW_REF_SURFACE 11
49#define DRM_VMW_EXECBUF 12
50#define DRM_VMW_GET_3D_CAP 13
51#define DRM_VMW_FENCE_WAIT 14
52#define DRM_VMW_FENCE_SIGNALED 15
53#define DRM_VMW_FENCE_UNREF 16
54#define DRM_VMW_FENCE_EVENT 17
55#define DRM_VMW_PRESENT 18
56#define DRM_VMW_PRESENT_READBACK 19
57#define DRM_VMW_UPDATE_LAYOUT 20
58
59/*************************************************************************/
60/**
61 * DRM_VMW_GET_PARAM - get device information.
62 *
63 * DRM_VMW_PARAM_FIFO_OFFSET:
64 * Offset to use to map the first page of the FIFO read-only.
65 * The fifo is mapped using the mmap() system call on the drm device.
66 *
67 * DRM_VMW_PARAM_OVERLAY_IOCTL:
68 * Does the driver support the overlay ioctl.
69 */
70
71#define DRM_VMW_PARAM_NUM_STREAMS 0
72#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
73#define DRM_VMW_PARAM_3D 2
74#define DRM_VMW_PARAM_HW_CAPS 3
75#define DRM_VMW_PARAM_FIFO_CAPS 4
76#define DRM_VMW_PARAM_MAX_FB_SIZE 5
77#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
78
79/**
80 * struct drm_vmw_getparam_arg
81 *
82 * @value: Returned value. //Out
83 * @param: Parameter to query. //In.
84 *
85 * Argument to the DRM_VMW_GET_PARAM Ioctl.
86 */
87
88struct drm_vmw_getparam_arg {
89 uint64_t value;
90 uint32_t param;
91 uint32_t pad64;
92};
93
94/*************************************************************************/
95/**
96 * DRM_VMW_CREATE_CONTEXT - Create a host context.
97 *
98 * Allocates a device unique context id, and queues a create context command
99 * for the host. Does not wait for host completion.
100 */
101
102/**
103 * struct drm_vmw_context_arg
104 *
105 * @cid: Device unique context ID.
106 *
107 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
108 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
109 */
110
111struct drm_vmw_context_arg {
112 int32_t cid;
113 uint32_t pad64;
114};
115
116/*************************************************************************/
117/**
118 * DRM_VMW_UNREF_CONTEXT - Create a host context.
119 *
120 * Frees a global context id, and queues a destroy host command for the host.
121 * Does not wait for host completion. The context ID can be used directly
122 * in the command stream and shows up as the same context ID on the host.
123 */
124
125/*************************************************************************/
126/**
127 * DRM_VMW_CREATE_SURFACE - Create a host suface.
128 *
129 * Allocates a device unique surface id, and queues a create surface command
130 * for the host. Does not wait for host completion. The surface ID can be
131 * used directly in the command stream and shows up as the same surface
132 * ID on the host.
133 */
134
135/**
136 * struct drm_wmv_surface_create_req
137 *
138 * @flags: Surface flags as understood by the host.
139 * @format: Surface format as understood by the host.
140 * @mip_levels: Number of mip levels for each face.
141 * An unused face should have 0 encoded.
142 * @size_addr: Address of a user-space array of sruct drm_vmw_size
143 * cast to an uint64_t for 32-64 bit compatibility.
144 * The size of the array should equal the total number of mipmap levels.
145 * @shareable: Boolean whether other clients (as identified by file descriptors)
146 * may reference this surface.
147 * @scanout: Boolean whether the surface is intended to be used as a
148 * scanout.
149 *
150 * Input data to the DRM_VMW_CREATE_SURFACE Ioctl.
151 * Output data from the DRM_VMW_REF_SURFACE Ioctl.
152 */
153
154struct drm_vmw_surface_create_req {
155 uint32_t flags;
156 uint32_t format;
157 uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES];
158 uint64_t size_addr;
159 int32_t shareable;
160 int32_t scanout;
161};
162
163/**
164 * struct drm_wmv_surface_arg
165 *
166 * @sid: Surface id of created surface or surface to destroy or reference.
167 *
168 * Output data from the DRM_VMW_CREATE_SURFACE Ioctl.
169 * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl.
170 * Input argument to the DRM_VMW_REF_SURFACE Ioctl.
171 */
172
173struct drm_vmw_surface_arg {
174 int32_t sid;
175 uint32_t pad64;
176};
177
178/**
179 * struct drm_vmw_size ioctl.
180 *
181 * @width - mip level width
182 * @height - mip level height
183 * @depth - mip level depth
184 *
185 * Description of a mip level.
186 * Input data to the DRM_WMW_CREATE_SURFACE Ioctl.
187 */
188
189struct drm_vmw_size {
190 uint32_t width;
191 uint32_t height;
192 uint32_t depth;
193 uint32_t pad64;
194};
195
196/**
197 * union drm_vmw_surface_create_arg
198 *
199 * @rep: Output data as described above.
200 * @req: Input data as described above.
201 *
202 * Argument to the DRM_VMW_CREATE_SURFACE Ioctl.
203 */
204
205union drm_vmw_surface_create_arg {
206 struct drm_vmw_surface_arg rep;
207 struct drm_vmw_surface_create_req req;
208};
209
210/*************************************************************************/
211/**
212 * DRM_VMW_REF_SURFACE - Reference a host surface.
213 *
214 * Puts a reference on a host surface with a give sid, as previously
215 * returned by the DRM_VMW_CREATE_SURFACE ioctl.
216 * A reference will make sure the surface isn't destroyed while we hold
217 * it and will allow the calling client to use the surface ID in the command
218 * stream.
219 *
220 * On successful return, the Ioctl returns the surface information given
221 * in the DRM_VMW_CREATE_SURFACE ioctl.
222 */
223
224/**
225 * union drm_vmw_surface_reference_arg
226 *
227 * @rep: Output data as described above.
228 * @req: Input data as described above.
229 *
230 * Argument to the DRM_VMW_REF_SURFACE Ioctl.
231 */
232
233union drm_vmw_surface_reference_arg {
234 struct drm_vmw_surface_create_req rep;
235 struct drm_vmw_surface_arg req;
236};
237
238/*************************************************************************/
239/**
240 * DRM_VMW_UNREF_SURFACE - Unreference a host surface.
241 *
242 * Clear a reference previously put on a host surface.
243 * When all references are gone, including the one implicitly placed
244 * on creation,
245 * a destroy surface command will be queued for the host.
246 * Does not wait for completion.
247 */
248
249/*************************************************************************/
250/**
251 * DRM_VMW_EXECBUF
252 *
253 * Submit a command buffer for execution on the host, and return a
254 * fence seqno that when signaled, indicates that the command buffer has
255 * executed.
256 */
257
258/**
259 * struct drm_vmw_execbuf_arg
260 *
261 * @commands: User-space address of a command buffer cast to an uint64_t.
262 * @command-size: Size in bytes of the command buffer.
263 * @throttle-us: Sleep until software is less than @throttle_us
264 * microseconds ahead of hardware. The driver may round this value
265 * to the nearest kernel tick.
266 * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
267 * uint64_t.
268 * @version: Allows expanding the execbuf ioctl parameters without breaking
269 * backwards compatibility, since user-space will always tell the kernel
270 * which version it uses.
271 * @flags: Execbuf flags. None currently.
272 *
273 * Argument to the DRM_VMW_EXECBUF Ioctl.
274 */
275
276#define DRM_VMW_EXECBUF_VERSION 1
277
278struct drm_vmw_execbuf_arg {
279 uint64_t commands;
280 uint32_t command_size;
281 uint32_t throttle_us;
282 uint64_t fence_rep;
283 uint32_t version;
284 uint32_t flags;
285};
286
287/**
288 * struct drm_vmw_fence_rep
289 *
290 * @handle: Fence object handle for fence associated with a command submission.
291 * @mask: Fence flags relevant for this fence object.
292 * @seqno: Fence sequence number in fifo. A fence object with a lower
293 * seqno will signal the EXEC flag before a fence object with a higher
294 * seqno. This can be used by user-space to avoid kernel calls to determine
295 * whether a fence has signaled the EXEC flag. Note that @seqno will
296 * wrap at 32-bit.
297 * @passed_seqno: The highest seqno number processed by the hardware
298 * so far. This can be used to mark user-space fence objects as signaled, and
299 * to determine whether a fence seqno might be stale.
300 * @error: This member should've been set to -EFAULT on submission.
301 * The following actions should be take on completion:
302 * error == -EFAULT: Fence communication failed. The host is synchronized.
303 * Use the last fence id read from the FIFO fence register.
304 * error != 0 && error != -EFAULT:
305 * Fence submission failed. The host is synchronized. Use the fence_seq member.
306 * error == 0: All is OK, The host may not be synchronized.
307 * Use the fence_seq member.
308 *
309 * Input / Output data to the DRM_VMW_EXECBUF Ioctl.
310 */
311
312struct drm_vmw_fence_rep {
313 uint32_t handle;
314 uint32_t mask;
315 uint32_t seqno;
316 uint32_t passed_seqno;
317 uint32_t pad64;
318 int32_t error;
319};
320
321/*************************************************************************/
322/**
323 * DRM_VMW_ALLOC_DMABUF
324 *
325 * Allocate a DMA buffer that is visible also to the host.
326 * NOTE: The buffer is
327 * identified by a handle and an offset, which are private to the guest, but
328 * useable in the command stream. The guest kernel may translate these
329 * and patch up the command stream accordingly. In the future, the offset may
330 * be zero at all times, or it may disappear from the interface before it is
331 * fixed.
332 *
333 * The DMA buffer may stay user-space mapped in the guest at all times,
334 * and is thus suitable for sub-allocation.
335 *
336 * DMA buffers are mapped using the mmap() syscall on the drm device.
337 */
338
339/**
340 * struct drm_vmw_alloc_dmabuf_req
341 *
342 * @size: Required minimum size of the buffer.
343 *
344 * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl.
345 */
346
347struct drm_vmw_alloc_dmabuf_req {
348 uint32_t size;
349 uint32_t pad64;
350};
351
352/**
353 * struct drm_vmw_dmabuf_rep
354 *
355 * @map_handle: Offset to use in the mmap() call used to map the buffer.
356 * @handle: Handle unique to this buffer. Used for unreferencing.
357 * @cur_gmr_id: GMR id to use in the command stream when this buffer is
358 * referenced. See not above.
359 * @cur_gmr_offset: Offset to use in the command stream when this buffer is
360 * referenced. See note above.
361 *
362 * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl.
363 */
364
365struct drm_vmw_dmabuf_rep {
366 uint64_t map_handle;
367 uint32_t handle;
368 uint32_t cur_gmr_id;
369 uint32_t cur_gmr_offset;
370 uint32_t pad64;
371};
372
373/**
374 * union drm_vmw_dmabuf_arg
375 *
376 * @req: Input data as described above.
377 * @rep: Output data as described above.
378 *
379 * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl.
380 */
381
382union drm_vmw_alloc_dmabuf_arg {
383 struct drm_vmw_alloc_dmabuf_req req;
384 struct drm_vmw_dmabuf_rep rep;
385};
386
387/*************************************************************************/
388/**
389 * DRM_VMW_UNREF_DMABUF - Free a DMA buffer.
390 *
391 */
392
393/**
394 * struct drm_vmw_unref_dmabuf_arg
395 *
396 * @handle: Handle indicating what buffer to free. Obtained from the
397 * DRM_VMW_ALLOC_DMABUF Ioctl.
398 *
399 * Argument to the DRM_VMW_UNREF_DMABUF Ioctl.
400 */
401
402struct drm_vmw_unref_dmabuf_arg {
403 uint32_t handle;
404 uint32_t pad64;
405};
406
407/*************************************************************************/
408/**
409 * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams.
410 *
411 * This IOCTL controls the overlay units of the svga device.
412 * The SVGA overlay units does not work like regular hardware units in
413 * that they do not automaticaly read back the contents of the given dma
414 * buffer. But instead only read back for each call to this ioctl, and
415 * at any point between this call being made and a following call that
416 * either changes the buffer or disables the stream.
417 */
418
419/**
420 * struct drm_vmw_rect
421 *
422 * Defines a rectangle. Used in the overlay ioctl to define
423 * source and destination rectangle.
424 */
425
426struct drm_vmw_rect {
427 int32_t x;
428 int32_t y;
429 uint32_t w;
430 uint32_t h;
431};
432
433/**
434 * struct drm_vmw_control_stream_arg
435 *
436 * @stream_id: Stearm to control
437 * @enabled: If false all following arguments are ignored.
438 * @handle: Handle to buffer for getting data from.
439 * @format: Format of the overlay as understood by the host.
440 * @width: Width of the overlay.
441 * @height: Height of the overlay.
442 * @size: Size of the overlay in bytes.
443 * @pitch: Array of pitches, the two last are only used for YUV12 formats.
444 * @offset: Offset from start of dma buffer to overlay.
445 * @src: Source rect, must be within the defined area above.
446 * @dst: Destination rect, x and y may be negative.
447 *
448 * Argument to the DRM_VMW_CONTROL_STREAM Ioctl.
449 */
450
451struct drm_vmw_control_stream_arg {
452 uint32_t stream_id;
453 uint32_t enabled;
454
455 uint32_t flags;
456 uint32_t color_key;
457
458 uint32_t handle;
459 uint32_t offset;
460 int32_t format;
461 uint32_t size;
462 uint32_t width;
463 uint32_t height;
464 uint32_t pitch[3];
465
466 uint32_t pad64;
467 struct drm_vmw_rect src;
468 struct drm_vmw_rect dst;
469};
470
471/*************************************************************************/
472/**
473 * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass.
474 *
475 */
476
477#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
478#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
479
480/**
481 * struct drm_vmw_cursor_bypass_arg
482 *
483 * @flags: Flags.
484 * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed.
485 * @xpos: X position of cursor.
486 * @ypos: Y position of cursor.
487 * @xhot: X hotspot.
488 * @yhot: Y hotspot.
489 *
490 * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl.
491 */
492
493struct drm_vmw_cursor_bypass_arg {
494 uint32_t flags;
495 uint32_t crtc_id;
496 int32_t xpos;
497 int32_t ypos;
498 int32_t xhot;
499 int32_t yhot;
500};
501
502/*************************************************************************/
503/**
504 * DRM_VMW_CLAIM_STREAM - Claim a single stream.
505 */
506
507/**
508 * struct drm_vmw_context_arg
509 *
510 * @stream_id: Device unique context ID.
511 *
512 * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl.
513 * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl.
514 */
515
516struct drm_vmw_stream_arg {
517 uint32_t stream_id;
518 uint32_t pad64;
519};
520
521/*************************************************************************/
522/**
523 * DRM_VMW_UNREF_STREAM - Unclaim a stream.
524 *
525 * Return a single stream that was claimed by this process. Also makes
526 * sure that the stream has been stopped.
527 */
528
529/*************************************************************************/
530/**
531 * DRM_VMW_GET_3D_CAP
532 *
533 * Read 3D capabilities from the FIFO
534 *
535 */
536
537/**
538 * struct drm_vmw_get_3d_cap_arg
539 *
540 * @buffer: Pointer to a buffer for capability data, cast to an uint64_t
541 * @size: Max size to copy
542 *
543 * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL
544 * ioctls.
545 */
546
547struct drm_vmw_get_3d_cap_arg {
548 uint64_t buffer;
549 uint32_t max_size;
550 uint32_t pad64;
551};
552
553/*************************************************************************/
554/**
555 * DRM_VMW_FENCE_WAIT
556 *
557 * Waits for a fence object to signal. The wait is interruptible, so that
558 * signals may be delivered during the interrupt. The wait may timeout,
559 * in which case the calls returns -EBUSY. If the wait is restarted,
560 * that is restarting without resetting @cookie_valid to zero,
561 * the timeout is computed from the first call.
562 *
563 * The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait
564 * on:
565 * DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command
566 * stream
567 * have executed.
568 * DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish
569 * commands
570 * in the buffer given to the EXECBUF ioctl returning the fence object handle
571 * are available to user-space.
572 *
573 * DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the
574 * fenc wait ioctl returns 0, the fence object has been unreferenced after
575 * the wait.
576 */
577
578#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
579#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
580
581#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
582
583/**
584 * struct drm_vmw_fence_wait_arg
585 *
586 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
587 * @cookie_valid: Must be reset to 0 on first call. Left alone on restart.
588 * @kernel_cookie: Set to 0 on first call. Left alone on restart.
589 * @timeout_us: Wait timeout in microseconds. 0 for indefinite timeout.
590 * @lazy: Set to 1 if timing is not critical. Allow more than a kernel tick
591 * before returning.
592 * @flags: Fence flags to wait on.
593 * @wait_options: Options that control the behaviour of the wait ioctl.
594 *
595 * Input argument to the DRM_VMW_FENCE_WAIT ioctl.
596 */
597
598struct drm_vmw_fence_wait_arg {
599 uint32_t handle;
600 int32_t cookie_valid;
601 uint64_t kernel_cookie;
602 uint64_t timeout_us;
603 int32_t lazy;
604 int32_t flags;
605 int32_t wait_options;
606 int32_t pad64;
607};
608
609/*************************************************************************/
610/**
611 * DRM_VMW_FENCE_SIGNALED
612 *
613 * Checks if a fence object is signaled..
614 */
615
616/**
617 * struct drm_vmw_fence_signaled_arg
618 *
619 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
620 * @flags: Fence object flags input to DRM_VMW_FENCE_SIGNALED ioctl
621 * @signaled: Out: Flags signaled.
622 * @sequence: Out: Highest sequence passed so far. Can be used to signal the
623 * EXEC flag of user-space fence objects.
624 *
625 * Input/Output argument to the DRM_VMW_FENCE_SIGNALED and DRM_VMW_FENCE_UNREF
626 * ioctls.
627 */
628
629struct drm_vmw_fence_signaled_arg {
630 uint32_t handle;
631 uint32_t flags;
632 int32_t signaled;
633 uint32_t passed_seqno;
634 uint32_t signaled_flags;
635 uint32_t pad64;
636};
637
638/*************************************************************************/
639/**
640 * DRM_VMW_FENCE_UNREF
641 *
642 * Unreferences a fence object, and causes it to be destroyed if there are no
643 * other references to it.
644 *
645 */
646
647/**
648 * struct drm_vmw_fence_arg
649 *
650 * @handle: Fence object handle as returned by the DRM_VMW_EXECBUF ioctl.
651 *
652 * Input/Output argument to the DRM_VMW_FENCE_UNREF ioctl..
653 */
654
655struct drm_vmw_fence_arg {
656 uint32_t handle;
657 uint32_t pad64;
658};
659
660
661/*************************************************************************/
662/**
663 * DRM_VMW_FENCE_EVENT
664 *
665 * Queues an event on a fence to be delivered on the drm character device
666 * when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag.
667 * Optionally the approximate time when the fence signaled is
668 * given by the event.
669 */
670
671/*
672 * The event type
673 */
674#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
675
676struct drm_vmw_event_fence {
677 struct drm_event base;
678 uint64_t user_data;
679 uint32_t tv_sec;
680 uint32_t tv_usec;
681};
682
683/*
684 * Flags that may be given to the command.
685 */
686/* Request fence signaled time on the event. */
687#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
688
689/**
690 * struct drm_vmw_fence_event_arg
691 *
692 * @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if
693 * the fence is not supposed to be referenced by user-space.
694 * @user_info: Info to be delivered with the event.
695 * @handle: Attach the event to this fence only.
696 * @flags: A set of flags as defined above.
697 */
698struct drm_vmw_fence_event_arg {
699 uint64_t fence_rep;
700 uint64_t user_data;
701 uint32_t handle;
702 uint32_t flags;
703};
704
705
706/*************************************************************************/
707/**
708 * DRM_VMW_PRESENT
709 *
710 * Executes an SVGA present on a given fb for a given surface. The surface
711 * is placed on the framebuffer. Cliprects are given relative to the given
712 * point (the point disignated by dest_{x|y}).
713 *
714 */
715
716/**
717 * struct drm_vmw_present_arg
718 * @fb_id: framebuffer id to present / read back from.
719 * @sid: Surface id to present from.
720 * @dest_x: X placement coordinate for surface.
721 * @dest_y: Y placement coordinate for surface.
722 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
723 * @num_clips: Number of cliprects given relative to the framebuffer origin,
724 * in the same coordinate space as the frame buffer.
725 * @pad64: Unused 64-bit padding.
726 *
727 * Input argument to the DRM_VMW_PRESENT ioctl.
728 */
729
730struct drm_vmw_present_arg {
731 uint32_t fb_id;
732 uint32_t sid;
733 int32_t dest_x;
734 int32_t dest_y;
735 uint64_t clips_ptr;
736 uint32_t num_clips;
737 uint32_t pad64;
738};
739
740
741/*************************************************************************/
742/**
743 * DRM_VMW_PRESENT_READBACK
744 *
745 * Executes an SVGA present readback from a given fb to the dma buffer
746 * currently bound as the fb. If there is no dma buffer bound to the fb,
747 * an error will be returned.
748 *
749 */
750
751/**
752 * struct drm_vmw_present_arg
753 * @fb_id: fb_id to present / read back from.
754 * @num_clips: Number of cliprects.
755 * @clips_ptr: Pointer to an array of clip rects cast to an uint64_t.
756 * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t.
757 * If this member is NULL, then the ioctl should not return a fence.
758 */
759
760struct drm_vmw_present_readback_arg {
761 uint32_t fb_id;
762 uint32_t num_clips;
763 uint64_t clips_ptr;
764 uint64_t fence_rep;
765};
766
767/*************************************************************************/
768/**
769 * DRM_VMW_UPDATE_LAYOUT - Update layout
770 *
771 * Updates the preferred modes and connection status for connectors. The
772 * command consists of one drm_vmw_update_layout_arg pointing to an array
773 * of num_outputs drm_vmw_rect's.
774 */
775
776/**
777 * struct drm_vmw_update_layout_arg
778 *
779 * @num_outputs: number of active connectors
780 * @rects: pointer to array of drm_vmw_rect cast to an uint64_t
781 *
782 * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
783 */
784struct drm_vmw_update_layout_arg {
785 uint32_t num_outputs;
786 uint32_t pad64;
787 uint64_t rects;
788};
789
790#endif
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