3 files changed, 35 insertions, 3 deletions

diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index ced362533e3c..617d87ae2b1a 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -214,8 +214,6 @@ struct drm_display_info {
         u32 color_formats;
 
         u8 cea_rev;
-
-        char *raw_edid; /* if any */
 };
 
 struct drm_framebuffer_funcs {
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h
index ee5389d22c64..1d1a858a203d 100644
--- a/include/drm/drm_sarea.h
+++ b/include/drm/drm_sarea.h
@@ -37,6 +37,8 @@
 /* SAREA area needs to be at least a page */
 #if defined(__alpha__)
 #define SAREA_MAX                       0x2000U
+#elif defined(__mips__)
+#define SAREA_MAX                       0x4000U
 #elif defined(__ia64__)
 #define SAREA_MAX                       0x10000U        /* 64kB */
 #else
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 8cc70837f929..d8a79bf59ae7 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -203,6 +203,9 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GEM_WAIT       0x2c
 #define DRM_I915_GEM_CONTEXT_CREATE     0x2d
 #define DRM_I915_GEM_CONTEXT_DESTROY    0x2e
+#define DRM_I915_GEM_SET_CACHEING       0x2f
+#define DRM_I915_GEM_GET_CACHEING       0x30
+#define DRM_I915_REG_READ               0x31
 
 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -227,6 +230,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_SET_CACHEING         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)
+#define DRM_IOCTL_I915_GEM_GET_CACHEING         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)
 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
@@ -249,6 +254,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_WAIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE       DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY      DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+#define DRM_IOCTL_I915_REG_READ                 DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -305,6 +311,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_LLC               17
 #define I915_PARAM_HAS_ALIASING_PPGTT    18
 #define I915_PARAM_HAS_WAIT_TIMEOUT      19
+#define I915_PARAM_HAS_SEMAPHORES        20
 
 typedef struct drm_i915_getparam {
         int param;
@@ -698,10 +705,31 @@ struct drm_i915_gem_busy {
         /** Handle of the buffer to check for busy */
         __u32 handle;
 
-        /** Return busy status (1 if busy, 0 if idle) */
+        /** Return busy status (1 if busy, 0 if idle).
+         * The high word is used to indicate on which rings the object
+         * currently resides:
+         *  16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
+         */
         __u32 busy;
 };
 
+#define I915_CACHEING_NONE              0
+#define I915_CACHEING_CACHED            1
+
+struct drm_i915_gem_cacheing {
+        /**
+         * Handle of the buffer to set/get the cacheing level of. */
+        __u32 handle;
+
+        /**
+         * Cacheing level to apply or return value
+         *
+         * bits0-15 are for generic cacheing control (i.e. the above defined
+         * values). bits16-31 are reserved for platform-specific variations
+         * (e.g. l3$ caching on gen7). */
+        __u32 cacheing;
+};
+
 #define I915_TILING_NONE        0
 #define I915_TILING_X           1
 #define I915_TILING_Y           2
@@ -918,4 +946,8 @@ struct drm_i915_gem_context_destroy {
         __u32 pad;
 };
 
+struct drm_i915_reg_read {
+        __u64 offset;
+        __u64 val; /* Return value */
+};
 #endif                          /* _I915_DRM_H_ */