5 files changed, 190 insertions, 0 deletions
diff --git a/include/drm/drm_buffer.h b/include/drm/drm_buffer.h
new file mode 100644
index 000000000000..322dbff3f861
--- /dev/null
+++ b/include/drm/drm_buffer.h
@@ -0,0 +1,148 @@
+/**************************************************************************
+ *
+ * Copyright 2010 Pauli Nieminen.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ **************************************************************************/
+/*
+ * Multipart buffer for coping data which is larger than the page size.
+ *
+ * Authors:
+ * Pauli Nieminen <suokkos-at-gmail-dot-com>
+ */
+#ifndef _DRM_BUFFER_H_
+#define _DRM_BUFFER_H_
+#include "drmP.h"
+struct drm_buffer {
+        int iterator;
+        int size;
+        char *data[];
+};
+/**
+ * Return the index of page that buffer is currently pointing at.
+ */
+static inline int drm_buffer_page(struct drm_buffer *buf)
+{
+        return buf->iterator / PAGE_SIZE;
+}
+/**
+ * Return the index of the current byte in the page
+ */
+static inline int drm_buffer_index(struct drm_buffer *buf)
+{
+        return buf->iterator & (PAGE_SIZE - 1);
+}
+/**
+ * Return number of bytes that is left to process
+ */
+static inline int drm_buffer_unprocessed(struct drm_buffer *buf)
+{
+        return buf->size - buf->iterator;
+}
+/**
+ * Advance the buffer iterator number of bytes that is given.
+ */
+static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes)
+{
+        buf->iterator += bytes;
+}
+/**
+ * Allocate the drm buffer object.
+ *
+ *   buf: A pointer to a pointer where the object is stored.
+ *   size: The number of bytes to allocate.
+ */
+extern int drm_buffer_alloc(struct drm_buffer **buf, int size);
+/**
+ * Copy the user data to the begin of the buffer and reset the processing
+ * iterator.
+ *
+ *   user_data: A pointer the data that is copied to the buffer.
+ *   size: The Number of bytes to copy.
+ */
+extern int drm_buffer_copy_from_user(struct drm_buffer *buf,
+                void __user *user_data, int size);
+/**
+ * Free the drm buffer object
+ */
+extern void drm_buffer_free(struct drm_buffer *buf);
+/**
+ * Read an object from buffer that may be split to multiple parts. If object
+ * is not split function just returns the pointer to object in buffer. But in
+ * case of split object data is copied to given stack object that is suplied
+ * by caller.
+ *
+ * The processing location of the buffer is also advanced to the next byte
+ * after the object.
+ *
+ *   objsize: The size of the objet in bytes.
+ *   stack_obj: A pointer to a memory location where object can be copied.
+ */
+extern void *drm_buffer_read_object(struct drm_buffer *buf,
+                int objsize, void *stack_obj);
+/**
+ * Returns the pointer to the dword which is offset number of elements from the
+ * current processing location.
+ *
+ * Caller must make sure that dword is not split in the buffer. This
+ * requirement is easily met if all the sizes of objects in buffer are
+ * multiples of dword and PAGE_SIZE is multiple dword.
+ *
+ * Call to this function doesn't change the processing location.
+ *
+ *   offset: The index of the dword relative to the internat iterator.
+ */
+static inline void *drm_buffer_pointer_to_dword(struct drm_buffer *buffer,
+                int offset)
+{
+        int iter = buffer->iterator + offset * 4;
+        return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
+}
+/**
+ * Returns the pointer to the dword which is offset number of elements from
+ * the current processing location.
+ *
+ * Call to this function doesn't change the processing location.
+ *
+ *   offset: The index of the byte relative to the internat iterator.
+ */
+static inline void *drm_buffer_pointer_to_byte(struct drm_buffer *buffer,
+                int offset)
+{
+        int iter = buffer->iterator + offset;
+        return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
+}
+#endif
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index fdf43abc36db..1347524a8e30 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,4 +801,6 @@ extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
                                bool interlaced, int margins);
 extern int drm_add_modes_noedid(struct drm_connector *connector,
                                int hdisplay, int vdisplay);
+extern bool drm_edid_is_valid(struct edid *edid);
 #endif /* __DRM_CRTC_H__ */
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index d33c3e038606..b4209898f115 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -201,4 +201,7 @@ struct edid {
 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
+/* define the number of Extension EDID block */
+#define DRM_MAX_EDID_EXT_NUM 4
 #endif /* __DRM_EDID_H__ */
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e6f3b120f51a..676104b7818c 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -141,6 +141,41 @@
        {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
        {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -558,4 +593,5 @@
        {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
        {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
        {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
+        {0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
        {0, 0, 0}
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 39537f3cf98a..81e614bf2dc3 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -808,6 +808,7 @@ struct drm_radeon_gem_create {
 #define RADEON_TILING_SWAP_32BIT  0x8
 #define RADEON_TILING_SURFACE     0x10 /* this object requires a surface
                                        * when mapped - i.e. front buffer */
+#define RADEON_TILING_MICRO_SQUARE 0x20
 struct drm_radeon_gem_set_tiling {
        uint32_t        handle;

diff --git a/include/drm/drm_buffer.h b/include/drm/drm_buffer.h new file mode 100644 index 000000000000..322dbff3f861 --- /dev/null +++ b/include/drm/drm_buffer.h
@@ -0,0 +1,148 @@
		1	/**************************************************************************
		2	*
		3	* Copyright 2010 Pauli Nieminen.
		4	* All Rights Reserved.
		5	*
		6	* Permission is hereby granted, free of charge, to any person obtaining a
		7	* copy of this software and associated documentation files (the
		8	* "Software"), to deal in the Software without restriction, including
		9	* without limitation the rights to use, copy, modify, merge, publish,
		10	* distribute, sub license, and/or sell copies of the Software, and to
		11	* permit persons to whom the Software is furnished to do so, subject to
		12	* the following conditions:
		13	*
		14	* The above copyright notice and this permission notice (including the
		15	* next paragraph) shall be included in all copies or substantial portions
		16	* of the Software.
		17	*
		18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
		21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
		22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
		23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
		24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
		25	*
		26	*
		27	**************************************************************************/
		28	/*
		29	* Multipart buffer for coping data which is larger than the page size.
		30	*
		31	* Authors:
		32	* Pauli Nieminen <suokkos-at-gmail-dot-com>
		33	*/
		34
		35	#ifndef _DRM_BUFFER_H_
		36	#define _DRM_BUFFER_H_
		37
		38	#include "drmP.h"
		39
		40	struct drm_buffer {
		41	int iterator;
		42	int size;
		43	char *data[];
		44	};
		45
		46
		47	/**
		48	* Return the index of page that buffer is currently pointing at.
		49	*/
		50	static inline int drm_buffer_page(struct drm_buffer *buf)
		51	{
		52	return buf->iterator / PAGE_SIZE;
		53	}
		54	/**
		55	* Return the index of the current byte in the page
		56	*/
		57	static inline int drm_buffer_index(struct drm_buffer *buf)
		58	{
		59	return buf->iterator & (PAGE_SIZE - 1);
		60	}
		61	/**
		62	* Return number of bytes that is left to process
		63	*/
		64	static inline int drm_buffer_unprocessed(struct drm_buffer *buf)
		65	{
		66	return buf->size - buf->iterator;
		67	}
		68
		69	/**
		70	* Advance the buffer iterator number of bytes that is given.
		71	*/
		72	static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes)
		73	{
		74	buf->iterator += bytes;
		75	}
		76
		77	/**
		78	* Allocate the drm buffer object.
		79	*
		80	* buf: A pointer to a pointer where the object is stored.
		81	* size: The number of bytes to allocate.
		82	*/
		83	extern int drm_buffer_alloc(struct drm_buffer **buf, int size);
		84
		85	/**
		86	* Copy the user data to the begin of the buffer and reset the processing
		87	* iterator.
		88	*
		89	* user_data: A pointer the data that is copied to the buffer.
		90	* size: The Number of bytes to copy.
		91	*/
		92	extern int drm_buffer_copy_from_user(struct drm_buffer *buf,
		93	void __user *user_data, int size);
		94
		95	/**
		96	* Free the drm buffer object
		97	*/
		98	extern void drm_buffer_free(struct drm_buffer *buf);
		99
		100	/**
		101	* Read an object from buffer that may be split to multiple parts. If object
		102	* is not split function just returns the pointer to object in buffer. But in
		103	* case of split object data is copied to given stack object that is suplied
		104	* by caller.
		105	*
		106	* The processing location of the buffer is also advanced to the next byte
		107	* after the object.
		108	*
		109	* objsize: The size of the objet in bytes.
		110	* stack_obj: A pointer to a memory location where object can be copied.
		111	*/
		112	extern void drm_buffer_read_object(struct drm_buffer buf,
		113	int objsize, void *stack_obj);
		114
		115	/**
		116	* Returns the pointer to the dword which is offset number of elements from the
		117	* current processing location.
		118	*
		119	* Caller must make sure that dword is not split in the buffer. This
		120	* requirement is easily met if all the sizes of objects in buffer are
		121	* multiples of dword and PAGE_SIZE is multiple dword.
		122	*
		123	* Call to this function doesn't change the processing location.
		124	*
		125	* offset: The index of the dword relative to the internat iterator.
		126	*/
		127	static inline void drm_buffer_pointer_to_dword(struct drm_buffer buffer,
		128	int offset)
		129	{
		130	int iter = buffer->iterator + offset * 4;
		131	return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
		132	}
		133	/**
		134	* Returns the pointer to the dword which is offset number of elements from
		135	* the current processing location.
		136	*
		137	* Call to this function doesn't change the processing location.
		138	*
		139	* offset: The index of the byte relative to the internat iterator.
		140	*/
		141	static inline void drm_buffer_pointer_to_byte(struct drm_buffer buffer,
		142	int offset)
		143	{
		144	int iter = buffer->iterator + offset;
		145	return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
		146	}
		147
		148	#endif


diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index fdf43abc36db..1347524a8e30 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h
@@ -801,4 +801,6 @@ extern struct drm_display_mode drm_gtf_mode(struct drm_device dev,
801	bool interlaced, int margins);	801	bool interlaced, int margins);
802	extern int drm_add_modes_noedid(struct drm_connector *connector,	802	extern int drm_add_modes_noedid(struct drm_connector *connector,
803	int hdisplay, int vdisplay);	803	int hdisplay, int vdisplay);
		804
		805	extern bool drm_edid_is_valid(struct edid *edid);
804	#endif /* __DRM_CRTC_H__ */	806	#endif /* __DRM_CRTC_H__ */


diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index d33c3e038606..b4209898f115 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h
@@ -201,4 +201,7 @@ struct edid {
201		201
202	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))	202	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
203		203
		204	/* define the number of Extension EDID block */
		205	#define DRM_MAX_EDID_EXT_NUM 4
		206
204	#endif /* __DRM_EDID_H__ */	207	#endif /* __DRM_EDID_H__ */


diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h index e6f3b120f51a..676104b7818c 100644 --- a/include/drm/drm_pciids.h +++ b/include/drm/drm_pciids.h
@@ -141,6 +141,41 @@
141	{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \	141	{0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
142	{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \	142	{0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
143	{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \	143	{0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410\|RADEON_NEW_MEMMAP}, \
		144	{0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		145	{0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		146	{0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		147	{0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		148	{0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		149	{0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		150	{0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK\|RADEON_NEW_MEMMAP}, \
		151	{0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK\|RADEON_NEW_MEMMAP}, \
		152	{0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS\|RADEON_NEW_MEMMAP}, \
		153	{0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		154	{0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		155	{0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_NEW_MEMMAP}, \
		156	{0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_NEW_MEMMAP}, \
		157	{0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		158	{0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_NEW_MEMMAP}, \
		159	{0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_NEW_MEMMAP}, \
		160	{0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER\|RADEON_NEW_MEMMAP}, \
		161	{0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		162	{0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		163	{0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		164	{0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		165	{0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		166	{0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		167	{0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		168	{0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD\|RADEON_NEW_MEMMAP}, \
		169	{0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		170	{0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		171	{0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		172	{0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
		173	{0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
		174	{0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
		175	{0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
		176	{0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
		177	{0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
		178	{0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR\|RADEON_NEW_MEMMAP}, \
144	{0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \	179	{0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_NEW_MEMMAP}, \
145	{0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \	180	{0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
146	{0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \	181	{0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520\|RADEON_IS_MOBILITY\|RADEON_NEW_MEMMAP}, \
@@ -558,4 +593,5 @@
558	{0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \	593	{0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
559	{0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \	594	{0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
560	{0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \	595	{0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
		596	{0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
561	{0, 0, 0}	597	{0, 0, 0}


diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 39537f3cf98a..81e614bf2dc3 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h
@@ -808,6 +808,7 @@ struct drm_radeon_gem_create {
808	#define RADEON_TILING_SWAP_32BIT 0x8	808	#define RADEON_TILING_SWAP_32BIT 0x8
809	#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface	809	#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
810	* when mapped - i.e. front buffer */	810	* when mapped - i.e. front buffer */
		811	#define RADEON_TILING_MICRO_SQUARE 0x20
811		812
812	struct drm_radeon_gem_set_tiling {	813	struct drm_radeon_gem_set_tiling {
813	uint32_t handle;	814	uint32_t handle;