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-rw-r--r--include/drm/drm.h21
-rw-r--r--include/drm/drmP.h145
-rw-r--r--include/drm/drm_crtc.h6
-rw-r--r--include/drm/drm_crtc_helper.h3
-rw-r--r--include/drm/drm_mode.h153
-rw-r--r--include/drm/drm_os_linux.h19
-rw-r--r--include/drm/drm_pciids.h115
-rw-r--r--include/drm/i915_drm.h140
-rw-r--r--include/drm/mga_drm.h18
-rw-r--r--include/drm/radeon_drm.h9
-rw-r--r--include/drm/via_drm.h42
11 files changed, 449 insertions, 222 deletions
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 8e77357334ad..7cb50bdde46d 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -36,8 +36,7 @@
36#ifndef _DRM_H_ 36#ifndef _DRM_H_
37#define _DRM_H_ 37#define _DRM_H_
38 38
39#if defined(__KERNEL__) 39#include <linux/types.h>
40#endif
41#include <asm/ioctl.h> /* For _IO* macros */ 40#include <asm/ioctl.h> /* For _IO* macros */
42#define DRM_IOCTL_NR(n) _IOC_NR(n) 41#define DRM_IOCTL_NR(n) _IOC_NR(n)
43#define DRM_IOC_VOID _IOC_NONE 42#define DRM_IOC_VOID _IOC_NONE
@@ -497,8 +496,8 @@ union drm_wait_vblank {
497 * \sa drmModesetCtl(). 496 * \sa drmModesetCtl().
498 */ 497 */
499struct drm_modeset_ctl { 498struct drm_modeset_ctl {
500 uint32_t crtc; 499 __u32 crtc;
501 uint32_t cmd; 500 __u32 cmd;
502}; 501};
503 502
504/** 503/**
@@ -574,29 +573,29 @@ struct drm_set_version {
574/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 573/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
575struct drm_gem_close { 574struct drm_gem_close {
576 /** Handle of the object to be closed. */ 575 /** Handle of the object to be closed. */
577 uint32_t handle; 576 __u32 handle;
578 uint32_t pad; 577 __u32 pad;
579}; 578};
580 579
581/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 580/** DRM_IOCTL_GEM_FLINK ioctl argument type */
582struct drm_gem_flink { 581struct drm_gem_flink {
583 /** Handle for the object being named */ 582 /** Handle for the object being named */
584 uint32_t handle; 583 __u32 handle;
585 584
586 /** Returned global name */ 585 /** Returned global name */
587 uint32_t name; 586 __u32 name;
588}; 587};
589 588
590/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 589/** DRM_IOCTL_GEM_OPEN ioctl argument type */
591struct drm_gem_open { 590struct drm_gem_open {
592 /** Name of object being opened */ 591 /** Name of object being opened */
593 uint32_t name; 592 __u32 name;
594 593
595 /** Returned handle for the object */ 594 /** Returned handle for the object */
596 uint32_t handle; 595 __u32 handle;
597 596
598 /** Returned size of the object */ 597 /** Returned size of the object */
599 uint64_t size; 598 __u64 size;
600}; 599};
601 600
602#include "drm_mode.h" 601#include "drm_mode.h"
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index e5f4ae989abf..c8c422151431 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -281,16 +281,16 @@ typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
281 281
282struct drm_ioctl_desc { 282struct drm_ioctl_desc {
283 unsigned int cmd; 283 unsigned int cmd;
284 drm_ioctl_t *func;
285 int flags; 284 int flags;
285 drm_ioctl_t *func;
286}; 286};
287 287
288/** 288/**
289 * Creates a driver or general drm_ioctl_desc array entry for the given 289 * Creates a driver or general drm_ioctl_desc array entry for the given
290 * ioctl, for use by drm_ioctl(). 290 * ioctl, for use by drm_ioctl().
291 */ 291 */
292#define DRM_IOCTL_DEF(ioctl, func, flags) \ 292#define DRM_IOCTL_DEF(ioctl, _func, _flags) \
293 [DRM_IOCTL_NR(ioctl)] = {ioctl, func, flags} 293 [DRM_IOCTL_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags}
294 294
295struct drm_magic_entry { 295struct drm_magic_entry {
296 struct list_head head; 296 struct list_head head;
@@ -523,19 +523,32 @@ struct drm_mm {
523 523
524 524
525/** 525/**
526 * Kernel side of a mapping
527 */
528struct drm_local_map {
529 resource_size_t offset; /**< Requested physical address (0 for SAREA)*/
530 unsigned long size; /**< Requested physical size (bytes) */
531 enum drm_map_type type; /**< Type of memory to map */
532 enum drm_map_flags flags; /**< Flags */
533 void *handle; /**< User-space: "Handle" to pass to mmap() */
534 /**< Kernel-space: kernel-virtual address */
535 int mtrr; /**< MTRR slot used */
536};
537
538typedef struct drm_local_map drm_local_map_t;
539
540/**
526 * Mappings list 541 * Mappings list
527 */ 542 */
528struct drm_map_list { 543struct drm_map_list {
529 struct list_head head; /**< list head */ 544 struct list_head head; /**< list head */
530 struct drm_hash_item hash; 545 struct drm_hash_item hash;
531 struct drm_map *map; /**< mapping */ 546 struct drm_local_map *map; /**< mapping */
532 uint64_t user_token; 547 uint64_t user_token;
533 struct drm_master *master; 548 struct drm_master *master;
534 struct drm_mm_node *file_offset_node; /**< fake offset */ 549 struct drm_mm_node *file_offset_node; /**< fake offset */
535}; 550};
536 551
537typedef struct drm_map drm_local_map_t;
538
539/** 552/**
540 * Context handle list 553 * Context handle list
541 */ 554 */
@@ -560,7 +573,7 @@ struct drm_ati_pcigart_info {
560 dma_addr_t bus_addr; 573 dma_addr_t bus_addr;
561 dma_addr_t table_mask; 574 dma_addr_t table_mask;
562 struct drm_dma_handle *table_handle; 575 struct drm_dma_handle *table_handle;
563 drm_local_map_t mapping; 576 struct drm_local_map mapping;
564 int table_size; 577 int table_size;
565}; 578};
566 579
@@ -675,7 +688,6 @@ struct drm_driver {
675 int (*kernel_context_switch) (struct drm_device *dev, int old, 688 int (*kernel_context_switch) (struct drm_device *dev, int old,
676 int new); 689 int new);
677 void (*kernel_context_switch_unlock) (struct drm_device *dev); 690 void (*kernel_context_switch_unlock) (struct drm_device *dev);
678 int (*dri_library_name) (struct drm_device *dev, char *buf);
679 691
680 /** 692 /**
681 * get_vblank_counter - get raw hardware vblank counter 693 * get_vblank_counter - get raw hardware vblank counter
@@ -747,8 +759,8 @@ struct drm_driver {
747 struct drm_file *file_priv); 759 struct drm_file *file_priv);
748 void (*reclaim_buffers_idlelocked) (struct drm_device *dev, 760 void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
749 struct drm_file *file_priv); 761 struct drm_file *file_priv);
750 unsigned long (*get_map_ofs) (struct drm_map * map); 762 resource_size_t (*get_map_ofs) (struct drm_local_map * map);
751 unsigned long (*get_reg_ofs) (struct drm_device *dev); 763 resource_size_t (*get_reg_ofs) (struct drm_device *dev);
752 void (*set_version) (struct drm_device *dev, 764 void (*set_version) (struct drm_device *dev,
753 struct drm_set_version *sv); 765 struct drm_set_version *sv);
754 766
@@ -758,6 +770,8 @@ struct drm_driver {
758 770
759 int (*proc_init)(struct drm_minor *minor); 771 int (*proc_init)(struct drm_minor *minor);
760 void (*proc_cleanup)(struct drm_minor *minor); 772 void (*proc_cleanup)(struct drm_minor *minor);
773 int (*debugfs_init)(struct drm_minor *minor);
774 void (*debugfs_cleanup)(struct drm_minor *minor);
761 775
762 /** 776 /**
763 * Driver-specific constructor for drm_gem_objects, to set up 777 * Driver-specific constructor for drm_gem_objects, to set up
@@ -793,6 +807,48 @@ struct drm_driver {
793#define DRM_MINOR_CONTROL 2 807#define DRM_MINOR_CONTROL 2
794#define DRM_MINOR_RENDER 3 808#define DRM_MINOR_RENDER 3
795 809
810
811/**
812 * debugfs node list. This structure represents a debugfs file to
813 * be created by the drm core
814 */
815struct drm_debugfs_list {
816 const char *name; /** file name */
817 int (*show)(struct seq_file*, void*); /** show callback */
818 u32 driver_features; /**< Required driver features for this entry */
819};
820
821/**
822 * debugfs node structure. This structure represents a debugfs file.
823 */
824struct drm_debugfs_node {
825 struct list_head list;
826 struct drm_minor *minor;
827 struct drm_debugfs_list *debugfs_ent;
828 struct dentry *dent;
829};
830
831/**
832 * Info file list entry. This structure represents a debugfs or proc file to
833 * be created by the drm core
834 */
835struct drm_info_list {
836 const char *name; /** file name */
837 int (*show)(struct seq_file*, void*); /** show callback */
838 u32 driver_features; /**< Required driver features for this entry */
839 void *data;
840};
841
842/**
843 * debugfs node structure. This structure represents a debugfs file.
844 */
845struct drm_info_node {
846 struct list_head list;
847 struct drm_minor *minor;
848 struct drm_info_list *info_ent;
849 struct dentry *dent;
850};
851
796/** 852/**
797 * DRM minor structure. This structure represents a drm minor number. 853 * DRM minor structure. This structure represents a drm minor number.
798 */ 854 */
@@ -802,7 +858,12 @@ struct drm_minor {
802 dev_t device; /**< Device number for mknod */ 858 dev_t device; /**< Device number for mknod */
803 struct device kdev; /**< Linux device */ 859 struct device kdev; /**< Linux device */
804 struct drm_device *dev; 860 struct drm_device *dev;
805 struct proc_dir_entry *dev_root; /**< proc directory entry */ 861
862 struct proc_dir_entry *proc_root; /**< proc directory entry */
863 struct drm_info_node proc_nodes;
864 struct dentry *debugfs_root;
865 struct drm_info_node debugfs_nodes;
866
806 struct drm_master *master; /* currently active master for this node */ 867 struct drm_master *master; /* currently active master for this node */
807 struct list_head master_list; 868 struct list_head master_list;
808 struct drm_mode_group mode_group; 869 struct drm_mode_group mode_group;
@@ -932,7 +993,7 @@ struct drm_device {
932 sigset_t sigmask; 993 sigset_t sigmask;
933 994
934 struct drm_driver *driver; 995 struct drm_driver *driver;
935 drm_local_map_t *agp_buffer_map; 996 struct drm_local_map *agp_buffer_map;
936 unsigned int agp_buffer_token; 997 unsigned int agp_buffer_token;
937 struct drm_minor *control; /**< Control node for card */ 998 struct drm_minor *control; /**< Control node for card */
938 struct drm_minor *primary; /**< render type primary screen head */ 999 struct drm_minor *primary; /**< render type primary screen head */
@@ -1049,8 +1110,8 @@ extern int drm_release(struct inode *inode, struct file *filp);
1049extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); 1110extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
1050extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma); 1111extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma);
1051extern void drm_vm_open_locked(struct vm_area_struct *vma); 1112extern void drm_vm_open_locked(struct vm_area_struct *vma);
1052extern unsigned long drm_core_get_map_ofs(struct drm_map * map); 1113extern resource_size_t drm_core_get_map_ofs(struct drm_local_map * map);
1053extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); 1114extern resource_size_t drm_core_get_reg_ofs(struct drm_device *dev);
1054extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); 1115extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
1055 1116
1056 /* Memory management support (drm_memory.h) */ 1117 /* Memory management support (drm_memory.h) */
@@ -1153,13 +1214,13 @@ extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv
1153 /* Buffer management support (drm_bufs.h) */ 1214 /* Buffer management support (drm_bufs.h) */
1154extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request); 1215extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
1155extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request); 1216extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
1156extern int drm_addmap(struct drm_device *dev, unsigned int offset, 1217extern int drm_addmap(struct drm_device *dev, resource_size_t offset,
1157 unsigned int size, enum drm_map_type type, 1218 unsigned int size, enum drm_map_type type,
1158 enum drm_map_flags flags, drm_local_map_t ** map_ptr); 1219 enum drm_map_flags flags, struct drm_local_map **map_ptr);
1159extern int drm_addmap_ioctl(struct drm_device *dev, void *data, 1220extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
1160 struct drm_file *file_priv); 1221 struct drm_file *file_priv);
1161extern int drm_rmmap(struct drm_device *dev, drm_local_map_t *map); 1222extern int drm_rmmap(struct drm_device *dev, struct drm_local_map *map);
1162extern int drm_rmmap_locked(struct drm_device *dev, drm_local_map_t *map); 1223extern int drm_rmmap_locked(struct drm_device *dev, struct drm_local_map *map);
1163extern int drm_rmmap_ioctl(struct drm_device *dev, void *data, 1224extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
1164 struct drm_file *file_priv); 1225 struct drm_file *file_priv);
1165extern int drm_addbufs(struct drm_device *dev, void *data, 1226extern int drm_addbufs(struct drm_device *dev, void *data,
@@ -1173,10 +1234,10 @@ extern int drm_freebufs(struct drm_device *dev, void *data,
1173extern int drm_mapbufs(struct drm_device *dev, void *data, 1234extern int drm_mapbufs(struct drm_device *dev, void *data,
1174 struct drm_file *file_priv); 1235 struct drm_file *file_priv);
1175extern int drm_order(unsigned long size); 1236extern int drm_order(unsigned long size);
1176extern unsigned long drm_get_resource_start(struct drm_device *dev, 1237extern resource_size_t drm_get_resource_start(struct drm_device *dev,
1238 unsigned int resource);
1239extern resource_size_t drm_get_resource_len(struct drm_device *dev,
1177 unsigned int resource); 1240 unsigned int resource);
1178extern unsigned long drm_get_resource_len(struct drm_device *dev,
1179 unsigned int resource);
1180 1241
1181 /* DMA support (drm_dma.h) */ 1242 /* DMA support (drm_dma.h) */
1182extern int drm_dma_setup(struct drm_device *dev); 1243extern int drm_dma_setup(struct drm_device *dev);
@@ -1252,22 +1313,48 @@ extern struct drm_master *drm_master_get(struct drm_master *master);
1252extern void drm_master_put(struct drm_master **master); 1313extern void drm_master_put(struct drm_master **master);
1253extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, 1314extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
1254 struct drm_driver *driver); 1315 struct drm_driver *driver);
1255extern int drm_put_dev(struct drm_device *dev); 1316extern void drm_put_dev(struct drm_device *dev);
1256extern int drm_put_minor(struct drm_minor **minor); 1317extern int drm_put_minor(struct drm_minor **minor);
1257extern unsigned int drm_debug; 1318extern unsigned int drm_debug;
1258 1319
1259extern struct class *drm_class; 1320extern struct class *drm_class;
1260extern struct proc_dir_entry *drm_proc_root; 1321extern struct proc_dir_entry *drm_proc_root;
1322extern struct dentry *drm_debugfs_root;
1261 1323
1262extern struct idr drm_minors_idr; 1324extern struct idr drm_minors_idr;
1263 1325
1264extern drm_local_map_t *drm_getsarea(struct drm_device *dev); 1326extern struct drm_local_map *drm_getsarea(struct drm_device *dev);
1265 1327
1266 /* Proc support (drm_proc.h) */ 1328 /* Proc support (drm_proc.h) */
1267extern int drm_proc_init(struct drm_minor *minor, int minor_id, 1329extern int drm_proc_init(struct drm_minor *minor, int minor_id,
1268 struct proc_dir_entry *root); 1330 struct proc_dir_entry *root);
1269extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root); 1331extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
1270 1332
1333 /* Debugfs support */
1334#if defined(CONFIG_DEBUG_FS)
1335extern int drm_debugfs_init(struct drm_minor *minor, int minor_id,
1336 struct dentry *root);
1337extern int drm_debugfs_create_files(struct drm_info_list *files, int count,
1338 struct dentry *root, struct drm_minor *minor);
1339extern int drm_debugfs_remove_files(struct drm_info_list *files, int count,
1340 struct drm_minor *minor);
1341extern int drm_debugfs_cleanup(struct drm_minor *minor);
1342#endif
1343
1344 /* Info file support */
1345extern int drm_name_info(struct seq_file *m, void *data);
1346extern int drm_vm_info(struct seq_file *m, void *data);
1347extern int drm_queues_info(struct seq_file *m, void *data);
1348extern int drm_bufs_info(struct seq_file *m, void *data);
1349extern int drm_vblank_info(struct seq_file *m, void *data);
1350extern int drm_clients_info(struct seq_file *m, void* data);
1351extern int drm_gem_name_info(struct seq_file *m, void *data);
1352extern int drm_gem_object_info(struct seq_file *m, void* data);
1353
1354#if DRM_DEBUG_CODE
1355extern int drm_vma_info(struct seq_file *m, void *data);
1356#endif
1357
1271 /* Scatter Gather Support (drm_scatter.h) */ 1358 /* Scatter Gather Support (drm_scatter.h) */
1272extern void drm_sg_cleanup(struct drm_sg_mem * entry); 1359extern void drm_sg_cleanup(struct drm_sg_mem * entry);
1273extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data, 1360extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
@@ -1378,12 +1465,12 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data,
1378void drm_gem_open(struct drm_device *dev, struct drm_file *file_private); 1465void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
1379void drm_gem_release(struct drm_device *dev, struct drm_file *file_private); 1466void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
1380 1467
1381extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev); 1468extern void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev);
1382extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev); 1469extern void drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
1383extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev); 1470extern void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
1384 1471
1385static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, 1472static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev,
1386 unsigned int token) 1473 unsigned int token)
1387{ 1474{
1388 struct drm_map_list *_entry; 1475 struct drm_map_list *_entry;
1389 list_for_each_entry(_entry, &dev->maplist, head) 1476 list_for_each_entry(_entry, &dev->maplist, head)
@@ -1410,7 +1497,7 @@ static __inline__ int drm_device_is_pcie(struct drm_device *dev)
1410 return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); 1497 return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
1411} 1498}
1412 1499
1413static __inline__ void drm_core_dropmap(struct drm_map *map) 1500static __inline__ void drm_core_dropmap(struct drm_local_map *map)
1414{ 1501{
1415} 1502}
1416 1503
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 5ded1acfb543..3c1924c010e8 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -550,7 +550,7 @@ struct drm_mode_config {
550 int min_width, min_height; 550 int min_width, min_height;
551 int max_width, max_height; 551 int max_width, max_height;
552 struct drm_mode_config_funcs *funcs; 552 struct drm_mode_config_funcs *funcs;
553 unsigned long fb_base; 553 resource_size_t fb_base;
554 554
555 /* pointers to standard properties */ 555 /* pointers to standard properties */
556 struct list_head property_blob_list; 556 struct list_head property_blob_list;
@@ -613,7 +613,8 @@ extern void drm_fb_release(struct drm_file *file_priv);
613extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); 613extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group);
614extern struct edid *drm_get_edid(struct drm_connector *connector, 614extern struct edid *drm_get_edid(struct drm_connector *connector,
615 struct i2c_adapter *adapter); 615 struct i2c_adapter *adapter);
616extern unsigned char *drm_do_probe_ddc_edid(struct i2c_adapter *adapter); 616extern int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
617 unsigned char *buf, int len);
617extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 618extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
618extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); 619extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode);
619extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode); 620extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode);
@@ -731,4 +732,5 @@ extern int drm_mode_gamma_get_ioctl(struct drm_device *dev,
731 void *data, struct drm_file *file_priv); 732 void *data, struct drm_file *file_priv);
732extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, 733extern int drm_mode_gamma_set_ioctl(struct drm_device *dev,
733 void *data, struct drm_file *file_priv); 734 void *data, struct drm_file *file_priv);
735extern bool drm_detect_hdmi_monitor(struct edid *edid);
734#endif /* __DRM_CRTC_H__ */ 736#endif /* __DRM_CRTC_H__ */
diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h
index c7d4b2e606a5..ec073d8288d9 100644
--- a/include/drm/drm_crtc_helper.h
+++ b/include/drm/drm_crtc_helper.h
@@ -33,7 +33,6 @@
33#ifndef __DRM_CRTC_HELPER_H__ 33#ifndef __DRM_CRTC_HELPER_H__
34#define __DRM_CRTC_HELPER_H__ 34#define __DRM_CRTC_HELPER_H__
35 35
36#include <linux/i2c.h>
37#include <linux/spinlock.h> 36#include <linux/spinlock.h>
38#include <linux/types.h> 37#include <linux/types.h>
39#include <linux/idr.h> 38#include <linux/idr.h>
@@ -92,7 +91,7 @@ struct drm_connector_helper_funcs {
92extern int drm_helper_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY); 91extern int drm_helper_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY);
93extern void drm_helper_disable_unused_functions(struct drm_device *dev); 92extern void drm_helper_disable_unused_functions(struct drm_device *dev);
94extern int drm_helper_hotplug_stage_two(struct drm_device *dev); 93extern int drm_helper_hotplug_stage_two(struct drm_device *dev);
95extern bool drm_helper_initial_config(struct drm_device *dev, bool can_grow); 94extern bool drm_helper_initial_config(struct drm_device *dev);
96extern int drm_crtc_helper_set_config(struct drm_mode_set *set); 95extern int drm_crtc_helper_set_config(struct drm_mode_set *set);
97extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, 96extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
98 struct drm_display_mode *mode, 97 struct drm_display_mode *mode,
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 601d2bd839f6..ae304cc73c90 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -27,11 +27,8 @@
27#ifndef _DRM_MODE_H 27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H 28#define _DRM_MODE_H
29 29
30#if !defined(__KERNEL__) && !defined(_KERNEL)
31#include <stdint.h>
32#else
33#include <linux/kernel.h> 30#include <linux/kernel.h>
34#endif 31#include <linux/types.h>
35 32
36#define DRM_DISPLAY_INFO_LEN 32 33#define DRM_DISPLAY_INFO_LEN 32
37#define DRM_CONNECTOR_NAME_LEN 32 34#define DRM_CONNECTOR_NAME_LEN 32
@@ -81,41 +78,41 @@
81#define DRM_MODE_DITHERING_ON 1 78#define DRM_MODE_DITHERING_ON 1
82 79
83struct drm_mode_modeinfo { 80struct drm_mode_modeinfo {
84 uint32_t clock; 81 __u32 clock;
85 uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; 82 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
86 uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; 83 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
87 84
88 uint32_t vrefresh; /* vertical refresh * 1000 */ 85 __u32 vrefresh; /* vertical refresh * 1000 */
89 86
90 uint32_t flags; 87 __u32 flags;
91 uint32_t type; 88 __u32 type;
92 char name[DRM_DISPLAY_MODE_LEN]; 89 char name[DRM_DISPLAY_MODE_LEN];
93}; 90};
94 91
95struct drm_mode_card_res { 92struct drm_mode_card_res {
96 uint64_t fb_id_ptr; 93 __u64 fb_id_ptr;
97 uint64_t crtc_id_ptr; 94 __u64 crtc_id_ptr;
98 uint64_t connector_id_ptr; 95 __u64 connector_id_ptr;
99 uint64_t encoder_id_ptr; 96 __u64 encoder_id_ptr;
100 uint32_t count_fbs; 97 __u32 count_fbs;
101 uint32_t count_crtcs; 98 __u32 count_crtcs;
102 uint32_t count_connectors; 99 __u32 count_connectors;
103 uint32_t count_encoders; 100 __u32 count_encoders;
104 uint32_t min_width, max_width; 101 __u32 min_width, max_width;
105 uint32_t min_height, max_height; 102 __u32 min_height, max_height;
106}; 103};
107 104
108struct drm_mode_crtc { 105struct drm_mode_crtc {
109 uint64_t set_connectors_ptr; 106 __u64 set_connectors_ptr;
110 uint32_t count_connectors; 107 __u32 count_connectors;
111 108
112 uint32_t crtc_id; /**< Id */ 109 __u32 crtc_id; /**< Id */
113 uint32_t fb_id; /**< Id of framebuffer */ 110 __u32 fb_id; /**< Id of framebuffer */
114 111
115 uint32_t x, y; /**< Position on the frameuffer */ 112 __u32 x, y; /**< Position on the frameuffer */
116 113
117 uint32_t gamma_size; 114 __u32 gamma_size;
118 uint32_t mode_valid; 115 __u32 mode_valid;
119 struct drm_mode_modeinfo mode; 116 struct drm_mode_modeinfo mode;
120}; 117};
121 118
@@ -126,13 +123,13 @@ struct drm_mode_crtc {
126#define DRM_MODE_ENCODER_TVDAC 4 123#define DRM_MODE_ENCODER_TVDAC 4
127 124
128struct drm_mode_get_encoder { 125struct drm_mode_get_encoder {
129 uint32_t encoder_id; 126 __u32 encoder_id;
130 uint32_t encoder_type; 127 __u32 encoder_type;
131 128
132 uint32_t crtc_id; /**< Id of crtc */ 129 __u32 crtc_id; /**< Id of crtc */
133 130
134 uint32_t possible_crtcs; 131 __u32 possible_crtcs;
135 uint32_t possible_clones; 132 __u32 possible_clones;
136}; 133};
137 134
138/* This is for connectors with multiple signal types. */ 135/* This is for connectors with multiple signal types. */
@@ -161,23 +158,23 @@ struct drm_mode_get_encoder {
161 158
162struct drm_mode_get_connector { 159struct drm_mode_get_connector {
163 160
164 uint64_t encoders_ptr; 161 __u64 encoders_ptr;
165 uint64_t modes_ptr; 162 __u64 modes_ptr;
166 uint64_t props_ptr; 163 __u64 props_ptr;
167 uint64_t prop_values_ptr; 164 __u64 prop_values_ptr;
168 165
169 uint32_t count_modes; 166 __u32 count_modes;
170 uint32_t count_props; 167 __u32 count_props;
171 uint32_t count_encoders; 168 __u32 count_encoders;
172 169
173 uint32_t encoder_id; /**< Current Encoder */ 170 __u32 encoder_id; /**< Current Encoder */
174 uint32_t connector_id; /**< Id */ 171 __u32 connector_id; /**< Id */
175 uint32_t connector_type; 172 __u32 connector_type;
176 uint32_t connector_type_id; 173 __u32 connector_type_id;
177 174
178 uint32_t connection; 175 __u32 connection;
179 uint32_t mm_width, mm_height; /**< HxW in millimeters */ 176 __u32 mm_width, mm_height; /**< HxW in millimeters */
180 uint32_t subpixel; 177 __u32 subpixel;
181}; 178};
182 179
183#define DRM_MODE_PROP_PENDING (1<<0) 180#define DRM_MODE_PROP_PENDING (1<<0)
@@ -187,46 +184,46 @@ struct drm_mode_get_connector {
187#define DRM_MODE_PROP_BLOB (1<<4) 184#define DRM_MODE_PROP_BLOB (1<<4)
188 185
189struct drm_mode_property_enum { 186struct drm_mode_property_enum {
190 uint64_t value; 187 __u64 value;
191 char name[DRM_PROP_NAME_LEN]; 188 char name[DRM_PROP_NAME_LEN];
192}; 189};
193 190
194struct drm_mode_get_property { 191struct drm_mode_get_property {
195 uint64_t values_ptr; /* values and blob lengths */ 192 __u64 values_ptr; /* values and blob lengths */
196 uint64_t enum_blob_ptr; /* enum and blob id ptrs */ 193 __u64 enum_blob_ptr; /* enum and blob id ptrs */
197 194
198 uint32_t prop_id; 195 __u32 prop_id;
199 uint32_t flags; 196 __u32 flags;
200 char name[DRM_PROP_NAME_LEN]; 197 char name[DRM_PROP_NAME_LEN];
201 198
202 uint32_t count_values; 199 __u32 count_values;
203 uint32_t count_enum_blobs; 200 __u32 count_enum_blobs;
204}; 201};
205 202
206struct drm_mode_connector_set_property { 203struct drm_mode_connector_set_property {
207 uint64_t value; 204 __u64 value;
208 uint32_t prop_id; 205 __u32 prop_id;
209 uint32_t connector_id; 206 __u32 connector_id;
210}; 207};
211 208
212struct drm_mode_get_blob { 209struct drm_mode_get_blob {
213 uint32_t blob_id; 210 __u32 blob_id;
214 uint32_t length; 211 __u32 length;
215 uint64_t data; 212 __u64 data;
216}; 213};
217 214
218struct drm_mode_fb_cmd { 215struct drm_mode_fb_cmd {
219 uint32_t fb_id; 216 __u32 fb_id;
220 uint32_t width, height; 217 __u32 width, height;
221 uint32_t pitch; 218 __u32 pitch;
222 uint32_t bpp; 219 __u32 bpp;
223 uint32_t depth; 220 __u32 depth;
224 /* driver specific handle */ 221 /* driver specific handle */
225 uint32_t handle; 222 __u32 handle;
226}; 223};
227 224
228struct drm_mode_mode_cmd { 225struct drm_mode_mode_cmd {
229 uint32_t connector_id; 226 __u32 connector_id;
230 struct drm_mode_modeinfo mode; 227 struct drm_mode_modeinfo mode;
231}; 228};
232 229
@@ -248,24 +245,24 @@ struct drm_mode_mode_cmd {
248 * y 245 * y
249 */ 246 */
250struct drm_mode_cursor { 247struct drm_mode_cursor {
251 uint32_t flags; 248 __u32 flags;
252 uint32_t crtc_id; 249 __u32 crtc_id;
253 int32_t x; 250 __s32 x;
254 int32_t y; 251 __s32 y;
255 uint32_t width; 252 __u32 width;
256 uint32_t height; 253 __u32 height;
257 /* driver specific handle */ 254 /* driver specific handle */
258 uint32_t handle; 255 __u32 handle;
259}; 256};
260 257
261struct drm_mode_crtc_lut { 258struct drm_mode_crtc_lut {
262 uint32_t crtc_id; 259 __u32 crtc_id;
263 uint32_t gamma_size; 260 __u32 gamma_size;
264 261
265 /* pointers to arrays */ 262 /* pointers to arrays */
266 uint64_t red; 263 __u64 red;
267 uint64_t green; 264 __u64 green;
268 uint64_t blue; 265 __u64 blue;
269}; 266};
270 267
271#endif 268#endif
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
index 8dbd2572b7c3..26641e95e0a4 100644
--- a/include/drm/drm_os_linux.h
+++ b/include/drm/drm_os_linux.h
@@ -6,6 +6,19 @@
6#include <linux/interrupt.h> /* For task queue support */ 6#include <linux/interrupt.h> /* For task queue support */
7#include <linux/delay.h> 7#include <linux/delay.h>
8 8
9#ifndef readq
10static inline u64 readq(void __iomem *reg)
11{
12 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
13}
14
15static inline void writeq(u64 val, void __iomem *reg)
16{
17 writel(val & 0xffffffff, reg);
18 writel(val >> 32, reg + 0x4UL);
19}
20#endif
21
9/** Current process ID */ 22/** Current process ID */
10#define DRM_CURRENTPID task_pid_nr(current) 23#define DRM_CURRENTPID task_pid_nr(current)
11#define DRM_SUSER(p) capable(CAP_SYS_ADMIN) 24#define DRM_SUSER(p) capable(CAP_SYS_ADMIN)
@@ -23,6 +36,12 @@
23/** Write a dword into a MMIO region */ 36/** Write a dword into a MMIO region */
24#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset)) 37#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
25/** Read memory barrier */ 38/** Read memory barrier */
39
40/** Read a qword from a MMIO region - be careful using these unless you really understand them */
41#define DRM_READ64(map, offset) readq(((void __iomem *)(map)->handle) + (offset))
42/** Write a qword into a MMIO region */
43#define DRM_WRITE64(map, offset, val) writeq(val, ((void __iomem *)(map)->handle) + (offset))
44
26#define DRM_READMEMORYBARRIER() rmb() 45#define DRM_READMEMORYBARRIER() rmb()
27/** Write memory barrier */ 46/** Write memory barrier */
28#define DRM_WRITEMEMORYBARRIER() wmb() 47#define DRM_WRITEMEMORYBARRIER() wmb()
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 5165f240aa68..2df74eb09563 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -239,10 +239,123 @@
239 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 239 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
240 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 240 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
241 {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 241 {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
242 {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
243 {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
244 {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
242 {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 245 {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
243 {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 246 {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
244 {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 247 {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
245 {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ 248 {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
249 {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
250 {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
251 {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
252 {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
253 {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
254 {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
255 {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
256 {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
257 {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
258 {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
259 {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
260 {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
261 {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
262 {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
263 {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
264 {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
265 {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
266 {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
267 {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
268 {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
269 {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
270 {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
271 {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
272 {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
273 {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
274 {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
275 {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
276 {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
277 {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
278 {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
279 {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
280 {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
281 {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
282 {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
283 {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
284 {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
285 {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
286 {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
287 {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
288 {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
289 {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
290 {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
291 {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
292 {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
293 {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
294 {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
295 {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
296 {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
297 {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
298 {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
299 {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
300 {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
301 {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
302 {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
303 {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
304 {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
305 {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
306 {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
307 {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
308 {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
309 {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
310 {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
311 {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
312 {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
313 {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
314 {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
315 {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
316 {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
317 {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
318 {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
319 {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
320 {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
321 {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
322 {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
323 {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
324 {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
325 {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
326 {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
327 {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
328 {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
329 {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
330 {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
331 {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
332 {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
333 {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
334 {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
335 {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
336 {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
337 {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
338 {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
339 {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
340 {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
341 {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
342 {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
343 {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
344 {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
345 {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
346 {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
347 {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
348 {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
349 {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
350 {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
351 {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
352 {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
353 {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
354 {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
355 {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
356 {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
357 {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
358 {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
246 {0, 0, 0} 359 {0, 0, 0}
247 360
248#define r128_PCI_IDS \ 361#define r128_PCI_IDS \
@@ -418,4 +531,6 @@
418 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 531 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
419 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 532 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
420 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 533 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
534 {0x8086, 0xa001, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
535 {0x8086, 0xa011, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
421 {0, 0, 0} 536 {0, 0, 0}
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 912cd52db965..67e3353a56d6 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -30,7 +30,7 @@
30/* Please note that modifications to all structs defined here are 30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints. 31 * subject to backwards-compatibility constraints.
32 */ 32 */
33 33#include <linux/types.h>
34#include "drm.h" 34#include "drm.h"
35 35
36/* Each region is a minimum of 16k, and there are at most 255 of them. 36/* Each region is a minimum of 16k, and there are at most 255 of them.
@@ -116,15 +116,15 @@ typedef struct _drm_i915_sarea {
116 116
117 /* fill out some space for old userspace triple buffer */ 117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle; 118 drm_handle_t unused_handle;
119 uint32_t unused1, unused2, unused3; 119 __u32 unused1, unused2, unused3;
120 120
121 /* buffer object handles for static buffers. May change 121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client. 122 * over the lifetime of the client.
123 */ 123 */
124 uint32_t front_bo_handle; 124 __u32 front_bo_handle;
125 uint32_t back_bo_handle; 125 __u32 back_bo_handle;
126 uint32_t unused_bo_handle; 126 __u32 unused_bo_handle;
127 uint32_t depth_bo_handle; 127 __u32 depth_bo_handle;
128 128
129} drm_i915_sarea_t; 129} drm_i915_sarea_t;
130 130
@@ -327,7 +327,7 @@ typedef struct drm_i915_vblank_swap {
327} drm_i915_vblank_swap_t; 327} drm_i915_vblank_swap_t;
328 328
329typedef struct drm_i915_hws_addr { 329typedef struct drm_i915_hws_addr {
330 uint64_t addr; 330 __u64 addr;
331} drm_i915_hws_addr_t; 331} drm_i915_hws_addr_t;
332 332
333struct drm_i915_gem_init { 333struct drm_i915_gem_init {
@@ -335,12 +335,12 @@ struct drm_i915_gem_init {
335 * Beginning offset in the GTT to be managed by the DRM memory 335 * Beginning offset in the GTT to be managed by the DRM memory
336 * manager. 336 * manager.
337 */ 337 */
338 uint64_t gtt_start; 338 __u64 gtt_start;
339 /** 339 /**
340 * Ending offset in the GTT to be managed by the DRM memory 340 * Ending offset in the GTT to be managed by the DRM memory
341 * manager. 341 * manager.
342 */ 342 */
343 uint64_t gtt_end; 343 __u64 gtt_end;
344}; 344};
345 345
346struct drm_i915_gem_create { 346struct drm_i915_gem_create {
@@ -349,94 +349,94 @@ struct drm_i915_gem_create {
349 * 349 *
350 * The (page-aligned) allocated size for the object will be returned. 350 * The (page-aligned) allocated size for the object will be returned.
351 */ 351 */
352 uint64_t size; 352 __u64 size;
353 /** 353 /**
354 * Returned handle for the object. 354 * Returned handle for the object.
355 * 355 *
356 * Object handles are nonzero. 356 * Object handles are nonzero.
357 */ 357 */
358 uint32_t handle; 358 __u32 handle;
359 uint32_t pad; 359 __u32 pad;
360}; 360};
361 361
362struct drm_i915_gem_pread { 362struct drm_i915_gem_pread {
363 /** Handle for the object being read. */ 363 /** Handle for the object being read. */
364 uint32_t handle; 364 __u32 handle;
365 uint32_t pad; 365 __u32 pad;
366 /** Offset into the object to read from */ 366 /** Offset into the object to read from */
367 uint64_t offset; 367 __u64 offset;
368 /** Length of data to read */ 368 /** Length of data to read */
369 uint64_t size; 369 __u64 size;
370 /** 370 /**
371 * Pointer to write the data into. 371 * Pointer to write the data into.
372 * 372 *
373 * This is a fixed-size type for 32/64 compatibility. 373 * This is a fixed-size type for 32/64 compatibility.
374 */ 374 */
375 uint64_t data_ptr; 375 __u64 data_ptr;
376}; 376};
377 377
378struct drm_i915_gem_pwrite { 378struct drm_i915_gem_pwrite {
379 /** Handle for the object being written to. */ 379 /** Handle for the object being written to. */
380 uint32_t handle; 380 __u32 handle;
381 uint32_t pad; 381 __u32 pad;
382 /** Offset into the object to write to */ 382 /** Offset into the object to write to */
383 uint64_t offset; 383 __u64 offset;
384 /** Length of data to write */ 384 /** Length of data to write */
385 uint64_t size; 385 __u64 size;
386 /** 386 /**
387 * Pointer to read the data from. 387 * Pointer to read the data from.
388 * 388 *
389 * This is a fixed-size type for 32/64 compatibility. 389 * This is a fixed-size type for 32/64 compatibility.
390 */ 390 */
391 uint64_t data_ptr; 391 __u64 data_ptr;
392}; 392};
393 393
394struct drm_i915_gem_mmap { 394struct drm_i915_gem_mmap {
395 /** Handle for the object being mapped. */ 395 /** Handle for the object being mapped. */
396 uint32_t handle; 396 __u32 handle;
397 uint32_t pad; 397 __u32 pad;
398 /** Offset in the object to map. */ 398 /** Offset in the object to map. */
399 uint64_t offset; 399 __u64 offset;
400 /** 400 /**
401 * Length of data to map. 401 * Length of data to map.
402 * 402 *
403 * The value will be page-aligned. 403 * The value will be page-aligned.
404 */ 404 */
405 uint64_t size; 405 __u64 size;
406 /** 406 /**
407 * Returned pointer the data was mapped at. 407 * Returned pointer the data was mapped at.
408 * 408 *
409 * This is a fixed-size type for 32/64 compatibility. 409 * This is a fixed-size type for 32/64 compatibility.
410 */ 410 */
411 uint64_t addr_ptr; 411 __u64 addr_ptr;
412}; 412};
413 413
414struct drm_i915_gem_mmap_gtt { 414struct drm_i915_gem_mmap_gtt {
415 /** Handle for the object being mapped. */ 415 /** Handle for the object being mapped. */
416 uint32_t handle; 416 __u32 handle;
417 uint32_t pad; 417 __u32 pad;
418 /** 418 /**
419 * Fake offset to use for subsequent mmap call 419 * Fake offset to use for subsequent mmap call
420 * 420 *
421 * This is a fixed-size type for 32/64 compatibility. 421 * This is a fixed-size type for 32/64 compatibility.
422 */ 422 */
423 uint64_t offset; 423 __u64 offset;
424}; 424};
425 425
426struct drm_i915_gem_set_domain { 426struct drm_i915_gem_set_domain {
427 /** Handle for the object */ 427 /** Handle for the object */
428 uint32_t handle; 428 __u32 handle;
429 429
430 /** New read domains */ 430 /** New read domains */
431 uint32_t read_domains; 431 __u32 read_domains;
432 432
433 /** New write domain */ 433 /** New write domain */
434 uint32_t write_domain; 434 __u32 write_domain;
435}; 435};
436 436
437struct drm_i915_gem_sw_finish { 437struct drm_i915_gem_sw_finish {
438 /** Handle for the object */ 438 /** Handle for the object */
439 uint32_t handle; 439 __u32 handle;
440}; 440};
441 441
442struct drm_i915_gem_relocation_entry { 442struct drm_i915_gem_relocation_entry {
@@ -448,16 +448,16 @@ struct drm_i915_gem_relocation_entry {
448 * a relocation list for state buffers and not re-write it per 448 * a relocation list for state buffers and not re-write it per
449 * exec using the buffer. 449 * exec using the buffer.
450 */ 450 */
451 uint32_t target_handle; 451 __u32 target_handle;
452 452
453 /** 453 /**
454 * Value to be added to the offset of the target buffer to make up 454 * Value to be added to the offset of the target buffer to make up
455 * the relocation entry. 455 * the relocation entry.
456 */ 456 */
457 uint32_t delta; 457 __u32 delta;
458 458
459 /** Offset in the buffer the relocation entry will be written into */ 459 /** Offset in the buffer the relocation entry will be written into */
460 uint64_t offset; 460 __u64 offset;
461 461
462 /** 462 /**
463 * Offset value of the target buffer that the relocation entry was last 463 * Offset value of the target buffer that the relocation entry was last
@@ -467,12 +467,12 @@ struct drm_i915_gem_relocation_entry {
467 * and writing the relocation. This value is written back out by 467 * and writing the relocation. This value is written back out by
468 * the execbuffer ioctl when the relocation is written. 468 * the execbuffer ioctl when the relocation is written.
469 */ 469 */
470 uint64_t presumed_offset; 470 __u64 presumed_offset;
471 471
472 /** 472 /**
473 * Target memory domains read by this operation. 473 * Target memory domains read by this operation.
474 */ 474 */
475 uint32_t read_domains; 475 __u32 read_domains;
476 476
477 /** 477 /**
478 * Target memory domains written by this operation. 478 * Target memory domains written by this operation.
@@ -481,7 +481,7 @@ struct drm_i915_gem_relocation_entry {
481 * execbuffer operation, so that where there are conflicts, 481 * execbuffer operation, so that where there are conflicts,
482 * the application will get -EINVAL back. 482 * the application will get -EINVAL back.
483 */ 483 */
484 uint32_t write_domain; 484 __u32 write_domain;
485}; 485};
486 486
487/** @{ 487/** @{
@@ -512,24 +512,24 @@ struct drm_i915_gem_exec_object {
512 * User's handle for a buffer to be bound into the GTT for this 512 * User's handle for a buffer to be bound into the GTT for this
513 * operation. 513 * operation.
514 */ 514 */
515 uint32_t handle; 515 __u32 handle;
516 516
517 /** Number of relocations to be performed on this buffer */ 517 /** Number of relocations to be performed on this buffer */
518 uint32_t relocation_count; 518 __u32 relocation_count;
519 /** 519 /**
520 * Pointer to array of struct drm_i915_gem_relocation_entry containing 520 * Pointer to array of struct drm_i915_gem_relocation_entry containing
521 * the relocations to be performed in this buffer. 521 * the relocations to be performed in this buffer.
522 */ 522 */
523 uint64_t relocs_ptr; 523 __u64 relocs_ptr;
524 524
525 /** Required alignment in graphics aperture */ 525 /** Required alignment in graphics aperture */
526 uint64_t alignment; 526 __u64 alignment;
527 527
528 /** 528 /**
529 * Returned value of the updated offset of the object, for future 529 * Returned value of the updated offset of the object, for future
530 * presumed_offset writes. 530 * presumed_offset writes.
531 */ 531 */
532 uint64_t offset; 532 __u64 offset;
533}; 533};
534 534
535struct drm_i915_gem_execbuffer { 535struct drm_i915_gem_execbuffer {
@@ -543,44 +543,44 @@ struct drm_i915_gem_execbuffer {
543 * a buffer is performing refer to buffers that have already appeared 543 * a buffer is performing refer to buffers that have already appeared
544 * in the validate list. 544 * in the validate list.
545 */ 545 */
546 uint64_t buffers_ptr; 546 __u64 buffers_ptr;
547 uint32_t buffer_count; 547 __u32 buffer_count;
548 548
549 /** Offset in the batchbuffer to start execution from. */ 549 /** Offset in the batchbuffer to start execution from. */
550 uint32_t batch_start_offset; 550 __u32 batch_start_offset;
551 /** Bytes used in batchbuffer from batch_start_offset */ 551 /** Bytes used in batchbuffer from batch_start_offset */
552 uint32_t batch_len; 552 __u32 batch_len;
553 uint32_t DR1; 553 __u32 DR1;
554 uint32_t DR4; 554 __u32 DR4;
555 uint32_t num_cliprects; 555 __u32 num_cliprects;
556 /** This is a struct drm_clip_rect *cliprects */ 556 /** This is a struct drm_clip_rect *cliprects */
557 uint64_t cliprects_ptr; 557 __u64 cliprects_ptr;
558}; 558};
559 559
560struct drm_i915_gem_pin { 560struct drm_i915_gem_pin {
561 /** Handle of the buffer to be pinned. */ 561 /** Handle of the buffer to be pinned. */
562 uint32_t handle; 562 __u32 handle;
563 uint32_t pad; 563 __u32 pad;
564 564
565 /** alignment required within the aperture */ 565 /** alignment required within the aperture */
566 uint64_t alignment; 566 __u64 alignment;
567 567
568 /** Returned GTT offset of the buffer. */ 568 /** Returned GTT offset of the buffer. */
569 uint64_t offset; 569 __u64 offset;
570}; 570};
571 571
572struct drm_i915_gem_unpin { 572struct drm_i915_gem_unpin {
573 /** Handle of the buffer to be unpinned. */ 573 /** Handle of the buffer to be unpinned. */
574 uint32_t handle; 574 __u32 handle;
575 uint32_t pad; 575 __u32 pad;
576}; 576};
577 577
578struct drm_i915_gem_busy { 578struct drm_i915_gem_busy {
579 /** Handle of the buffer to check for busy */ 579 /** Handle of the buffer to check for busy */
580 uint32_t handle; 580 __u32 handle;
581 581
582 /** Return busy status (1 if busy, 0 if idle) */ 582 /** Return busy status (1 if busy, 0 if idle) */
583 uint32_t busy; 583 __u32 busy;
584}; 584};
585 585
586#define I915_TILING_NONE 0 586#define I915_TILING_NONE 0
@@ -597,7 +597,7 @@ struct drm_i915_gem_busy {
597 597
598struct drm_i915_gem_set_tiling { 598struct drm_i915_gem_set_tiling {
599 /** Handle of the buffer to have its tiling state updated */ 599 /** Handle of the buffer to have its tiling state updated */
600 uint32_t handle; 600 __u32 handle;
601 601
602 /** 602 /**
603 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 603 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
@@ -611,47 +611,47 @@ struct drm_i915_gem_set_tiling {
611 * 611 *
612 * Buffer contents become undefined when changing tiling_mode. 612 * Buffer contents become undefined when changing tiling_mode.
613 */ 613 */
614 uint32_t tiling_mode; 614 __u32 tiling_mode;
615 615
616 /** 616 /**
617 * Stride in bytes for the object when in I915_TILING_X or 617 * Stride in bytes for the object when in I915_TILING_X or
618 * I915_TILING_Y. 618 * I915_TILING_Y.
619 */ 619 */
620 uint32_t stride; 620 __u32 stride;
621 621
622 /** 622 /**
623 * Returned address bit 6 swizzling required for CPU access through 623 * Returned address bit 6 swizzling required for CPU access through
624 * mmap mapping. 624 * mmap mapping.
625 */ 625 */
626 uint32_t swizzle_mode; 626 __u32 swizzle_mode;
627}; 627};
628 628
629struct drm_i915_gem_get_tiling { 629struct drm_i915_gem_get_tiling {
630 /** Handle of the buffer to get tiling state for. */ 630 /** Handle of the buffer to get tiling state for. */
631 uint32_t handle; 631 __u32 handle;
632 632
633 /** 633 /**
634 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 634 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
635 * I915_TILING_Y). 635 * I915_TILING_Y).
636 */ 636 */
637 uint32_t tiling_mode; 637 __u32 tiling_mode;
638 638
639 /** 639 /**
640 * Returned address bit 6 swizzling required for CPU access through 640 * Returned address bit 6 swizzling required for CPU access through
641 * mmap mapping. 641 * mmap mapping.
642 */ 642 */
643 uint32_t swizzle_mode; 643 __u32 swizzle_mode;
644}; 644};
645 645
646struct drm_i915_gem_get_aperture { 646struct drm_i915_gem_get_aperture {
647 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ 647 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
648 uint64_t aper_size; 648 __u64 aper_size;
649 649
650 /** 650 /**
651 * Available space in the aperture used by i915_gem_execbuffer, in 651 * Available space in the aperture used by i915_gem_execbuffer, in
652 * bytes 652 * bytes
653 */ 653 */
654 uint64_t aper_available_size; 654 __u64 aper_available_size;
655}; 655};
656 656
657#endif /* _I915_DRM_H_ */ 657#endif /* _I915_DRM_H_ */
diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h
index 944b50a5ff24..325fd6fb4a42 100644
--- a/include/drm/mga_drm.h
+++ b/include/drm/mga_drm.h
@@ -35,6 +35,8 @@
35#ifndef __MGA_DRM_H__ 35#ifndef __MGA_DRM_H__
36#define __MGA_DRM_H__ 36#define __MGA_DRM_H__
37 37
38#include <linux/types.h>
39
38/* WARNING: If you change any of these defines, make sure to change the 40/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the Xserver file (mga_sarea.h) 41 * defines in the Xserver file (mga_sarea.h)
40 */ 42 */
@@ -255,8 +257,8 @@ typedef struct _drm_mga_sarea {
255#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) 257#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
256#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) 258#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
257#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) 259#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
258#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t) 260#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
259#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t) 261#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
260#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) 262#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
261 263
262typedef struct _drm_mga_warp_index { 264typedef struct _drm_mga_warp_index {
@@ -310,7 +312,7 @@ typedef struct drm_mga_dma_bootstrap {
310 */ 312 */
311 /*@{ */ 313 /*@{ */
312 unsigned long texture_handle; /**< Handle used to map AGP textures. */ 314 unsigned long texture_handle; /**< Handle used to map AGP textures. */
313 uint32_t texture_size; /**< Size of the AGP texture region. */ 315 __u32 texture_size; /**< Size of the AGP texture region. */
314 /*@} */ 316 /*@} */
315 317
316 /** 318 /**
@@ -319,7 +321,7 @@ typedef struct drm_mga_dma_bootstrap {
319 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be 321 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
320 * filled in with the actual AGP mode. If AGP was not available 322 * filled in with the actual AGP mode. If AGP was not available
321 */ 323 */
322 uint32_t primary_size; 324 __u32 primary_size;
323 325
324 /** 326 /**
325 * Requested number of secondary DMA buffers. 327 * Requested number of secondary DMA buffers.
@@ -329,7 +331,7 @@ typedef struct drm_mga_dma_bootstrap {
329 * allocated. Particularly when PCI DMA is used, this may be 331 * allocated. Particularly when PCI DMA is used, this may be
330 * (subtantially) less than the number requested. 332 * (subtantially) less than the number requested.
331 */ 333 */
332 uint32_t secondary_bin_count; 334 __u32 secondary_bin_count;
333 335
334 /** 336 /**
335 * Requested size of each secondary DMA buffer. 337 * Requested size of each secondary DMA buffer.
@@ -338,7 +340,7 @@ typedef struct drm_mga_dma_bootstrap {
338 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed 340 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
339 * to reduce dma_mga_dma_bootstrap::secondary_bin_size. 341 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
340 */ 342 */
341 uint32_t secondary_bin_size; 343 __u32 secondary_bin_size;
342 344
343 /** 345 /**
344 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, 346 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
@@ -350,12 +352,12 @@ typedef struct drm_mga_dma_bootstrap {
350 * filled in with the actual AGP mode. If AGP was not available 352 * filled in with the actual AGP mode. If AGP was not available
351 * (i.e., PCI DMA was used), this value will be zero. 353 * (i.e., PCI DMA was used), this value will be zero.
352 */ 354 */
353 uint32_t agp_mode; 355 __u32 agp_mode;
354 356
355 /** 357 /**
356 * Desired AGP GART size, measured in megabytes. 358 * Desired AGP GART size, measured in megabytes.
357 */ 359 */
358 uint8_t agp_size; 360 __u8 agp_size;
359} drm_mga_dma_bootstrap_t; 361} drm_mga_dma_bootstrap_t;
360 362
361typedef struct drm_mga_clear { 363typedef struct drm_mga_clear {
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 73ff51f12311..fe3e3a4b4aed 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -33,6 +33,8 @@
33#ifndef __RADEON_DRM_H__ 33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__ 34#define __RADEON_DRM_H__
35 35
36#include <linux/types.h>
37
36/* WARNING: If you change any of these defines, make sure to change the 38/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h) 39 * defines in the X server file (radeon_sarea.h)
38 */ 40 */
@@ -304,6 +306,8 @@ typedef union {
304 306
305#define RADEON_SCRATCH_REG_OFFSET 32 307#define RADEON_SCRATCH_REG_OFFSET 32
306 308
309#define R600_SCRATCH_REG_OFFSET 256
310
307#define RADEON_NR_SAREA_CLIPRECTS 12 311#define RADEON_NR_SAREA_CLIPRECTS 12
308 312
309/* There are 2 heaps (local/GART). Each region within a heap is a 313/* There are 2 heaps (local/GART). Each region within a heap is a
@@ -526,7 +530,8 @@ typedef struct drm_radeon_init {
526 RADEON_INIT_CP = 0x01, 530 RADEON_INIT_CP = 0x01,
527 RADEON_CLEANUP_CP = 0x02, 531 RADEON_CLEANUP_CP = 0x02,
528 RADEON_INIT_R200_CP = 0x03, 532 RADEON_INIT_R200_CP = 0x03,
529 RADEON_INIT_R300_CP = 0x04 533 RADEON_INIT_R300_CP = 0x04,
534 RADEON_INIT_R600_CP = 0x05
530 } func; 535 } func;
531 unsigned long sarea_priv_offset; 536 unsigned long sarea_priv_offset;
532 int is_pci; 537 int is_pci;
@@ -722,7 +727,7 @@ typedef struct drm_radeon_irq_wait {
722 727
723typedef struct drm_radeon_setparam { 728typedef struct drm_radeon_setparam {
724 unsigned int param; 729 unsigned int param;
725 int64_t value; 730 __s64 value;
726} drm_radeon_setparam_t; 731} drm_radeon_setparam_t;
727 732
728#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 733#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h
index a3b5c102b067..170786e5c2ff 100644
--- a/include/drm/via_drm.h
+++ b/include/drm/via_drm.h
@@ -24,6 +24,8 @@
24#ifndef _VIA_DRM_H_ 24#ifndef _VIA_DRM_H_
25#define _VIA_DRM_H_ 25#define _VIA_DRM_H_
26 26
27#include <linux/types.h>
28
27/* WARNING: These defines must be the same as what the Xserver uses. 29/* WARNING: These defines must be the same as what the Xserver uses.
28 * if you change them, you must change the defines in the Xserver. 30 * if you change them, you must change the defines in the Xserver.
29 */ 31 */
@@ -114,19 +116,19 @@
114#define VIA_MEM_UNKNOWN 4 116#define VIA_MEM_UNKNOWN 4
115 117
116typedef struct { 118typedef struct {
117 uint32_t offset; 119 __u32 offset;
118 uint32_t size; 120 __u32 size;
119} drm_via_agp_t; 121} drm_via_agp_t;
120 122
121typedef struct { 123typedef struct {
122 uint32_t offset; 124 __u32 offset;
123 uint32_t size; 125 __u32 size;
124} drm_via_fb_t; 126} drm_via_fb_t;
125 127
126typedef struct { 128typedef struct {
127 uint32_t context; 129 __u32 context;
128 uint32_t type; 130 __u32 type;
129 uint32_t size; 131 __u32 size;
130 unsigned long index; 132 unsigned long index;
131 unsigned long offset; 133 unsigned long offset;
132} drm_via_mem_t; 134} drm_via_mem_t;
@@ -148,9 +150,9 @@ typedef struct _drm_via_futex {
148 VIA_FUTEX_WAIT = 0x00, 150 VIA_FUTEX_WAIT = 0x00,
149 VIA_FUTEX_WAKE = 0X01 151 VIA_FUTEX_WAKE = 0X01
150 } func; 152 } func;
151 uint32_t ms; 153 __u32 ms;
152 uint32_t lock; 154 __u32 lock;
153 uint32_t val; 155 __u32 val;
154} drm_via_futex_t; 156} drm_via_futex_t;
155 157
156typedef struct _drm_via_dma_init { 158typedef struct _drm_via_dma_init {
@@ -211,7 +213,7 @@ typedef struct _drm_via_cmdbuf_size {
211 VIA_CMDBUF_LAG = 0x02 213 VIA_CMDBUF_LAG = 0x02
212 } func; 214 } func;
213 int wait; 215 int wait;
214 uint32_t size; 216 __u32 size;
215} drm_via_cmdbuf_size_t; 217} drm_via_cmdbuf_size_t;
216 218
217typedef enum { 219typedef enum {
@@ -236,8 +238,8 @@ enum drm_via_irqs {
236struct drm_via_wait_irq_request { 238struct drm_via_wait_irq_request {
237 unsigned irq; 239 unsigned irq;
238 via_irq_seq_type_t type; 240 via_irq_seq_type_t type;
239 uint32_t sequence; 241 __u32 sequence;
240 uint32_t signal; 242 __u32 signal;
241}; 243};
242 244
243typedef union drm_via_irqwait { 245typedef union drm_via_irqwait {
@@ -246,7 +248,7 @@ typedef union drm_via_irqwait {
246} drm_via_irqwait_t; 248} drm_via_irqwait_t;
247 249
248typedef struct drm_via_blitsync { 250typedef struct drm_via_blitsync {
249 uint32_t sync_handle; 251 __u32 sync_handle;
250 unsigned engine; 252 unsigned engine;
251} drm_via_blitsync_t; 253} drm_via_blitsync_t;
252 254
@@ -257,16 +259,16 @@ typedef struct drm_via_blitsync {
257 */ 259 */
258 260
259typedef struct drm_via_dmablit { 261typedef struct drm_via_dmablit {
260 uint32_t num_lines; 262 __u32 num_lines;
261 uint32_t line_length; 263 __u32 line_length;
262 264
263 uint32_t fb_addr; 265 __u32 fb_addr;
264 uint32_t fb_stride; 266 __u32 fb_stride;
265 267
266 unsigned char *mem_addr; 268 unsigned char *mem_addr;
267 uint32_t mem_stride; 269 __u32 mem_stride;
268 270
269 uint32_t flags; 271 __u32 flags;
270 int to_fb; 272 int to_fb;
271 273
272 drm_via_blitsync_t sync; 274 drm_via_blitsync_t sync;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 04:47:24 -0500