diff options
Diffstat (limited to 'include/drm')
-rw-r--r-- | include/drm/drm_dp_helper.h | 61 | ||||
-rw-r--r-- | include/drm/intel-gtt.h | 2 |
2 files changed, 63 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 91567bbdb027..0d2f727e96be 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h | |||
@@ -74,6 +74,20 @@ | |||
74 | 74 | ||
75 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e | 75 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
76 | 76 | ||
77 | #define DP_PSR_SUPPORT 0x070 | ||
78 | # define DP_PSR_IS_SUPPORTED 1 | ||
79 | #define DP_PSR_CAPS 0x071 | ||
80 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 | ||
81 | # define DP_PSR_SETUP_TIME_330 (0 << 1) | ||
82 | # define DP_PSR_SETUP_TIME_275 (1 << 1) | ||
83 | # define DP_PSR_SETUP_TIME_220 (2 << 1) | ||
84 | # define DP_PSR_SETUP_TIME_165 (3 << 1) | ||
85 | # define DP_PSR_SETUP_TIME_110 (4 << 1) | ||
86 | # define DP_PSR_SETUP_TIME_55 (5 << 1) | ||
87 | # define DP_PSR_SETUP_TIME_0 (6 << 1) | ||
88 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) | ||
89 | # define DP_PSR_SETUP_TIME_SHIFT 1 | ||
90 | |||
77 | /* link configuration */ | 91 | /* link configuration */ |
78 | #define DP_LINK_BW_SET 0x100 | 92 | #define DP_LINK_BW_SET 0x100 |
79 | # define DP_LINK_BW_1_62 0x06 | 93 | # define DP_LINK_BW_1_62 0x06 |
@@ -133,6 +147,18 @@ | |||
133 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 | 147 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
134 | # define DP_SET_ANSI_8B10B (1 << 0) | 148 | # define DP_SET_ANSI_8B10B (1 << 0) |
135 | 149 | ||
150 | #define DP_PSR_EN_CFG 0x170 | ||
151 | # define DP_PSR_ENABLE (1 << 0) | ||
152 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) | ||
153 | # define DP_PSR_CRC_VERIFICATION (1 << 2) | ||
154 | # define DP_PSR_FRAME_CAPTURE (1 << 3) | ||
155 | |||
156 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 | ||
157 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) | ||
158 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) | ||
159 | # define DP_CP_IRQ (1 << 2) | ||
160 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) | ||
161 | |||
136 | #define DP_LANE0_1_STATUS 0x202 | 162 | #define DP_LANE0_1_STATUS 0x202 |
137 | #define DP_LANE2_3_STATUS 0x203 | 163 | #define DP_LANE2_3_STATUS 0x203 |
138 | # define DP_LANE_CR_DONE (1 << 0) | 164 | # define DP_LANE_CR_DONE (1 << 0) |
@@ -165,10 +191,45 @@ | |||
165 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 | 191 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
166 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 | 192 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
167 | 193 | ||
194 | #define DP_TEST_REQUEST 0x218 | ||
195 | # define DP_TEST_LINK_TRAINING (1 << 0) | ||
196 | # define DP_TEST_LINK_PATTERN (1 << 1) | ||
197 | # define DP_TEST_LINK_EDID_READ (1 << 2) | ||
198 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ | ||
199 | |||
200 | #define DP_TEST_LINK_RATE 0x219 | ||
201 | # define DP_LINK_RATE_162 (0x6) | ||
202 | # define DP_LINK_RATE_27 (0xa) | ||
203 | |||
204 | #define DP_TEST_LANE_COUNT 0x220 | ||
205 | |||
206 | #define DP_TEST_PATTERN 0x221 | ||
207 | |||
208 | #define DP_TEST_RESPONSE 0x260 | ||
209 | # define DP_TEST_ACK (1 << 0) | ||
210 | # define DP_TEST_NAK (1 << 1) | ||
211 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) | ||
212 | |||
168 | #define DP_SET_POWER 0x600 | 213 | #define DP_SET_POWER 0x600 |
169 | # define DP_SET_POWER_D0 0x1 | 214 | # define DP_SET_POWER_D0 0x1 |
170 | # define DP_SET_POWER_D3 0x2 | 215 | # define DP_SET_POWER_D3 0x2 |
171 | 216 | ||
217 | #define DP_PSR_ERROR_STATUS 0x2006 | ||
218 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) | ||
219 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) | ||
220 | |||
221 | #define DP_PSR_ESI 0x2007 | ||
222 | # define DP_PSR_CAPS_CHANGE (1 << 0) | ||
223 | |||
224 | #define DP_PSR_STATUS 0x2008 | ||
225 | # define DP_PSR_SINK_INACTIVE 0 | ||
226 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 | ||
227 | # define DP_PSR_SINK_ACTIVE_RFB 2 | ||
228 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 | ||
229 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 | ||
230 | # define DP_PSR_SINK_INTERNAL_ERROR 7 | ||
231 | # define DP_PSR_SINK_STATE_MASK 0x07 | ||
232 | |||
172 | #define MODE_I2C_START 1 | 233 | #define MODE_I2C_START 1 |
173 | #define MODE_I2C_WRITE 2 | 234 | #define MODE_I2C_WRITE 2 |
174 | #define MODE_I2C_READ 4 | 235 | #define MODE_I2C_READ 4 |
diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h index 9e343c0998b4..b174620cc9b3 100644 --- a/include/drm/intel-gtt.h +++ b/include/drm/intel-gtt.h | |||
@@ -13,6 +13,8 @@ const struct intel_gtt { | |||
13 | unsigned int gtt_mappable_entries; | 13 | unsigned int gtt_mappable_entries; |
14 | /* Whether i915 needs to use the dmar apis or not. */ | 14 | /* Whether i915 needs to use the dmar apis or not. */ |
15 | unsigned int needs_dmar : 1; | 15 | unsigned int needs_dmar : 1; |
16 | /* Whether we idle the gpu before mapping/unmapping */ | ||
17 | unsigned int do_idle_maps : 1; | ||
16 | } *intel_gtt_get(void); | 18 | } *intel_gtt_get(void); |
17 | 19 | ||
18 | void intel_gtt_chipset_flush(void); | 20 | void intel_gtt_chipset_flush(void); |