1 files changed, 27 insertions, 2 deletions

diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 41862e9a4c20..2ba61e18fc8b 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -506,6 +506,9 @@ typedef struct {
 #define DRM_RADEON_GEM_WAIT_IDLE        0x24
 #define DRM_RADEON_CS                   0x26
 #define DRM_RADEON_INFO                 0x27
+#define DRM_RADEON_GEM_SET_TILING       0x28
+#define DRM_RADEON_GEM_GET_TILING       0x29
+#define DRM_RADEON_GEM_BUSY             0x2a
 
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -544,7 +547,9 @@ typedef struct {
 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE  DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
 #define DRM_IOCTL_RADEON_CS             DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 #define DRM_IOCTL_RADEON_INFO           DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
-
+#define DRM_IOCTL_RADEON_SET_TILING     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
+#define DRM_IOCTL_RADEON_GET_TILING     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
+#define DRM_IOCTL_RADEON_GEM_BUSY       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 
 typedef struct drm_radeon_init {
         enum {
@@ -704,6 +709,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 #define RADEON_PARAM_DEVICE_ID             16
+#define RADEON_PARAM_NUM_Z_PIPES           17   /* num Z pipes */
 
 typedef struct drm_radeon_getparam {
         int param;
@@ -796,6 +802,24 @@ struct drm_radeon_gem_create {
         uint32_t        flags;
 };
 
+#define RADEON_TILING_MACRO 0x1
+#define RADEON_TILING_MICRO 0x2
+#define RADEON_TILING_SWAP  0x4
+#define RADEON_TILING_SURFACE  0x8 /* this object requires a surface
+                                    * when mapped - i.e. front buffer */
+
+struct drm_radeon_gem_set_tiling {
+        uint32_t        handle;
+        uint32_t        tiling_flags;
+        uint32_t        pitch;
+};
+
+struct drm_radeon_gem_get_tiling {
+        uint32_t        handle;
+        uint32_t        tiling_flags;
+        uint32_t        pitch;
+};
+
 struct drm_radeon_gem_mmap {
         uint32_t        handle;
         uint32_t        pad;
@@ -817,7 +841,7 @@ struct drm_radeon_gem_wait_idle {
 
 struct drm_radeon_gem_busy {
         uint32_t        handle;
-        uint32_t        busy;
+        uint32_t        domain;
 };
 
 struct drm_radeon_gem_pread {
@@ -874,6 +898,7 @@ struct drm_radeon_cs {
 
 #define RADEON_INFO_DEVICE_ID           0x00
 #define RADEON_INFO_NUM_GB_PIPES        0x01
+#define RADEON_INFO_NUM_Z_PIPES         0x02
 
 struct drm_radeon_info {
         uint32_t                request;