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-rw-r--r--include/drm/i915_drm.h886
1 files changed, 1 insertions, 885 deletions
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 8cc70837f929..63d609d8a3f6 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -23,899 +23,15 @@
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * 24 *
25 */ 25 */
26
27#ifndef _I915_DRM_H_ 26#ifndef _I915_DRM_H_
28#define _I915_DRM_H_ 27#define _I915_DRM_H_
29 28
30#include "drm.h" 29#include <uapi/drm/i915_drm.h>
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35 30
36#ifdef __KERNEL__
37/* For use by IPS driver */ 31/* For use by IPS driver */
38extern unsigned long i915_read_mch_val(void); 32extern unsigned long i915_read_mch_val(void);
39extern bool i915_gpu_raise(void); 33extern bool i915_gpu_raise(void);
40extern bool i915_gpu_lower(void); 34extern bool i915_gpu_lower(void);
41extern bool i915_gpu_busy(void); 35extern bool i915_gpu_busy(void);
42extern bool i915_gpu_turbo_disable(void); 36extern bool i915_gpu_turbo_disable(void);
43#endif
44
45/* Each region is a minimum of 16k, and there are at most 255 of them.
46 */
47#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
48 * of chars for next/prev indices */
49#define I915_LOG_MIN_TEX_REGION_SIZE 14
50
51typedef struct _drm_i915_init {
52 enum {
53 I915_INIT_DMA = 0x01,
54 I915_CLEANUP_DMA = 0x02,
55 I915_RESUME_DMA = 0x03
56 } func;
57 unsigned int mmio_offset;
58 int sarea_priv_offset;
59 unsigned int ring_start;
60 unsigned int ring_end;
61 unsigned int ring_size;
62 unsigned int front_offset;
63 unsigned int back_offset;
64 unsigned int depth_offset;
65 unsigned int w;
66 unsigned int h;
67 unsigned int pitch;
68 unsigned int pitch_bits;
69 unsigned int back_pitch;
70 unsigned int depth_pitch;
71 unsigned int cpp;
72 unsigned int chipset;
73} drm_i915_init_t;
74
75typedef struct _drm_i915_sarea {
76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
77 int last_upload; /* last time texture was uploaded */
78 int last_enqueue; /* last time a buffer was enqueued */
79 int last_dispatch; /* age of the most recently dispatched buffer */
80 int ctxOwner; /* last context to upload state */
81 int texAge;
82 int pf_enabled; /* is pageflipping allowed? */
83 int pf_active;
84 int pf_current_page; /* which buffer is being displayed? */
85 int perf_boxes; /* performance boxes to be displayed */
86 int width, height; /* screen size in pixels */
87
88 drm_handle_t front_handle;
89 int front_offset;
90 int front_size;
91
92 drm_handle_t back_handle;
93 int back_offset;
94 int back_size;
95
96 drm_handle_t depth_handle;
97 int depth_offset;
98 int depth_size;
99
100 drm_handle_t tex_handle;
101 int tex_offset;
102 int tex_size;
103 int log_tex_granularity;
104 int pitch;
105 int rotation; /* 0, 90, 180 or 270 */
106 int rotated_offset;
107 int rotated_size;
108 int rotated_pitch;
109 int virtualX, virtualY;
110
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
116
117 int pipeA_x;
118 int pipeA_y;
119 int pipeA_w;
120 int pipeA_h;
121 int pipeB_x;
122 int pipeB_y;
123 int pipeB_w;
124 int pipeB_h;
125
126 /* fill out some space for old userspace triple buffer */
127 drm_handle_t unused_handle;
128 __u32 unused1, unused2, unused3;
129
130 /* buffer object handles for static buffers. May change
131 * over the lifetime of the client.
132 */
133 __u32 front_bo_handle;
134 __u32 back_bo_handle;
135 __u32 unused_bo_handle;
136 __u32 depth_bo_handle;
137
138} drm_i915_sarea_t;
139
140/* due to userspace building against these headers we need some compat here */
141#define planeA_x pipeA_x
142#define planeA_y pipeA_y
143#define planeA_w pipeA_w
144#define planeA_h pipeA_h
145#define planeB_x pipeB_x
146#define planeB_y pipeB_y
147#define planeB_w pipeB_w
148#define planeB_h pipeB_h
149
150/* Flags for perf_boxes
151 */
152#define I915_BOX_RING_EMPTY 0x1
153#define I915_BOX_FLIP 0x2
154#define I915_BOX_WAIT 0x4
155#define I915_BOX_TEXTURE_LOAD 0x8
156#define I915_BOX_LOST_CONTEXT 0x10
157
158/* I915 specific ioctls
159 * The device specific ioctl range is 0x40 to 0x79.
160 */
161#define DRM_I915_INIT 0x00
162#define DRM_I915_FLUSH 0x01
163#define DRM_I915_FLIP 0x02
164#define DRM_I915_BATCHBUFFER 0x03
165#define DRM_I915_IRQ_EMIT 0x04
166#define DRM_I915_IRQ_WAIT 0x05
167#define DRM_I915_GETPARAM 0x06
168#define DRM_I915_SETPARAM 0x07
169#define DRM_I915_ALLOC 0x08
170#define DRM_I915_FREE 0x09
171#define DRM_I915_INIT_HEAP 0x0a
172#define DRM_I915_CMDBUFFER 0x0b
173#define DRM_I915_DESTROY_HEAP 0x0c
174#define DRM_I915_SET_VBLANK_PIPE 0x0d
175#define DRM_I915_GET_VBLANK_PIPE 0x0e
176#define DRM_I915_VBLANK_SWAP 0x0f
177#define DRM_I915_HWS_ADDR 0x11
178#define DRM_I915_GEM_INIT 0x13
179#define DRM_I915_GEM_EXECBUFFER 0x14
180#define DRM_I915_GEM_PIN 0x15
181#define DRM_I915_GEM_UNPIN 0x16
182#define DRM_I915_GEM_BUSY 0x17
183#define DRM_I915_GEM_THROTTLE 0x18
184#define DRM_I915_GEM_ENTERVT 0x19
185#define DRM_I915_GEM_LEAVEVT 0x1a
186#define DRM_I915_GEM_CREATE 0x1b
187#define DRM_I915_GEM_PREAD 0x1c
188#define DRM_I915_GEM_PWRITE 0x1d
189#define DRM_I915_GEM_MMAP 0x1e
190#define DRM_I915_GEM_SET_DOMAIN 0x1f
191#define DRM_I915_GEM_SW_FINISH 0x20
192#define DRM_I915_GEM_SET_TILING 0x21
193#define DRM_I915_GEM_GET_TILING 0x22
194#define DRM_I915_GEM_GET_APERTURE 0x23
195#define DRM_I915_GEM_MMAP_GTT 0x24
196#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
197#define DRM_I915_GEM_MADVISE 0x26
198#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
199#define DRM_I915_OVERLAY_ATTRS 0x28
200#define DRM_I915_GEM_EXECBUFFER2 0x29
201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
203#define DRM_I915_GEM_WAIT 0x2c
204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
206
207#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
208#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
209#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
210#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
211#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
212#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
213#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
214#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
215#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
216#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
217#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
218#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
219#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
220#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
221#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
222#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
223#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
224#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
225#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
226#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
227#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
228#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
229#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
230#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
231#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
232#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
233#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
234#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
235#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
236#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
237#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
238#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
239#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
240#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
241#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
242#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
243#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
244#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
245#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
246#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
247#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
248#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
249#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
250#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
251#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
252
253/* Allow drivers to submit batchbuffers directly to hardware, relying
254 * on the security mechanisms provided by hardware.
255 */
256typedef struct drm_i915_batchbuffer {
257 int start; /* agp offset */
258 int used; /* nr bytes in use */
259 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
260 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
261 int num_cliprects; /* mulitpass with multiple cliprects? */
262 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
263} drm_i915_batchbuffer_t;
264
265/* As above, but pass a pointer to userspace buffer which can be
266 * validated by the kernel prior to sending to hardware.
267 */
268typedef struct _drm_i915_cmdbuffer {
269 char __user *buf; /* pointer to userspace command buffer */
270 int sz; /* nr bytes in buf */
271 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
272 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
273 int num_cliprects; /* mulitpass with multiple cliprects? */
274 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
275} drm_i915_cmdbuffer_t;
276
277/* Userspace can request & wait on irq's:
278 */
279typedef struct drm_i915_irq_emit {
280 int __user *irq_seq;
281} drm_i915_irq_emit_t;
282
283typedef struct drm_i915_irq_wait {
284 int irq_seq;
285} drm_i915_irq_wait_t;
286
287/* Ioctl to query kernel params:
288 */
289#define I915_PARAM_IRQ_ACTIVE 1
290#define I915_PARAM_ALLOW_BATCHBUFFER 2
291#define I915_PARAM_LAST_DISPATCH 3
292#define I915_PARAM_CHIPSET_ID 4
293#define I915_PARAM_HAS_GEM 5
294#define I915_PARAM_NUM_FENCES_AVAIL 6
295#define I915_PARAM_HAS_OVERLAY 7
296#define I915_PARAM_HAS_PAGEFLIPPING 8
297#define I915_PARAM_HAS_EXECBUF2 9
298#define I915_PARAM_HAS_BSD 10
299#define I915_PARAM_HAS_BLT 11
300#define I915_PARAM_HAS_RELAXED_FENCING 12
301#define I915_PARAM_HAS_COHERENT_RINGS 13
302#define I915_PARAM_HAS_EXEC_CONSTANTS 14
303#define I915_PARAM_HAS_RELAXED_DELTA 15
304#define I915_PARAM_HAS_GEN7_SOL_RESET 16
305#define I915_PARAM_HAS_LLC 17
306#define I915_PARAM_HAS_ALIASING_PPGTT 18
307#define I915_PARAM_HAS_WAIT_TIMEOUT 19
308
309typedef struct drm_i915_getparam {
310 int param;
311 int __user *value;
312} drm_i915_getparam_t;
313
314/* Ioctl to set kernel params:
315 */
316#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
317#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
318#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
319#define I915_SETPARAM_NUM_USED_FENCES 4
320
321typedef struct drm_i915_setparam {
322 int param;
323 int value;
324} drm_i915_setparam_t;
325
326/* A memory manager for regions of shared memory:
327 */
328#define I915_MEM_REGION_AGP 1
329
330typedef struct drm_i915_mem_alloc {
331 int region;
332 int alignment;
333 int size;
334 int __user *region_offset; /* offset from start of fb or agp */
335} drm_i915_mem_alloc_t;
336
337typedef struct drm_i915_mem_free {
338 int region;
339 int region_offset;
340} drm_i915_mem_free_t;
341
342typedef struct drm_i915_mem_init_heap {
343 int region;
344 int size;
345 int start;
346} drm_i915_mem_init_heap_t;
347
348/* Allow memory manager to be torn down and re-initialized (eg on
349 * rotate):
350 */
351typedef struct drm_i915_mem_destroy_heap {
352 int region;
353} drm_i915_mem_destroy_heap_t;
354
355/* Allow X server to configure which pipes to monitor for vblank signals
356 */
357#define DRM_I915_VBLANK_PIPE_A 1
358#define DRM_I915_VBLANK_PIPE_B 2
359
360typedef struct drm_i915_vblank_pipe {
361 int pipe;
362} drm_i915_vblank_pipe_t;
363
364/* Schedule buffer swap at given vertical blank:
365 */
366typedef struct drm_i915_vblank_swap {
367 drm_drawable_t drawable;
368 enum drm_vblank_seq_type seqtype;
369 unsigned int sequence;
370} drm_i915_vblank_swap_t;
371
372typedef struct drm_i915_hws_addr {
373 __u64 addr;
374} drm_i915_hws_addr_t;
375
376struct drm_i915_gem_init {
377 /**
378 * Beginning offset in the GTT to be managed by the DRM memory
379 * manager.
380 */
381 __u64 gtt_start;
382 /**
383 * Ending offset in the GTT to be managed by the DRM memory
384 * manager.
385 */
386 __u64 gtt_end;
387};
388
389struct drm_i915_gem_create {
390 /**
391 * Requested size for the object.
392 *
393 * The (page-aligned) allocated size for the object will be returned.
394 */
395 __u64 size;
396 /**
397 * Returned handle for the object.
398 *
399 * Object handles are nonzero.
400 */
401 __u32 handle;
402 __u32 pad;
403};
404
405struct drm_i915_gem_pread {
406 /** Handle for the object being read. */
407 __u32 handle;
408 __u32 pad;
409 /** Offset into the object to read from */
410 __u64 offset;
411 /** Length of data to read */
412 __u64 size;
413 /**
414 * Pointer to write the data into.
415 *
416 * This is a fixed-size type for 32/64 compatibility.
417 */
418 __u64 data_ptr;
419};
420
421struct drm_i915_gem_pwrite {
422 /** Handle for the object being written to. */
423 __u32 handle;
424 __u32 pad;
425 /** Offset into the object to write to */
426 __u64 offset;
427 /** Length of data to write */
428 __u64 size;
429 /**
430 * Pointer to read the data from.
431 *
432 * This is a fixed-size type for 32/64 compatibility.
433 */
434 __u64 data_ptr;
435};
436
437struct drm_i915_gem_mmap {
438 /** Handle for the object being mapped. */
439 __u32 handle;
440 __u32 pad;
441 /** Offset in the object to map. */
442 __u64 offset;
443 /**
444 * Length of data to map.
445 *
446 * The value will be page-aligned.
447 */
448 __u64 size;
449 /**
450 * Returned pointer the data was mapped at.
451 *
452 * This is a fixed-size type for 32/64 compatibility.
453 */
454 __u64 addr_ptr;
455};
456
457struct drm_i915_gem_mmap_gtt {
458 /** Handle for the object being mapped. */
459 __u32 handle;
460 __u32 pad;
461 /**
462 * Fake offset to use for subsequent mmap call
463 *
464 * This is a fixed-size type for 32/64 compatibility.
465 */
466 __u64 offset;
467};
468
469struct drm_i915_gem_set_domain {
470 /** Handle for the object */
471 __u32 handle;
472
473 /** New read domains */
474 __u32 read_domains;
475
476 /** New write domain */
477 __u32 write_domain;
478};
479
480struct drm_i915_gem_sw_finish {
481 /** Handle for the object */
482 __u32 handle;
483};
484
485struct drm_i915_gem_relocation_entry {
486 /**
487 * Handle of the buffer being pointed to by this relocation entry.
488 *
489 * It's appealing to make this be an index into the mm_validate_entry
490 * list to refer to the buffer, but this allows the driver to create
491 * a relocation list for state buffers and not re-write it per
492 * exec using the buffer.
493 */
494 __u32 target_handle;
495
496 /**
497 * Value to be added to the offset of the target buffer to make up
498 * the relocation entry.
499 */
500 __u32 delta;
501
502 /** Offset in the buffer the relocation entry will be written into */
503 __u64 offset;
504
505 /**
506 * Offset value of the target buffer that the relocation entry was last
507 * written as.
508 *
509 * If the buffer has the same offset as last time, we can skip syncing
510 * and writing the relocation. This value is written back out by
511 * the execbuffer ioctl when the relocation is written.
512 */
513 __u64 presumed_offset;
514
515 /**
516 * Target memory domains read by this operation.
517 */
518 __u32 read_domains;
519
520 /**
521 * Target memory domains written by this operation.
522 *
523 * Note that only one domain may be written by the whole
524 * execbuffer operation, so that where there are conflicts,
525 * the application will get -EINVAL back.
526 */
527 __u32 write_domain;
528};
529
530/** @{
531 * Intel memory domains
532 *
533 * Most of these just align with the various caches in
534 * the system and are used to flush and invalidate as
535 * objects end up cached in different domains.
536 */
537/** CPU cache */
538#define I915_GEM_DOMAIN_CPU 0x00000001
539/** Render cache, used by 2D and 3D drawing */
540#define I915_GEM_DOMAIN_RENDER 0x00000002
541/** Sampler cache, used by texture engine */
542#define I915_GEM_DOMAIN_SAMPLER 0x00000004
543/** Command queue, used to load batch buffers */
544#define I915_GEM_DOMAIN_COMMAND 0x00000008
545/** Instruction cache, used by shader programs */
546#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
547/** Vertex address cache */
548#define I915_GEM_DOMAIN_VERTEX 0x00000020
549/** GTT domain - aperture and scanout */
550#define I915_GEM_DOMAIN_GTT 0x00000040
551/** @} */
552
553struct drm_i915_gem_exec_object {
554 /**
555 * User's handle for a buffer to be bound into the GTT for this
556 * operation.
557 */
558 __u32 handle;
559
560 /** Number of relocations to be performed on this buffer */
561 __u32 relocation_count;
562 /**
563 * Pointer to array of struct drm_i915_gem_relocation_entry containing
564 * the relocations to be performed in this buffer.
565 */
566 __u64 relocs_ptr;
567
568 /** Required alignment in graphics aperture */
569 __u64 alignment;
570
571 /**
572 * Returned value of the updated offset of the object, for future
573 * presumed_offset writes.
574 */
575 __u64 offset;
576};
577
578struct drm_i915_gem_execbuffer {
579 /**
580 * List of buffers to be validated with their relocations to be
581 * performend on them.
582 *
583 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
584 *
585 * These buffers must be listed in an order such that all relocations
586 * a buffer is performing refer to buffers that have already appeared
587 * in the validate list.
588 */
589 __u64 buffers_ptr;
590 __u32 buffer_count;
591
592 /** Offset in the batchbuffer to start execution from. */
593 __u32 batch_start_offset;
594 /** Bytes used in batchbuffer from batch_start_offset */
595 __u32 batch_len;
596 __u32 DR1;
597 __u32 DR4;
598 __u32 num_cliprects;
599 /** This is a struct drm_clip_rect *cliprects */
600 __u64 cliprects_ptr;
601};
602
603struct drm_i915_gem_exec_object2 {
604 /**
605 * User's handle for a buffer to be bound into the GTT for this
606 * operation.
607 */
608 __u32 handle;
609
610 /** Number of relocations to be performed on this buffer */
611 __u32 relocation_count;
612 /**
613 * Pointer to array of struct drm_i915_gem_relocation_entry containing
614 * the relocations to be performed in this buffer.
615 */
616 __u64 relocs_ptr;
617
618 /** Required alignment in graphics aperture */
619 __u64 alignment;
620
621 /**
622 * Returned value of the updated offset of the object, for future
623 * presumed_offset writes.
624 */
625 __u64 offset;
626
627#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
628 __u64 flags;
629 __u64 rsvd1;
630 __u64 rsvd2;
631};
632
633struct drm_i915_gem_execbuffer2 {
634 /**
635 * List of gem_exec_object2 structs
636 */
637 __u64 buffers_ptr;
638 __u32 buffer_count;
639
640 /** Offset in the batchbuffer to start execution from. */
641 __u32 batch_start_offset;
642 /** Bytes used in batchbuffer from batch_start_offset */
643 __u32 batch_len;
644 __u32 DR1;
645 __u32 DR4;
646 __u32 num_cliprects;
647 /** This is a struct drm_clip_rect *cliprects */
648 __u64 cliprects_ptr;
649#define I915_EXEC_RING_MASK (7<<0)
650#define I915_EXEC_DEFAULT (0<<0)
651#define I915_EXEC_RENDER (1<<0)
652#define I915_EXEC_BSD (2<<0)
653#define I915_EXEC_BLT (3<<0)
654
655/* Used for switching the constants addressing mode on gen4+ RENDER ring.
656 * Gen6+ only supports relative addressing to dynamic state (default) and
657 * absolute addressing.
658 *
659 * These flags are ignored for the BSD and BLT rings.
660 */
661#define I915_EXEC_CONSTANTS_MASK (3<<6)
662#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
663#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
664#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
665 __u64 flags;
666 __u64 rsvd1; /* now used for context info */
667 __u64 rsvd2;
668};
669
670/** Resets the SO write offset registers for transform feedback on gen7. */
671#define I915_EXEC_GEN7_SOL_RESET (1<<8)
672
673#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
674#define i915_execbuffer2_set_context_id(eb2, context) \
675 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
676#define i915_execbuffer2_get_context_id(eb2) \
677 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
678
679struct drm_i915_gem_pin {
680 /** Handle of the buffer to be pinned. */
681 __u32 handle;
682 __u32 pad;
683
684 /** alignment required within the aperture */
685 __u64 alignment;
686
687 /** Returned GTT offset of the buffer. */
688 __u64 offset;
689};
690
691struct drm_i915_gem_unpin {
692 /** Handle of the buffer to be unpinned. */
693 __u32 handle;
694 __u32 pad;
695};
696
697struct drm_i915_gem_busy {
698 /** Handle of the buffer to check for busy */
699 __u32 handle;
700
701 /** Return busy status (1 if busy, 0 if idle) */
702 __u32 busy;
703};
704
705#define I915_TILING_NONE 0
706#define I915_TILING_X 1
707#define I915_TILING_Y 2
708
709#define I915_BIT_6_SWIZZLE_NONE 0
710#define I915_BIT_6_SWIZZLE_9 1
711#define I915_BIT_6_SWIZZLE_9_10 2
712#define I915_BIT_6_SWIZZLE_9_11 3
713#define I915_BIT_6_SWIZZLE_9_10_11 4
714/* Not seen by userland */
715#define I915_BIT_6_SWIZZLE_UNKNOWN 5
716/* Seen by userland. */
717#define I915_BIT_6_SWIZZLE_9_17 6
718#define I915_BIT_6_SWIZZLE_9_10_17 7
719
720struct drm_i915_gem_set_tiling {
721 /** Handle of the buffer to have its tiling state updated */
722 __u32 handle;
723
724 /**
725 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
726 * I915_TILING_Y).
727 *
728 * This value is to be set on request, and will be updated by the
729 * kernel on successful return with the actual chosen tiling layout.
730 *
731 * The tiling mode may be demoted to I915_TILING_NONE when the system
732 * has bit 6 swizzling that can't be managed correctly by GEM.
733 *
734 * Buffer contents become undefined when changing tiling_mode.
735 */
736 __u32 tiling_mode;
737
738 /**
739 * Stride in bytes for the object when in I915_TILING_X or
740 * I915_TILING_Y.
741 */
742 __u32 stride;
743
744 /**
745 * Returned address bit 6 swizzling required for CPU access through
746 * mmap mapping.
747 */
748 __u32 swizzle_mode;
749};
750
751struct drm_i915_gem_get_tiling {
752 /** Handle of the buffer to get tiling state for. */
753 __u32 handle;
754
755 /**
756 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
757 * I915_TILING_Y).
758 */
759 __u32 tiling_mode;
760
761 /**
762 * Returned address bit 6 swizzling required for CPU access through
763 * mmap mapping.
764 */
765 __u32 swizzle_mode;
766};
767
768struct drm_i915_gem_get_aperture {
769 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
770 __u64 aper_size;
771
772 /**
773 * Available space in the aperture used by i915_gem_execbuffer, in
774 * bytes
775 */
776 __u64 aper_available_size;
777};
778
779struct drm_i915_get_pipe_from_crtc_id {
780 /** ID of CRTC being requested **/
781 __u32 crtc_id;
782
783 /** pipe of requested CRTC **/
784 __u32 pipe;
785};
786
787#define I915_MADV_WILLNEED 0
788#define I915_MADV_DONTNEED 1
789#define __I915_MADV_PURGED 2 /* internal state */
790
791struct drm_i915_gem_madvise {
792 /** Handle of the buffer to change the backing store advice */
793 __u32 handle;
794
795 /* Advice: either the buffer will be needed again in the near future,
796 * or wont be and could be discarded under memory pressure.
797 */
798 __u32 madv;
799
800 /** Whether the backing store still exists. */
801 __u32 retained;
802};
803
804/* flags */
805#define I915_OVERLAY_TYPE_MASK 0xff
806#define I915_OVERLAY_YUV_PLANAR 0x01
807#define I915_OVERLAY_YUV_PACKED 0x02
808#define I915_OVERLAY_RGB 0x03
809
810#define I915_OVERLAY_DEPTH_MASK 0xff00
811#define I915_OVERLAY_RGB24 0x1000
812#define I915_OVERLAY_RGB16 0x2000
813#define I915_OVERLAY_RGB15 0x3000
814#define I915_OVERLAY_YUV422 0x0100
815#define I915_OVERLAY_YUV411 0x0200
816#define I915_OVERLAY_YUV420 0x0300
817#define I915_OVERLAY_YUV410 0x0400
818
819#define I915_OVERLAY_SWAP_MASK 0xff0000
820#define I915_OVERLAY_NO_SWAP 0x000000
821#define I915_OVERLAY_UV_SWAP 0x010000
822#define I915_OVERLAY_Y_SWAP 0x020000
823#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
824
825#define I915_OVERLAY_FLAGS_MASK 0xff000000
826#define I915_OVERLAY_ENABLE 0x01000000
827
828struct drm_intel_overlay_put_image {
829 /* various flags and src format description */
830 __u32 flags;
831 /* source picture description */
832 __u32 bo_handle;
833 /* stride values and offsets are in bytes, buffer relative */
834 __u16 stride_Y; /* stride for packed formats */
835 __u16 stride_UV;
836 __u32 offset_Y; /* offset for packet formats */
837 __u32 offset_U;
838 __u32 offset_V;
839 /* in pixels */
840 __u16 src_width;
841 __u16 src_height;
842 /* to compensate the scaling factors for partially covered surfaces */
843 __u16 src_scan_width;
844 __u16 src_scan_height;
845 /* output crtc description */
846 __u32 crtc_id;
847 __u16 dst_x;
848 __u16 dst_y;
849 __u16 dst_width;
850 __u16 dst_height;
851};
852
853/* flags */
854#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
855#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
856struct drm_intel_overlay_attrs {
857 __u32 flags;
858 __u32 color_key;
859 __s32 brightness;
860 __u32 contrast;
861 __u32 saturation;
862 __u32 gamma0;
863 __u32 gamma1;
864 __u32 gamma2;
865 __u32 gamma3;
866 __u32 gamma4;
867 __u32 gamma5;
868};
869
870/*
871 * Intel sprite handling
872 *
873 * Color keying works with a min/mask/max tuple. Both source and destination
874 * color keying is allowed.
875 *
876 * Source keying:
877 * Sprite pixels within the min & max values, masked against the color channels
878 * specified in the mask field, will be transparent. All other pixels will
879 * be displayed on top of the primary plane. For RGB surfaces, only the min
880 * and mask fields will be used; ranged compares are not allowed.
881 *
882 * Destination keying:
883 * Primary plane pixels that match the min value, masked against the color
884 * channels specified in the mask field, will be replaced by corresponding
885 * pixels from the sprite plane.
886 *
887 * Note that source & destination keying are exclusive; only one can be
888 * active on a given plane.
889 */
890
891#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
892#define I915_SET_COLORKEY_DESTINATION (1<<1)
893#define I915_SET_COLORKEY_SOURCE (1<<2)
894struct drm_intel_sprite_colorkey {
895 __u32 plane_id;
896 __u32 min_value;
897 __u32 channel_mask;
898 __u32 max_value;
899 __u32 flags;
900};
901
902struct drm_i915_gem_wait {
903 /** Handle of BO we shall wait on */
904 __u32 bo_handle;
905 __u32 flags;
906 /** Number of nanoseconds to wait, Returns time remaining. */
907 __s64 timeout_ns;
908};
909
910struct drm_i915_gem_context_create {
911 /* output: id of new context*/
912 __u32 ctx_id;
913 __u32 pad;
914};
915
916struct drm_i915_gem_context_destroy {
917 __u32 ctx_id;
918 __u32 pad;
919};
920
921#endif /* _I915_DRM_H_ */ 37#endif /* _I915_DRM_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 05:34:01 -0500