diff options
Diffstat (limited to 'include/drm/i810_drm.h')
-rw-r--r-- | include/drm/i810_drm.h | 281 |
1 files changed, 281 insertions, 0 deletions
diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h new file mode 100644 index 000000000000..7a10bb6f2c0f --- /dev/null +++ b/include/drm/i810_drm.h | |||
@@ -0,0 +1,281 @@ | |||
1 | #ifndef _I810_DRM_H_ | ||
2 | #define _I810_DRM_H_ | ||
3 | |||
4 | /* WARNING: These defines must be the same as what the Xserver uses. | ||
5 | * if you change them, you must change the defines in the Xserver. | ||
6 | */ | ||
7 | |||
8 | #ifndef _I810_DEFINES_ | ||
9 | #define _I810_DEFINES_ | ||
10 | |||
11 | #define I810_DMA_BUF_ORDER 12 | ||
12 | #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) | ||
13 | #define I810_DMA_BUF_NR 256 | ||
14 | #define I810_NR_SAREA_CLIPRECTS 8 | ||
15 | |||
16 | /* Each region is a minimum of 64k, and there are at most 64 of them. | ||
17 | */ | ||
18 | #define I810_NR_TEX_REGIONS 64 | ||
19 | #define I810_LOG_MIN_TEX_REGION_SIZE 16 | ||
20 | #endif | ||
21 | |||
22 | #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ | ||
23 | #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ | ||
24 | #define I810_UPLOAD_CTX 0x4 | ||
25 | #define I810_UPLOAD_BUFFERS 0x8 | ||
26 | #define I810_UPLOAD_TEX0 0x10 | ||
27 | #define I810_UPLOAD_TEX1 0x20 | ||
28 | #define I810_UPLOAD_CLIPRECTS 0x40 | ||
29 | |||
30 | /* Indices into buf.Setup where various bits of state are mirrored per | ||
31 | * context and per buffer. These can be fired at the card as a unit, | ||
32 | * or in a piecewise fashion as required. | ||
33 | */ | ||
34 | |||
35 | /* Destbuffer state | ||
36 | * - backbuffer linear offset and pitch -- invarient in the current dri | ||
37 | * - zbuffer linear offset and pitch -- also invarient | ||
38 | * - drawing origin in back and depth buffers. | ||
39 | * | ||
40 | * Keep the depth/back buffer state here to accommodate private buffers | ||
41 | * in the future. | ||
42 | */ | ||
43 | #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ | ||
44 | #define I810_DESTREG_DI1 1 | ||
45 | #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ | ||
46 | #define I810_DESTREG_DV1 3 | ||
47 | #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ | ||
48 | #define I810_DESTREG_DR1 5 | ||
49 | #define I810_DESTREG_DR2 6 | ||
50 | #define I810_DESTREG_DR3 7 | ||
51 | #define I810_DESTREG_DR4 8 | ||
52 | #define I810_DEST_SETUP_SIZE 10 | ||
53 | |||
54 | /* Context state | ||
55 | */ | ||
56 | #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ | ||
57 | #define I810_CTXREG_CF1 1 | ||
58 | #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ | ||
59 | #define I810_CTXREG_ST1 3 | ||
60 | #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ | ||
61 | #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ | ||
62 | #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ | ||
63 | #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ | ||
64 | #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ | ||
65 | #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ | ||
66 | #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ | ||
67 | #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ | ||
68 | #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ | ||
69 | #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ | ||
70 | #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ | ||
71 | #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ | ||
72 | #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ | ||
73 | #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ | ||
74 | #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ | ||
75 | #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ | ||
76 | #define I810_CTX_SETUP_SIZE 20 | ||
77 | |||
78 | /* Texture state (per tex unit) | ||
79 | */ | ||
80 | #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ | ||
81 | #define I810_TEXREG_MI1 1 | ||
82 | #define I810_TEXREG_MI2 2 | ||
83 | #define I810_TEXREG_MI3 3 | ||
84 | #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ | ||
85 | #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ | ||
86 | #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ | ||
87 | #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ | ||
88 | #define I810_TEX_SETUP_SIZE 8 | ||
89 | |||
90 | /* Flags for clear ioctl | ||
91 | */ | ||
92 | #define I810_FRONT 0x1 | ||
93 | #define I810_BACK 0x2 | ||
94 | #define I810_DEPTH 0x4 | ||
95 | |||
96 | typedef enum _drm_i810_init_func { | ||
97 | I810_INIT_DMA = 0x01, | ||
98 | I810_CLEANUP_DMA = 0x02, | ||
99 | I810_INIT_DMA_1_4 = 0x03 | ||
100 | } drm_i810_init_func_t; | ||
101 | |||
102 | /* This is the init structure after v1.2 */ | ||
103 | typedef struct _drm_i810_init { | ||
104 | drm_i810_init_func_t func; | ||
105 | unsigned int mmio_offset; | ||
106 | unsigned int buffers_offset; | ||
107 | int sarea_priv_offset; | ||
108 | unsigned int ring_start; | ||
109 | unsigned int ring_end; | ||
110 | unsigned int ring_size; | ||
111 | unsigned int front_offset; | ||
112 | unsigned int back_offset; | ||
113 | unsigned int depth_offset; | ||
114 | unsigned int overlay_offset; | ||
115 | unsigned int overlay_physical; | ||
116 | unsigned int w; | ||
117 | unsigned int h; | ||
118 | unsigned int pitch; | ||
119 | unsigned int pitch_bits; | ||
120 | } drm_i810_init_t; | ||
121 | |||
122 | /* This is the init structure prior to v1.2 */ | ||
123 | typedef struct _drm_i810_pre12_init { | ||
124 | drm_i810_init_func_t func; | ||
125 | unsigned int mmio_offset; | ||
126 | unsigned int buffers_offset; | ||
127 | int sarea_priv_offset; | ||
128 | unsigned int ring_start; | ||
129 | unsigned int ring_end; | ||
130 | unsigned int ring_size; | ||
131 | unsigned int front_offset; | ||
132 | unsigned int back_offset; | ||
133 | unsigned int depth_offset; | ||
134 | unsigned int w; | ||
135 | unsigned int h; | ||
136 | unsigned int pitch; | ||
137 | unsigned int pitch_bits; | ||
138 | } drm_i810_pre12_init_t; | ||
139 | |||
140 | /* Warning: If you change the SAREA structure you must change the Xserver | ||
141 | * structure as well */ | ||
142 | |||
143 | typedef struct _drm_i810_tex_region { | ||
144 | unsigned char next, prev; /* indices to form a circular LRU */ | ||
145 | unsigned char in_use; /* owned by a client, or free? */ | ||
146 | int age; /* tracked by clients to update local LRU's */ | ||
147 | } drm_i810_tex_region_t; | ||
148 | |||
149 | typedef struct _drm_i810_sarea { | ||
150 | unsigned int ContextState[I810_CTX_SETUP_SIZE]; | ||
151 | unsigned int BufferState[I810_DEST_SETUP_SIZE]; | ||
152 | unsigned int TexState[2][I810_TEX_SETUP_SIZE]; | ||
153 | unsigned int dirty; | ||
154 | |||
155 | unsigned int nbox; | ||
156 | struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS]; | ||
157 | |||
158 | /* Maintain an LRU of contiguous regions of texture space. If | ||
159 | * you think you own a region of texture memory, and it has an | ||
160 | * age different to the one you set, then you are mistaken and | ||
161 | * it has been stolen by another client. If global texAge | ||
162 | * hasn't changed, there is no need to walk the list. | ||
163 | * | ||
164 | * These regions can be used as a proxy for the fine-grained | ||
165 | * texture information of other clients - by maintaining them | ||
166 | * in the same lru which is used to age their own textures, | ||
167 | * clients have an approximate lru for the whole of global | ||
168 | * texture space, and can make informed decisions as to which | ||
169 | * areas to kick out. There is no need to choose whether to | ||
170 | * kick out your own texture or someone else's - simply eject | ||
171 | * them all in LRU order. | ||
172 | */ | ||
173 | |||
174 | drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; | ||
175 | /* Last elt is sentinal */ | ||
176 | int texAge; /* last time texture was uploaded */ | ||
177 | int last_enqueue; /* last time a buffer was enqueued */ | ||
178 | int last_dispatch; /* age of the most recently dispatched buffer */ | ||
179 | int last_quiescent; /* */ | ||
180 | int ctxOwner; /* last context to upload state */ | ||
181 | |||
182 | int vertex_prim; | ||
183 | |||
184 | int pf_enabled; /* is pageflipping allowed? */ | ||
185 | int pf_active; | ||
186 | int pf_current_page; /* which buffer is being displayed? */ | ||
187 | } drm_i810_sarea_t; | ||
188 | |||
189 | /* WARNING: If you change any of these defines, make sure to change the | ||
190 | * defines in the Xserver file (xf86drmMga.h) | ||
191 | */ | ||
192 | |||
193 | /* i810 specific ioctls | ||
194 | * The device specific ioctl range is 0x40 to 0x79. | ||
195 | */ | ||
196 | #define DRM_I810_INIT 0x00 | ||
197 | #define DRM_I810_VERTEX 0x01 | ||
198 | #define DRM_I810_CLEAR 0x02 | ||
199 | #define DRM_I810_FLUSH 0x03 | ||
200 | #define DRM_I810_GETAGE 0x04 | ||
201 | #define DRM_I810_GETBUF 0x05 | ||
202 | #define DRM_I810_SWAP 0x06 | ||
203 | #define DRM_I810_COPY 0x07 | ||
204 | #define DRM_I810_DOCOPY 0x08 | ||
205 | #define DRM_I810_OV0INFO 0x09 | ||
206 | #define DRM_I810_FSTATUS 0x0a | ||
207 | #define DRM_I810_OV0FLIP 0x0b | ||
208 | #define DRM_I810_MC 0x0c | ||
209 | #define DRM_I810_RSTATUS 0x0d | ||
210 | #define DRM_I810_FLIP 0x0e | ||
211 | |||
212 | #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) | ||
213 | #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) | ||
214 | #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) | ||
215 | #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) | ||
216 | #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) | ||
217 | #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) | ||
218 | #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) | ||
219 | #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) | ||
220 | #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) | ||
221 | #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) | ||
222 | #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) | ||
223 | #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) | ||
224 | #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) | ||
225 | #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) | ||
226 | #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) | ||
227 | |||
228 | typedef struct _drm_i810_clear { | ||
229 | int clear_color; | ||
230 | int clear_depth; | ||
231 | int flags; | ||
232 | } drm_i810_clear_t; | ||
233 | |||
234 | /* These may be placeholders if we have more cliprects than | ||
235 | * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to | ||
236 | * false, indicating that the buffer will be dispatched again with a | ||
237 | * new set of cliprects. | ||
238 | */ | ||
239 | typedef struct _drm_i810_vertex { | ||
240 | int idx; /* buffer index */ | ||
241 | int used; /* nr bytes in use */ | ||
242 | int discard; /* client is finished with the buffer? */ | ||
243 | } drm_i810_vertex_t; | ||
244 | |||
245 | typedef struct _drm_i810_copy_t { | ||
246 | int idx; /* buffer index */ | ||
247 | int used; /* nr bytes in use */ | ||
248 | void *address; /* Address to copy from */ | ||
249 | } drm_i810_copy_t; | ||
250 | |||
251 | #define PR_TRIANGLES (0x0<<18) | ||
252 | #define PR_TRISTRIP_0 (0x1<<18) | ||
253 | #define PR_TRISTRIP_1 (0x2<<18) | ||
254 | #define PR_TRIFAN (0x3<<18) | ||
255 | #define PR_POLYGON (0x4<<18) | ||
256 | #define PR_LINES (0x5<<18) | ||
257 | #define PR_LINESTRIP (0x6<<18) | ||
258 | #define PR_RECTS (0x7<<18) | ||
259 | #define PR_MASK (0x7<<18) | ||
260 | |||
261 | typedef struct drm_i810_dma { | ||
262 | void *virtual; | ||
263 | int request_idx; | ||
264 | int request_size; | ||
265 | int granted; | ||
266 | } drm_i810_dma_t; | ||
267 | |||
268 | typedef struct _drm_i810_overlay_t { | ||
269 | unsigned int offset; /* Address of the Overlay Regs */ | ||
270 | unsigned int physical; | ||
271 | } drm_i810_overlay_t; | ||
272 | |||
273 | typedef struct _drm_i810_mc { | ||
274 | int idx; /* buffer index */ | ||
275 | int used; /* nr bytes in use */ | ||
276 | int num_blocks; /* number of GFXBlocks */ | ||
277 | int *length; /* List of lengths for GFXBlocks (FUTURE) */ | ||
278 | unsigned int last_render; /* Last Render Request */ | ||
279 | } drm_i810_mc_t; | ||
280 | |||
281 | #endif /* _I810_DRM_H_ */ | ||