aboutsummaryrefslogtreecommitdiffstats
path: root/include/drm/drm_dp_helper.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/drm/drm_dp_helper.h')
-rw-r--r--include/drm/drm_dp_helper.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index fe061489f91f..e8e1417af3d9 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -25,6 +25,7 @@
25 25
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/i2c.h> 27#include <linux/i2c.h>
28#include <linux/delay.h>
28 29
29/* 30/*
30 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
@@ -311,6 +312,14 @@
311#define MODE_I2C_READ 4 312#define MODE_I2C_READ 4
312#define MODE_I2C_STOP 8 313#define MODE_I2C_STOP 8
313 314
315/**
316 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
317 * aux algorithm
318 * @running: set by the algo indicating whether an i2c is ongoing or whether
319 * the i2c bus is quiescent
320 * @address: i2c target address for the currently ongoing transfer
321 * @aux_ch: driver callback to transfer a single byte of the i2c payload
322 */
314struct i2c_algo_dp_aux_data { 323struct i2c_algo_dp_aux_data {
315 bool running; 324 bool running;
316 u16 address; 325 u16 address;
@@ -322,4 +331,34 @@ struct i2c_algo_dp_aux_data {
322int 331int
323i2c_dp_aux_add_bus(struct i2c_adapter *adapter); 332i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
324 333
334
335#define DP_LINK_STATUS_SIZE 6
336bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
337 int lane_count);
338bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
339 int lane_count);
340u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
341 int lane);
342u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
343 int lane);
344
345#define DP_RECEIVER_CAP_SIZE 0xf
346void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
347void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
348
349u8 drm_dp_link_rate_to_bw_code(int link_rate);
350int drm_dp_bw_code_to_link_rate(u8 link_bw);
351
352static inline int
353drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
354{
355 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
356}
357
358static inline u8
359drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
360{
361 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
362}
363
325#endif /* _DRM_DP_HELPER_H_ */ 364#endif /* _DRM_DP_HELPER_H_ */