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-rw-r--r--include/asm-xtensa/Kbuild1
-rw-r--r--include/asm-xtensa/asmmacro.h153
-rw-r--r--include/asm-xtensa/atomic.h300
-rw-r--r--include/asm-xtensa/auxvec.h4
-rw-r--r--include/asm-xtensa/bitops.h121
-rw-r--r--include/asm-xtensa/bootparam.h61
-rw-r--r--include/asm-xtensa/bug.h18
-rw-r--r--include/asm-xtensa/bugs.h18
-rw-r--r--include/asm-xtensa/byteorder.h80
-rw-r--r--include/asm-xtensa/cache.h33
-rw-r--r--include/asm-xtensa/cacheasm.h177
-rw-r--r--include/asm-xtensa/cacheflush.h155
-rw-r--r--include/asm-xtensa/checksum.h250
-rw-r--r--include/asm-xtensa/coprocessor.h177
-rw-r--r--include/asm-xtensa/cpumask.h16
-rw-r--r--include/asm-xtensa/cputime.h6
-rw-r--r--include/asm-xtensa/current.h38
-rw-r--r--include/asm-xtensa/delay.h49
-rw-r--r--include/asm-xtensa/device.h7
-rw-r--r--include/asm-xtensa/div64.h16
-rw-r--r--include/asm-xtensa/dma-mapping.h179
-rw-r--r--include/asm-xtensa/dma.h61
-rw-r--r--include/asm-xtensa/elf.h205
-rw-r--r--include/asm-xtensa/emergency-restart.h6
-rw-r--r--include/asm-xtensa/errno.h16
-rw-r--r--include/asm-xtensa/fb.h12
-rw-r--r--include/asm-xtensa/fcntl.h1
-rw-r--r--include/asm-xtensa/futex.h1
-rw-r--r--include/asm-xtensa/hardirq.h28
-rw-r--r--include/asm-xtensa/highmem.h17
-rw-r--r--include/asm-xtensa/hw_irq.h14
-rw-r--r--include/asm-xtensa/io.h200
-rw-r--r--include/asm-xtensa/ioctl.h1
-rw-r--r--include/asm-xtensa/ioctls.h116
-rw-r--r--include/asm-xtensa/ipcbuf.h37
-rw-r--r--include/asm-xtensa/irq.h30
-rw-r--r--include/asm-xtensa/irq_regs.h1
-rw-r--r--include/asm-xtensa/kdebug.h1
-rw-r--r--include/asm-xtensa/kmap_types.h31
-rw-r--r--include/asm-xtensa/linkage.h16
-rw-r--r--include/asm-xtensa/local.h16
-rw-r--r--include/asm-xtensa/mman.h84
-rw-r--r--include/asm-xtensa/mmu.h17
-rw-r--r--include/asm-xtensa/mmu_context.h136
-rw-r--r--include/asm-xtensa/module.h27
-rw-r--r--include/asm-xtensa/msgbuf.h48
-rw-r--r--include/asm-xtensa/mutex.h9
-rw-r--r--include/asm-xtensa/page.h174
-rw-r--r--include/asm-xtensa/param.h34
-rw-r--r--include/asm-xtensa/pci-bridge.h88
-rw-r--r--include/asm-xtensa/pci.h82
-rw-r--r--include/asm-xtensa/percpu.h16
-rw-r--r--include/asm-xtensa/pgalloc.h73
-rw-r--r--include/asm-xtensa/pgtable.h416
-rw-r--r--include/asm-xtensa/platform-iss/hardware.h29
-rw-r--r--include/asm-xtensa/platform-iss/simcall.h62
-rw-r--r--include/asm-xtensa/platform.h91
-rw-r--r--include/asm-xtensa/poll.h20
-rw-r--r--include/asm-xtensa/posix_types.h122
-rw-r--r--include/asm-xtensa/processor.h193
-rw-r--r--include/asm-xtensa/ptrace.h135
-rw-r--r--include/asm-xtensa/regs.h145
-rw-r--r--include/asm-xtensa/resource.h16
-rw-r--r--include/asm-xtensa/rmap.h16
-rw-r--r--include/asm-xtensa/rwsem.h168
-rw-r--r--include/asm-xtensa/scatterlist.h39
-rw-r--r--include/asm-xtensa/sections.h16
-rw-r--r--include/asm-xtensa/segment.h16
-rw-r--r--include/asm-xtensa/sembuf.h44
-rw-r--r--include/asm-xtensa/serial.h18
-rw-r--r--include/asm-xtensa/setup.h16
-rw-r--r--include/asm-xtensa/shmbuf.h71
-rw-r--r--include/asm-xtensa/shmparam.h21
-rw-r--r--include/asm-xtensa/sigcontext.h28
-rw-r--r--include/asm-xtensa/siginfo.h16
-rw-r--r--include/asm-xtensa/signal.h172
-rw-r--r--include/asm-xtensa/smp.h27
-rw-r--r--include/asm-xtensa/socket.h68
-rw-r--r--include/asm-xtensa/sockios.h31
-rw-r--r--include/asm-xtensa/spinlock.h16
-rw-r--r--include/asm-xtensa/stat.h59
-rw-r--r--include/asm-xtensa/statfs.h17
-rw-r--r--include/asm-xtensa/string.h124
-rw-r--r--include/asm-xtensa/syscall.h42
-rw-r--r--include/asm-xtensa/system.h215
-rw-r--r--include/asm-xtensa/termbits.h219
-rw-r--r--include/asm-xtensa/termios.h105
-rw-r--r--include/asm-xtensa/thread_info.h164
-rw-r--r--include/asm-xtensa/timex.h96
-rw-r--r--include/asm-xtensa/tlb.h47
-rw-r--r--include/asm-xtensa/tlbflush.h191
-rw-r--r--include/asm-xtensa/topology.h16
-rw-r--r--include/asm-xtensa/types.h42
-rw-r--r--include/asm-xtensa/uaccess.h500
-rw-r--r--include/asm-xtensa/ucontext.h22
-rw-r--r--include/asm-xtensa/unaligned.h29
-rw-r--r--include/asm-xtensa/unistd.h735
-rw-r--r--include/asm-xtensa/user.h20
-rw-r--r--include/asm-xtensa/variant-dc232b/core.h424
-rw-r--r--include/asm-xtensa/variant-dc232b/tie-asm.h122
-rw-r--r--include/asm-xtensa/variant-dc232b/tie.h131
-rw-r--r--include/asm-xtensa/variant-fsf/core.h359
-rw-r--r--include/asm-xtensa/variant-fsf/tie-asm.h70
-rw-r--r--include/asm-xtensa/variant-fsf/tie.h77
-rw-r--r--include/asm-xtensa/vga.h19
-rw-r--r--include/asm-xtensa/xor.h16
106 files changed, 0 insertions, 9330 deletions
diff --git a/include/asm-xtensa/Kbuild b/include/asm-xtensa/Kbuild
deleted file mode 100644
index c68e1680da01..000000000000
--- a/include/asm-xtensa/Kbuild
+++ /dev/null
@@ -1 +0,0 @@
1include include/asm-generic/Kbuild.asm
diff --git a/include/asm-xtensa/asmmacro.h b/include/asm-xtensa/asmmacro.h
deleted file mode 100644
index 76915cabad17..000000000000
--- a/include/asm-xtensa/asmmacro.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * include/asm-xtensa/asmmacro.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_ASMMACRO_H
12#define _XTENSA_ASMMACRO_H
13
14#include <asm/variant/core.h>
15
16/*
17 * Some little helpers for loops. Use zero-overhead-loops
18 * where applicable and if supported by the processor.
19 *
20 * __loopi ar, at, size, inc
21 * ar register initialized with the start address
22 * at scratch register used by macro
23 * size size immediate value
24 * inc increment
25 *
26 * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
27 * ar register initialized with the start address
28 * as register initialized with the size
29 * at scratch register use by macro
30 * inc_log2 increment [in log2]
31 * mask_log2 mask [in log2]
32 * cond true condition (used in loop'cond')
33 * ncond false condition (used in b'ncond')
34 *
35 * __loop as
36 * restart loop. 'as' register must not have been modified!
37 *
38 * __endla ar, at, incr
39 * ar start address (modified)
40 * as scratch register used by macro
41 * inc increment
42 */
43
44/*
45 * loop for given size as immediate
46 */
47
48 .macro __loopi ar, at, size, incr
49
50#if XCHAL_HAVE_LOOPS
51 movi \at, ((\size + \incr - 1) / (\incr))
52 loop \at, 99f
53#else
54 addi \at, \ar, \size
55 98:
56#endif
57
58 .endm
59
60/*
61 * loop for given size in register
62 */
63
64 .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
65
66#if XCHAL_HAVE_LOOPS
67 .ifgt \incr_log2 - 1
68 addi \at, \as, (1 << \incr_log2) - 1
69 .ifnc \mask_log2,
70 extui \at, \at, \incr_log2, \mask_log2
71 .else
72 srli \at, \at, \incr_log2
73 .endif
74 .endif
75 loop\cond \at, 99f
76#else
77 .ifnc \mask_log2,
78 extui \at, \as, \incr_log2, \mask_log2
79 .else
80 .ifnc \ncond,
81 srli \at, \as, \incr_log2
82 .endif
83 .endif
84 .ifnc \ncond,
85 b\ncond \at, 99f
86
87 .endif
88 .ifnc \mask_log2,
89 slli \at, \at, \incr_log2
90 add \at, \ar, \at
91 .else
92 add \at, \ar, \as
93 .endif
94#endif
95 98:
96
97 .endm
98
99/*
100 * loop from ar to ax
101 */
102
103 .macro __loopt ar, as, at, incr_log2
104
105#if XCHAL_HAVE_LOOPS
106 sub \at, \as, \ar
107 .ifgt \incr_log2 - 1
108 addi \at, \at, (1 << \incr_log2) - 1
109 srli \at, \at, \incr_log2
110 .endif
111 loop \at, 99f
112#else
113 98:
114#endif
115
116 .endm
117
118/*
119 * restart loop. registers must be unchanged
120 */
121
122 .macro __loop as
123
124#if XCHAL_HAVE_LOOPS
125 loop \as, 99f
126#else
127 98:
128#endif
129
130 .endm
131
132/*
133 * end of loop with no increment of the address.
134 */
135
136 .macro __endl ar, as
137#if !XCHAL_HAVE_LOOPS
138 bltu \ar, \as, 98b
139#endif
140 99:
141 .endm
142
143/*
144 * end of loop with increment of the address.
145 */
146
147 .macro __endla ar, as, incr
148 addi \ar, \ar, \incr
149 __endl \ar \as
150 .endm
151
152
153#endif /* _XTENSA_ASMMACRO_H */
diff --git a/include/asm-xtensa/atomic.h b/include/asm-xtensa/atomic.h
deleted file mode 100644
index b3b23540f14d..000000000000
--- a/include/asm-xtensa/atomic.h
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * include/asm-xtensa/atomic.h
3 *
4 * Atomic operations that C can't guarantee us. Useful for resource counting..
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_ATOMIC_H
14#define _XTENSA_ATOMIC_H
15
16#include <linux/stringify.h>
17
18typedef struct { volatile int counter; } atomic_t;
19
20#ifdef __KERNEL__
21#include <asm/processor.h>
22#include <asm/system.h>
23
24#define ATOMIC_INIT(i) { (i) }
25
26/*
27 * This Xtensa implementation assumes that the right mechanism
28 * for exclusion is for locking interrupts to level 1.
29 *
30 * Locking interrupts looks like this:
31 *
32 * rsil a15, 1
33 * <code>
34 * wsr a15, PS
35 * rsync
36 *
37 * Note that a15 is used here because the register allocation
38 * done by the compiler is not guaranteed and a window overflow
39 * may not occur between the rsil and wsr instructions. By using
40 * a15 in the rsil, the machine is guaranteed to be in a state
41 * where no register reference will cause an overflow.
42 */
43
44/**
45 * atomic_read - read atomic variable
46 * @v: pointer of type atomic_t
47 *
48 * Atomically reads the value of @v.
49 */
50#define atomic_read(v) ((v)->counter)
51
52/**
53 * atomic_set - set atomic variable
54 * @v: pointer of type atomic_t
55 * @i: required value
56 *
57 * Atomically sets the value of @v to @i.
58 */
59#define atomic_set(v,i) ((v)->counter = (i))
60
61/**
62 * atomic_add - add integer to atomic variable
63 * @i: integer value to add
64 * @v: pointer of type atomic_t
65 *
66 * Atomically adds @i to @v.
67 */
68static inline void atomic_add(int i, atomic_t * v)
69{
70 unsigned int vval;
71
72 __asm__ __volatile__(
73 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
74 "l32i %0, %2, 0 \n\t"
75 "add %0, %0, %1 \n\t"
76 "s32i %0, %2, 0 \n\t"
77 "wsr a15, "__stringify(PS)" \n\t"
78 "rsync \n"
79 : "=&a" (vval)
80 : "a" (i), "a" (v)
81 : "a15", "memory"
82 );
83}
84
85/**
86 * atomic_sub - subtract the atomic variable
87 * @i: integer value to subtract
88 * @v: pointer of type atomic_t
89 *
90 * Atomically subtracts @i from @v.
91 */
92static inline void atomic_sub(int i, atomic_t *v)
93{
94 unsigned int vval;
95
96 __asm__ __volatile__(
97 "rsil a15, "__stringify(LOCKLEVEL)"\n\t"
98 "l32i %0, %2, 0 \n\t"
99 "sub %0, %0, %1 \n\t"
100 "s32i %0, %2, 0 \n\t"
101 "wsr a15, "__stringify(PS)" \n\t"
102 "rsync \n"
103 : "=&a" (vval)
104 : "a" (i), "a" (v)
105 : "a15", "memory"
106 );
107}
108
109/*
110 * We use atomic_{add|sub}_return to define other functions.
111 */
112
113static inline int atomic_add_return(int i, atomic_t * v)
114{
115 unsigned int vval;
116
117 __asm__ __volatile__(
118 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
119 "l32i %0, %2, 0 \n\t"
120 "add %0, %0, %1 \n\t"
121 "s32i %0, %2, 0 \n\t"
122 "wsr a15, "__stringify(PS)" \n\t"
123 "rsync \n"
124 : "=&a" (vval)
125 : "a" (i), "a" (v)
126 : "a15", "memory"
127 );
128
129 return vval;
130}
131
132static inline int atomic_sub_return(int i, atomic_t * v)
133{
134 unsigned int vval;
135
136 __asm__ __volatile__(
137 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
138 "l32i %0, %2, 0 \n\t"
139 "sub %0, %0, %1 \n\t"
140 "s32i %0, %2, 0 \n\t"
141 "wsr a15, "__stringify(PS)" \n\t"
142 "rsync \n"
143 : "=&a" (vval)
144 : "a" (i), "a" (v)
145 : "a15", "memory"
146 );
147
148 return vval;
149}
150
151/**
152 * atomic_sub_and_test - subtract value from variable and test result
153 * @i: integer value to subtract
154 * @v: pointer of type atomic_t
155 *
156 * Atomically subtracts @i from @v and returns
157 * true if the result is zero, or false for all
158 * other cases.
159 */
160#define atomic_sub_and_test(i,v) (atomic_sub_return((i),(v)) == 0)
161
162/**
163 * atomic_inc - increment atomic variable
164 * @v: pointer of type atomic_t
165 *
166 * Atomically increments @v by 1.
167 */
168#define atomic_inc(v) atomic_add(1,(v))
169
170/**
171 * atomic_inc - increment atomic variable
172 * @v: pointer of type atomic_t
173 *
174 * Atomically increments @v by 1.
175 */
176#define atomic_inc_return(v) atomic_add_return(1,(v))
177
178/**
179 * atomic_dec - decrement atomic variable
180 * @v: pointer of type atomic_t
181 *
182 * Atomically decrements @v by 1.
183 */
184#define atomic_dec(v) atomic_sub(1,(v))
185
186/**
187 * atomic_dec_return - decrement atomic variable
188 * @v: pointer of type atomic_t
189 *
190 * Atomically decrements @v by 1.
191 */
192#define atomic_dec_return(v) atomic_sub_return(1,(v))
193
194/**
195 * atomic_dec_and_test - decrement and test
196 * @v: pointer of type atomic_t
197 *
198 * Atomically decrements @v by 1 and
199 * returns true if the result is 0, or false for all other
200 * cases.
201 */
202#define atomic_dec_and_test(v) (atomic_sub_return(1,(v)) == 0)
203
204/**
205 * atomic_inc_and_test - increment and test
206 * @v: pointer of type atomic_t
207 *
208 * Atomically increments @v by 1
209 * and returns true if the result is zero, or false for all
210 * other cases.
211 */
212#define atomic_inc_and_test(v) (atomic_add_return(1,(v)) == 0)
213
214/**
215 * atomic_add_negative - add and test if negative
216 * @v: pointer of type atomic_t
217 * @i: integer value to add
218 *
219 * Atomically adds @i to @v and returns true
220 * if the result is negative, or false when
221 * result is greater than or equal to zero.
222 */
223#define atomic_add_negative(i,v) (atomic_add_return((i),(v)) < 0)
224
225#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
226#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
227
228/**
229 * atomic_add_unless - add unless the number is a given value
230 * @v: pointer of type atomic_t
231 * @a: the amount to add to v...
232 * @u: ...unless v is equal to u.
233 *
234 * Atomically adds @a to @v, so long as it was not @u.
235 * Returns non-zero if @v was not @u, and zero otherwise.
236 */
237static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
238{
239 int c, old;
240 c = atomic_read(v);
241 for (;;) {
242 if (unlikely(c == (u)))
243 break;
244 old = atomic_cmpxchg((v), c, c + (a));
245 if (likely(old == c))
246 break;
247 c = old;
248 }
249 return c != (u);
250}
251
252#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
253
254static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
255{
256 unsigned int all_f = -1;
257 unsigned int vval;
258
259 __asm__ __volatile__(
260 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
261 "l32i %0, %2, 0 \n\t"
262 "xor %1, %4, %3 \n\t"
263 "and %0, %0, %4 \n\t"
264 "s32i %0, %2, 0 \n\t"
265 "wsr a15, "__stringify(PS)" \n\t"
266 "rsync \n"
267 : "=&a" (vval), "=a" (mask)
268 : "a" (v), "a" (all_f), "1" (mask)
269 : "a15", "memory"
270 );
271}
272
273static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
274{
275 unsigned int vval;
276
277 __asm__ __volatile__(
278 "rsil a15,"__stringify(LOCKLEVEL)"\n\t"
279 "l32i %0, %2, 0 \n\t"
280 "or %0, %0, %1 \n\t"
281 "s32i %0, %2, 0 \n\t"
282 "wsr a15, "__stringify(PS)" \n\t"
283 "rsync \n"
284 : "=&a" (vval)
285 : "a" (mask), "a" (v)
286 : "a15", "memory"
287 );
288}
289
290/* Atomic operations are already serializing */
291#define smp_mb__before_atomic_dec() barrier()
292#define smp_mb__after_atomic_dec() barrier()
293#define smp_mb__before_atomic_inc() barrier()
294#define smp_mb__after_atomic_inc() barrier()
295
296#include <asm-generic/atomic.h>
297#endif /* __KERNEL__ */
298
299#endif /* _XTENSA_ATOMIC_H */
300
diff --git a/include/asm-xtensa/auxvec.h b/include/asm-xtensa/auxvec.h
deleted file mode 100644
index 257dec75c5af..000000000000
--- a/include/asm-xtensa/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __XTENSA_AUXVEC_H
2#define __XTENSA_AUXVEC_H
3
4#endif
diff --git a/include/asm-xtensa/bitops.h b/include/asm-xtensa/bitops.h
deleted file mode 100644
index 23261e8f2e5a..000000000000
--- a/include/asm-xtensa/bitops.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * include/asm-xtensa/bitops.h
3 *
4 * Atomic operations that C can't guarantee us.Useful for resource counting etc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2007 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_BITOPS_H
14#define _XTENSA_BITOPS_H
15
16#ifdef __KERNEL__
17
18#ifndef _LINUX_BITOPS_H
19#error only <linux/bitops.h> can be included directly
20#endif
21
22#include <asm/processor.h>
23#include <asm/byteorder.h>
24#include <asm/system.h>
25
26#ifdef CONFIG_SMP
27# error SMP not supported on this architecture
28#endif
29
30#define smp_mb__before_clear_bit() barrier()
31#define smp_mb__after_clear_bit() barrier()
32
33#include <asm-generic/bitops/atomic.h>
34#include <asm-generic/bitops/non-atomic.h>
35
36#if XCHAL_HAVE_NSA
37
38static inline unsigned long __cntlz (unsigned long x)
39{
40 int lz;
41 asm ("nsau %0, %1" : "=r" (lz) : "r" (x));
42 return lz;
43}
44
45/*
46 * ffz: Find first zero in word. Undefined if no zero exists.
47 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
48 */
49
50static inline int ffz(unsigned long x)
51{
52 return 31 - __cntlz(~x & -~x);
53}
54
55/*
56 * __ffs: Find first bit set in word. Return 0 for bit 0
57 */
58
59static inline int __ffs(unsigned long x)
60{
61 return 31 - __cntlz(x & -x);
62}
63
64/*
65 * ffs: Find first bit set in word. This is defined the same way as
66 * the libc and compiler builtin ffs routines, therefore
67 * differs in spirit from the above ffz (man ffs).
68 */
69
70static inline int ffs(unsigned long x)
71{
72 return 32 - __cntlz(x & -x);
73}
74
75/*
76 * fls: Find last (most-significant) bit set in word.
77 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
78 */
79
80static inline int fls (unsigned int x)
81{
82 return 32 - __cntlz(x);
83}
84
85#else
86
87/* Use the generic implementation if we don't have the nsa/nsau instructions. */
88
89# include <asm-generic/bitops/ffs.h>
90# include <asm-generic/bitops/__ffs.h>
91# include <asm-generic/bitops/ffz.h>
92# include <asm-generic/bitops/fls.h>
93
94#endif
95
96#include <asm-generic/bitops/fls64.h>
97#include <asm-generic/bitops/find.h>
98#include <asm-generic/bitops/ext2-non-atomic.h>
99
100#ifdef __XTENSA_EL__
101# define ext2_set_bit_atomic(lock,nr,addr) \
102 test_and_set_bit((nr), (unsigned long*)(addr))
103# define ext2_clear_bit_atomic(lock,nr,addr) \
104 test_and_clear_bit((nr), (unsigned long*)(addr))
105#elif defined(__XTENSA_EB__)
106# define ext2_set_bit_atomic(lock,nr,addr) \
107 test_and_set_bit((nr) ^ 0x18, (unsigned long*)(addr))
108# define ext2_clear_bit_atomic(lock,nr,addr) \
109 test_and_clear_bit((nr) ^ 0x18, (unsigned long*)(addr))
110#else
111# error processor byte order undefined!
112#endif
113
114#include <asm-generic/bitops/hweight.h>
115#include <asm-generic/bitops/lock.h>
116#include <asm-generic/bitops/sched.h>
117#include <asm-generic/bitops/minix.h>
118
119#endif /* __KERNEL__ */
120
121#endif /* _XTENSA_BITOPS_H */
diff --git a/include/asm-xtensa/bootparam.h b/include/asm-xtensa/bootparam.h
deleted file mode 100644
index 9983f2c1b7ee..000000000000
--- a/include/asm-xtensa/bootparam.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * include/asm-xtensa/bootparam.h
3 *
4 * Definition of the Linux/Xtensa boot parameter structure
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 *
12 * (Concept borrowed from the 68K port)
13 */
14
15#ifndef _XTENSA_BOOTPARAM_H
16#define _XTENSA_BOOTPARAM_H
17
18#define BP_VERSION 0x0001
19
20#define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/
21#define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */
22#define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */
23#define BP_TAG_SERIAL_BAUSRATE 0x1004 /* baud rate of current console. */
24#define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */
25
26#define BP_TAG_FIRST 0x7B0B /* first tag with a version number */
27#define BP_TAG_LAST 0x7E0B /* last tag */
28
29#ifndef __ASSEMBLY__
30
31/* All records are aligned to 4 bytes */
32
33typedef struct bp_tag {
34 unsigned short id; /* tag id */
35 unsigned short size; /* size of this record excluding the structure*/
36 unsigned long data[0]; /* data */
37} bp_tag_t;
38
39typedef struct meminfo {
40 unsigned long type;
41 unsigned long start;
42 unsigned long end;
43} meminfo_t;
44
45#define SYSMEM_BANKS_MAX 5
46
47#define MEMORY_TYPE_CONVENTIONAL 0x1000
48#define MEMORY_TYPE_NONE 0x2000
49
50typedef struct sysmem_info {
51 int nr_banks;
52 meminfo_t bank[SYSMEM_BANKS_MAX];
53} sysmem_info_t;
54
55extern sysmem_info_t sysmem;
56
57#endif
58#endif
59
60
61
diff --git a/include/asm-xtensa/bug.h b/include/asm-xtensa/bug.h
deleted file mode 100644
index 3e52d72712f1..000000000000
--- a/include/asm-xtensa/bug.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-xtensa/bug.h
3 *
4 * Macros to cause a 'bug' message.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_BUG_H
14#define _XTENSA_BUG_H
15
16#include <asm-generic/bug.h>
17
18#endif /* _XTENSA_BUG_H */
diff --git a/include/asm-xtensa/bugs.h b/include/asm-xtensa/bugs.h
deleted file mode 100644
index 69b29d198249..000000000000
--- a/include/asm-xtensa/bugs.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-xtensa/bugs.h
3 *
4 * This is included by init/main.c to check for architecture-dependent bugs.
5 *
6 * Xtensa processors don't have any bugs. :)
7 *
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of
10 * this archive for more details.
11 */
12
13#ifndef _XTENSA_BUGS_H
14#define _XTENSA_BUGS_H
15
16static void check_bugs(void) { }
17
18#endif /* _XTENSA_BUGS_H */
diff --git a/include/asm-xtensa/byteorder.h b/include/asm-xtensa/byteorder.h
deleted file mode 100644
index 07d10ad364d1..000000000000
--- a/include/asm-xtensa/byteorder.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * include/asm-xtensa/byteorder.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_BYTEORDER_H
12#define _XTENSA_BYTEORDER_H
13
14#include <asm/types.h>
15#include <linux/compiler.h>
16
17#ifdef __XTENSA_EL__
18# define __LITTLE_ENDIAN
19#elif defined(__XTENSA_EB__)
20# define __BIG_ENDIAN
21#else
22# error processor byte order undefined!
23#endif
24
25#define __SWAB_64_THRU_32__
26
27static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
28{
29 __u32 res;
30 /* instruction sequence from Xtensa ISA release 2/2000 */
31 __asm__("ssai 8 \n\t"
32 "srli %0, %1, 16 \n\t"
33 "src %0, %0, %1 \n\t"
34 "src %0, %0, %0 \n\t"
35 "src %0, %1, %0 \n"
36 : "=&a" (res)
37 : "a" (x)
38 );
39 return res;
40}
41#define __arch_swab32 __arch_swab32
42
43static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
44{
45 /* Given that 'short' values are signed (i.e., can be negative),
46 * we cannot assume that the upper 16-bits of the register are
47 * zero. We are careful to mask values after shifting.
48 */
49
50 /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
51 * inserts an extui instruction after putting this function inline
52 * to ensure that it uses only the least-significant 16 bits of
53 * the result. xt-xcc doesn't use an extui, but assumes the
54 * __asm__ macro follows convention that the upper 16 bits of an
55 * 'unsigned short' result are still zero. This macro doesn't
56 * follow convention; indeed, it leaves garbage in the upport 16
57 * bits of the register.
58
59 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
60 * types while the return type of the function is a 16-bit type
61 * forces both compilers to insert exactly one extui instruction
62 * (or equivalent) to mask off the upper 16 bits. */
63
64 __u32 res;
65 __u32 tmp;
66
67 __asm__("extui %1, %2, 8, 8\n\t"
68 "slli %0, %2, 8 \n\t"
69 "or %0, %0, %1 \n"
70 : "=&a" (res), "=&a" (tmp)
71 : "a" (x)
72 );
73
74 return res;
75}
76#define __arch_swab16 __arch_swab16
77
78#include <linux/byteorder.h>
79
80#endif /* _XTENSA_BYTEORDER_H */
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h
deleted file mode 100644
index 3bba2a540cf0..000000000000
--- a/include/asm-xtensa/cache.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * include/asm-xtensa/cache.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CACHE_H
12#define _XTENSA_CACHE_H
13
14#include <asm/variant/core.h>
15
16#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
17#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
18#define SMP_CACHE_BYTES L1_CACHE_BYTES
19
20#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
21#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
22#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
23#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
24
25/* Maximum cache size per way. */
26#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
27# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
28#else
29# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
30#endif
31
32
33#endif /* _XTENSA_CACHE_H */
diff --git a/include/asm-xtensa/cacheasm.h b/include/asm-xtensa/cacheasm.h
deleted file mode 100644
index 2c20a58f94cd..000000000000
--- a/include/asm-xtensa/cacheasm.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * include/asm-xtensa/cacheasm.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2006 Tensilica Inc.
9 */
10
11#include <asm/cache.h>
12#include <asm/asmmacro.h>
13#include <linux/stringify.h>
14
15/*
16 * Define cache functions as macros here so that they can be used
17 * by the kernel and boot loader. We should consider moving them to a
18 * library that can be linked by both.
19 *
20 * Locking
21 *
22 * ___unlock_dcache_all
23 * ___unlock_icache_all
24 *
25 * Flush and invaldating
26 *
27 * ___flush_invalidate_dcache_{all|range|page}
28 * ___flush_dcache_{all|range|page}
29 * ___invalidate_dcache_{all|range|page}
30 * ___invalidate_icache_{all|range|page}
31 *
32 */
33
34 .macro __loop_cache_all ar at insn size line_width
35
36 movi \ar, 0
37
38 __loopi \ar, \at, \size, (4 << (\line_width))
39 \insn \ar, 0 << (\line_width)
40 \insn \ar, 1 << (\line_width)
41 \insn \ar, 2 << (\line_width)
42 \insn \ar, 3 << (\line_width)
43 __endla \ar, \at, 4 << (\line_width)
44
45 .endm
46
47
48 .macro __loop_cache_range ar as at insn line_width
49
50 extui \at, \ar, 0, \line_width
51 add \as, \as, \at
52
53 __loops \ar, \as, \at, \line_width
54 \insn \ar, 0
55 __endla \ar, \at, (1 << (\line_width))
56
57 .endm
58
59
60 .macro __loop_cache_page ar at insn line_width
61
62 __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
63 \insn \ar, 0 << (\line_width)
64 \insn \ar, 1 << (\line_width)
65 \insn \ar, 2 << (\line_width)
66 \insn \ar, 3 << (\line_width)
67 __endla \ar, \at, 4 << (\line_width)
68
69 .endm
70
71
72#if XCHAL_DCACHE_LINE_LOCKABLE
73
74 .macro ___unlock_dcache_all ar at
75
76 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
77
78 .endm
79
80#endif
81
82#if XCHAL_ICACHE_LINE_LOCKABLE
83
84 .macro ___unlock_icache_all ar at
85
86 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
87
88 .endm
89#endif
90
91 .macro ___flush_invalidate_dcache_all ar at
92
93 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
94
95 .endm
96
97
98 .macro ___flush_dcache_all ar at
99
100 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH
101
102 .endm
103
104
105 .macro ___invalidate_dcache_all ar at
106
107 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \
108 XCHAL_DCACHE_LINEWIDTH
109
110 .endm
111
112
113 .macro ___invalidate_icache_all ar at
114
115 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \
116 XCHAL_ICACHE_LINEWIDTH
117
118 .endm
119
120
121
122 .macro ___flush_invalidate_dcache_range ar as at
123
124 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
125
126 .endm
127
128
129 .macro ___flush_dcache_range ar as at
130
131 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
132
133 .endm
134
135
136 .macro ___invalidate_dcache_range ar as at
137
138 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
139
140 .endm
141
142
143 .macro ___invalidate_icache_range ar as at
144
145 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
146
147 .endm
148
149
150
151 .macro ___flush_invalidate_dcache_page ar as
152
153 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH
154
155 .endm
156
157
158 .macro ___flush_dcache_page ar as
159
160 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH
161
162 .endm
163
164
165 .macro ___invalidate_dcache_page ar as
166
167 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH
168
169 .endm
170
171
172 .macro ___invalidate_icache_page ar as
173
174 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
175
176 .endm
177
diff --git a/include/asm-xtensa/cacheflush.h b/include/asm-xtensa/cacheflush.h
deleted file mode 100644
index 94c4c53a099e..000000000000
--- a/include/asm-xtensa/cacheflush.h
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * include/asm-xtensa/cacheflush.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CACHEFLUSH_H
12#define _XTENSA_CACHEFLUSH_H
13
14#ifdef __KERNEL__
15
16#include <linux/mm.h>
17#include <asm/processor.h>
18#include <asm/page.h>
19
20/*
21 * Lo-level routines for cache flushing.
22 *
23 * invalidate data or instruction cache:
24 *
25 * __invalidate_icache_all()
26 * __invalidate_icache_page(adr)
27 * __invalidate_dcache_page(adr)
28 * __invalidate_icache_range(from,size)
29 * __invalidate_dcache_range(from,size)
30 *
31 * flush data cache:
32 *
33 * __flush_dcache_page(adr)
34 *
35 * flush and invalidate data cache:
36 *
37 * __flush_invalidate_dcache_all()
38 * __flush_invalidate_dcache_page(adr)
39 * __flush_invalidate_dcache_range(from,size)
40 *
41 * specials for cache aliasing:
42 *
43 * __flush_invalidate_dcache_page_alias(vaddr,paddr)
44 * __invalidate_icache_page_alias(vaddr,paddr)
45 */
46
47extern void __invalidate_dcache_all(void);
48extern void __invalidate_icache_all(void);
49extern void __invalidate_dcache_page(unsigned long);
50extern void __invalidate_icache_page(unsigned long);
51extern void __invalidate_icache_range(unsigned long, unsigned long);
52extern void __invalidate_dcache_range(unsigned long, unsigned long);
53
54
55#if XCHAL_DCACHE_IS_WRITEBACK
56extern void __flush_invalidate_dcache_all(void);
57extern void __flush_dcache_page(unsigned long);
58extern void __flush_dcache_range(unsigned long, unsigned long);
59extern void __flush_invalidate_dcache_page(unsigned long);
60extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
61#else
62# define __flush_dcache_range(p,s) do { } while(0)
63# define __flush_dcache_page(p) do { } while(0)
64# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
65# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
66#endif
67
68#if (DCACHE_WAY_SIZE > PAGE_SIZE)
69extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
70#endif
71#if (ICACHE_WAY_SIZE > PAGE_SIZE)
72extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
73#else
74# define __invalidate_icache_page_alias(v,p) do { } while(0)
75#endif
76
77/*
78 * We have physically tagged caches - nothing to do here -
79 * unless we have cache aliasing.
80 *
81 * Pages can get remapped. Because this might change the 'color' of that page,
82 * we have to flush the cache before the PTE is changed.
83 * (see also Documentation/cachetlb.txt)
84 */
85
86#if (DCACHE_WAY_SIZE > PAGE_SIZE)
87
88#define flush_cache_all() \
89 do { \
90 __flush_invalidate_dcache_all(); \
91 __invalidate_icache_all(); \
92 } while (0)
93
94#define flush_cache_mm(mm) flush_cache_all()
95#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
96
97#define flush_cache_vmap(start,end) flush_cache_all()
98#define flush_cache_vunmap(start,end) flush_cache_all()
99
100extern void flush_dcache_page(struct page*);
101extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
102extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
103
104#else
105
106#define flush_cache_all() do { } while (0)
107#define flush_cache_mm(mm) do { } while (0)
108#define flush_cache_dup_mm(mm) do { } while (0)
109
110#define flush_cache_vmap(start,end) do { } while (0)
111#define flush_cache_vunmap(start,end) do { } while (0)
112
113#define flush_dcache_page(page) do { } while (0)
114
115#define flush_cache_page(vma,addr,pfn) do { } while (0)
116#define flush_cache_range(vma,start,end) do { } while (0)
117
118#endif
119
120/* Ensure consistency between data and instruction cache. */
121#define flush_icache_range(start,end) \
122 do { \
123 __flush_dcache_range(start, (end) - (start)); \
124 __invalidate_icache_range(start,(end) - (start)); \
125 } while (0)
126
127/* This is not required, see Documentation/cachetlb.txt */
128#define flush_icache_page(vma,page) do { } while (0)
129
130#define flush_dcache_mmap_lock(mapping) do { } while (0)
131#define flush_dcache_mmap_unlock(mapping) do { } while (0)
132
133#if (DCACHE_WAY_SIZE > PAGE_SIZE)
134
135extern void copy_to_user_page(struct vm_area_struct*, struct page*,
136 unsigned long, void*, const void*, unsigned long);
137extern void copy_from_user_page(struct vm_area_struct*, struct page*,
138 unsigned long, void*, const void*, unsigned long);
139
140#else
141
142#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
143 do { \
144 memcpy(dst, src, len); \
145 __flush_dcache_range((unsigned long) dst, len); \
146 __invalidate_icache_range((unsigned long) dst, len); \
147 } while (0)
148
149#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
150 memcpy(dst, src, len)
151
152#endif
153
154#endif /* __KERNEL__ */
155#endif /* _XTENSA_CACHEFLUSH_H */
diff --git a/include/asm-xtensa/checksum.h b/include/asm-xtensa/checksum.h
deleted file mode 100644
index 23534c60b3a4..000000000000
--- a/include/asm-xtensa/checksum.h
+++ /dev/null
@@ -1,250 +0,0 @@
1/*
2 * include/asm-xtensa/checksum.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CHECKSUM_H
12#define _XTENSA_CHECKSUM_H
13
14#include <linux/in6.h>
15#include <asm/variant/core.h>
16
17/*
18 * computes the checksum of a memory block at buff, length len,
19 * and adds in "sum" (32-bit)
20 *
21 * returns a 32-bit number suitable for feeding into itself
22 * or csum_tcpudp_magic
23 *
24 * this function must be called with even lengths, except
25 * for the last fragment, which may be odd
26 *
27 * it's best to have buff aligned on a 32-bit boundary
28 */
29asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
30
31/*
32 * the same as csum_partial, but copies from src while it
33 * checksums, and handles user-space pointer exceptions correctly, when needed.
34 *
35 * here even more important to align src and dst on a 32-bit (or even
36 * better 64-bit) boundary
37 */
38
39asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst, int len, __wsum sum,
40 int *src_err_ptr, int *dst_err_ptr);
41
42/*
43 * Note: when you get a NULL pointer exception here this means someone
44 * passed in an incorrect kernel address to one of these functions.
45 *
46 * If you use these functions directly please don't forget the access_ok().
47 */
48static inline
49__wsum csum_partial_copy_nocheck(const void *src, void *dst,
50 int len, __wsum sum)
51{
52 return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
53}
54
55static inline
56__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
57 int len, __wsum sum, int *err_ptr)
58{
59 return csum_partial_copy_generic((__force const void *)src, dst,
60 len, sum, err_ptr, NULL);
61}
62
63/*
64 * Fold a partial checksum
65 */
66
67static __inline__ __sum16 csum_fold(__wsum sum)
68{
69 unsigned int __dummy;
70 __asm__("extui %1, %0, 16, 16\n\t"
71 "extui %0 ,%0, 0, 16\n\t"
72 "add %0, %0, %1\n\t"
73 "slli %1, %0, 16\n\t"
74 "add %0, %0, %1\n\t"
75 "extui %0, %0, 16, 16\n\t"
76 "neg %0, %0\n\t"
77 "addi %0, %0, -1\n\t"
78 "extui %0, %0, 0, 16\n\t"
79 : "=r" (sum), "=&r" (__dummy)
80 : "0" (sum));
81 return (__force __sum16)sum;
82}
83
84/*
85 * This is a version of ip_compute_csum() optimized for IP headers,
86 * which always checksum on 4 octet boundaries.
87 */
88static __inline__ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
89{
90 unsigned int sum, tmp, endaddr;
91
92 __asm__ __volatile__(
93 "sub %0, %0, %0\n\t"
94#if XCHAL_HAVE_LOOPS
95 "loopgtz %2, 2f\n\t"
96#else
97 "beqz %2, 2f\n\t"
98 "slli %4, %2, 2\n\t"
99 "add %4, %4, %1\n\t"
100 "0:\t"
101#endif
102 "l32i %3, %1, 0\n\t"
103 "add %0, %0, %3\n\t"
104 "bgeu %0, %3, 1f\n\t"
105 "addi %0, %0, 1\n\t"
106 "1:\t"
107 "addi %1, %1, 4\n\t"
108#if !XCHAL_HAVE_LOOPS
109 "blt %1, %4, 0b\n\t"
110#endif
111 "2:\t"
112 /* Since the input registers which are loaded with iph and ihl
113 are modified, we must also specify them as outputs, or gcc
114 will assume they contain their original values. */
115 : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (tmp), "=&r" (endaddr)
116 : "1" (iph), "2" (ihl));
117
118 return csum_fold(sum);
119}
120
121static __inline__ __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
122 unsigned short len,
123 unsigned short proto,
124 __wsum sum)
125{
126
127#ifdef __XTENSA_EL__
128 unsigned long len_proto = (len + proto) << 8;
129#elif defined(__XTENSA_EB__)
130 unsigned long len_proto = len + proto;
131#else
132# error processor byte order undefined!
133#endif
134 __asm__("add %0, %0, %1\n\t"
135 "bgeu %0, %1, 1f\n\t"
136 "addi %0, %0, 1\n\t"
137 "1:\t"
138 "add %0, %0, %2\n\t"
139 "bgeu %0, %2, 1f\n\t"
140 "addi %0, %0, 1\n\t"
141 "1:\t"
142 "add %0, %0, %3\n\t"
143 "bgeu %0, %3, 1f\n\t"
144 "addi %0, %0, 1\n\t"
145 "1:\t"
146 : "=r" (sum), "=r" (len_proto)
147 : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum));
148 return sum;
149}
150
151/*
152 * computes the checksum of the TCP/UDP pseudo-header
153 * returns a 16-bit checksum, already complemented
154 */
155static __inline__ __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
156 unsigned short len,
157 unsigned short proto,
158 __wsum sum)
159{
160 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
161}
162
163/*
164 * this routine is used for miscellaneous IP-like checksums, mainly
165 * in icmp.c
166 */
167
168static __inline__ __sum16 ip_compute_csum(const void *buff, int len)
169{
170 return csum_fold (csum_partial(buff, len, 0));
171}
172
173#define _HAVE_ARCH_IPV6_CSUM
174static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
175 const struct in6_addr *daddr,
176 __u32 len, unsigned short proto,
177 __wsum sum)
178{
179 unsigned int __dummy;
180 __asm__("l32i %1, %2, 0\n\t"
181 "add %0, %0, %1\n\t"
182 "bgeu %0, %1, 1f\n\t"
183 "addi %0, %0, 1\n\t"
184 "1:\t"
185 "l32i %1, %2, 4\n\t"
186 "add %0, %0, %1\n\t"
187 "bgeu %0, %1, 1f\n\t"
188 "addi %0, %0, 1\n\t"
189 "1:\t"
190 "l32i %1, %2, 8\n\t"
191 "add %0, %0, %1\n\t"
192 "bgeu %0, %1, 1f\n\t"
193 "addi %0, %0, 1\n\t"
194 "1:\t"
195 "l32i %1, %2, 12\n\t"
196 "add %0, %0, %1\n\t"
197 "bgeu %0, %1, 1f\n\t"
198 "addi %0, %0, 1\n\t"
199 "1:\t"
200 "l32i %1, %3, 0\n\t"
201 "add %0, %0, %1\n\t"
202 "bgeu %0, %1, 1f\n\t"
203 "addi %0, %0, 1\n\t"
204 "1:\t"
205 "l32i %1, %3, 4\n\t"
206 "add %0, %0, %1\n\t"
207 "bgeu %0, %1, 1f\n\t"
208 "addi %0, %0, 1\n\t"
209 "1:\t"
210 "l32i %1, %3, 8\n\t"
211 "add %0, %0, %1\n\t"
212 "bgeu %0, %1, 1f\n\t"
213 "addi %0, %0, 1\n\t"
214 "1:\t"
215 "l32i %1, %3, 12\n\t"
216 "add %0, %0, %1\n\t"
217 "bgeu %0, %1, 1f\n\t"
218 "addi %0, %0, 1\n\t"
219 "1:\t"
220 "add %0, %0, %4\n\t"
221 "bgeu %0, %4, 1f\n\t"
222 "addi %0, %0, 1\n\t"
223 "1:\t"
224 "add %0, %0, %5\n\t"
225 "bgeu %0, %5, 1f\n\t"
226 "addi %0, %0, 1\n\t"
227 "1:\t"
228 : "=r" (sum), "=&r" (__dummy)
229 : "r" (saddr), "r" (daddr),
230 "r" (htonl(len)), "r" (htonl(proto)), "0" (sum));
231
232 return csum_fold(sum);
233}
234
235/*
236 * Copy and checksum to user
237 */
238#define HAVE_CSUM_COPY_USER
239static __inline__ __wsum csum_and_copy_to_user(const void *src, void __user *dst,
240 int len, __wsum sum, int *err_ptr)
241{
242 if (access_ok(VERIFY_WRITE, dst, len))
243 return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr);
244
245 if (len)
246 *err_ptr = -EFAULT;
247
248 return (__force __wsum)-1; /* invalid checksum */
249}
250#endif
diff --git a/include/asm-xtensa/coprocessor.h b/include/asm-xtensa/coprocessor.h
deleted file mode 100644
index 1cbcf9001a41..000000000000
--- a/include/asm-xtensa/coprocessor.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * include/asm-xtensa/coprocessor.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2003 - 2007 Tensilica Inc.
9 */
10
11
12#ifndef _XTENSA_COPROCESSOR_H
13#define _XTENSA_COPROCESSOR_H
14
15#include <linux/stringify.h>
16#include <asm/variant/tie.h>
17#include <asm/types.h>
18
19#ifdef __ASSEMBLY__
20# include <asm/variant/tie-asm.h>
21
22.macro xchal_sa_start a b
23 .set .Lxchal_pofs_, 0
24 .set .Lxchal_ofs_, 0
25.endm
26
27.macro xchal_sa_align ptr minofs maxofs ofsalign totalign
28 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
29 .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
30.endm
31
32#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
33 | XTHAL_SAS_CC \
34 | XTHAL_SAS_CALR | XTHAL_SAS_CALE )
35
36.macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
37 .if XTREGS_OPT_SIZE > 0
38 addi \clb, \ptr, \offset
39 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
40 .endif
41.endm
42
43.macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
44 .if XTREGS_OPT_SIZE > 0
45 addi \clb, \ptr, \offset
46 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
47 .endif
48.endm
49#undef _SELECT
50
51#define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \
52 | XTHAL_SAS_NOCC \
53 | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
54
55.macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
56 .if XTREGS_USER_SIZE > 0
57 addi \clb, \ptr, \offset
58 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
59 .endif
60.endm
61
62.macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
63 .if XTREGS_USER_SIZE > 0
64 addi \clb, \ptr, \offset
65 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
66 .endif
67.endm
68#undef _SELECT
69
70
71
72#endif /* __ASSEMBLY__ */
73
74/*
75 * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
76 *
77 * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
78 *
79 */
80
81#define XTENSA_HAVE_COPROCESSOR(x) \
82 ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
83#define XTENSA_HAVE_COPROCESSORS \
84 (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
85#define XTENSA_HAVE_IO_PORT(x) \
86 (XCHAL_CP_PORT_MASK & (1 << (x)))
87#define XTENSA_HAVE_IO_PORTS \
88 XCHAL_CP_PORT_MASK
89
90#ifndef __ASSEMBLY__
91
92
93#if XCHAL_HAVE_CP
94
95#define RSR_CPENABLE(x) do { \
96 __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
97 } while(0);
98#define WSR_CPENABLE(x) do { \
99 __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \
100 :: "a" (x)); \
101 } while(0);
102
103#endif /* XCHAL_HAVE_CP */
104
105
106/*
107 * Additional registers.
108 * We define three types of additional registers:
109 * ext: extra registers that are used by the compiler
110 * cpn: optional registers that can be used by a user application
111 * cpX: coprocessor registers that can only be used if the corresponding
112 * CPENABLE bit is set.
113 */
114
115#define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \
116 __REG ## list (cc, abi, type, name, size, align)
117
118#define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name)
119#define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name)
120#define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__)
121
122#define __REG0_0(abi,name)
123#define __REG0_1(abi,name) __REG0_1 ## abi (name)
124#define __REG0_10(name) __u32 name;
125#define __REG0_11(name) __u32 name;
126#define __REG0_12(name)
127
128#define __REG1_0(name) __u32 name;
129#define __REG1_1(name)
130
131#define __REG2_0(n,s,a) __u32 name;
132#define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
133#define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
134
135typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
136 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
137typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
138 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
139
140#if XTENSA_HAVE_COPROCESSORS
141
142typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
143 __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
144typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
145 __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
146typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
147 __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
148typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
149 __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
150typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
151 __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
152typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
153 __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
154typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
155 __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
156typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
157 __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
158
159extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
160extern void coprocessor_save(void*, int);
161extern void coprocessor_load(void*, int);
162extern void coprocessor_flush(struct thread_info*, int);
163extern void coprocessor_restore(struct thread_info*, int);
164
165extern void coprocessor_release_all(struct thread_info*);
166extern void coprocessor_flush_all(struct thread_info*);
167
168static inline void coprocessor_clear_cpenable(void)
169{
170 unsigned long i = 0;
171 WSR_CPENABLE(i);
172}
173
174#endif /* XTENSA_HAVE_COPROCESSORS */
175
176#endif /* !__ASSEMBLY__ */
177#endif /* _XTENSA_COPROCESSOR_H */
diff --git a/include/asm-xtensa/cpumask.h b/include/asm-xtensa/cpumask.h
deleted file mode 100644
index ebeede397db3..000000000000
--- a/include/asm-xtensa/cpumask.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/cpumask.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CPUMASK_H
12#define _XTENSA_CPUMASK_H
13
14#include <asm-generic/cpumask.h>
15
16#endif /* _XTENSA_CPUMASK_H */
diff --git a/include/asm-xtensa/cputime.h b/include/asm-xtensa/cputime.h
deleted file mode 100644
index a7fb864a50ae..000000000000
--- a/include/asm-xtensa/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _XTENSA_CPUTIME_H
2#define _XTENSA_CPUTIME_H
3
4#include <asm-generic/cputime.h>
5
6#endif /* _XTENSA_CPUTIME_H */
diff --git a/include/asm-xtensa/current.h b/include/asm-xtensa/current.h
deleted file mode 100644
index 8d1eb5d78649..000000000000
--- a/include/asm-xtensa/current.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * include/asm-xtensa/current.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CURRENT_H
12#define _XTENSA_CURRENT_H
13
14#ifndef __ASSEMBLY__
15
16#include <linux/thread_info.h>
17
18struct task_struct;
19
20static inline struct task_struct *get_current(void)
21{
22 return current_thread_info()->task;
23}
24
25#define current get_current()
26
27#else
28
29#define CURRENT_SHIFT 13
30
31#define GET_CURRENT(reg,sp) \
32 GET_THREAD_INFO(reg,sp); \
33 l32i reg, reg, TI_TASK \
34
35#endif
36
37
38#endif /* XTENSA_CURRENT_H */
diff --git a/include/asm-xtensa/delay.h b/include/asm-xtensa/delay.h
deleted file mode 100644
index e1d8c9e010c1..000000000000
--- a/include/asm-xtensa/delay.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * include/asm-xtensa/delay.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 *
10 */
11
12#ifndef _XTENSA_DELAY_H
13#define _XTENSA_DELAY_H
14
15#include <asm/processor.h>
16#include <asm/param.h>
17
18extern unsigned long loops_per_jiffy;
19
20static inline void __delay(unsigned long loops)
21{
22 /* 2 cycles per loop. */
23 __asm__ __volatile__ ("1: addi %0, %0, -2; bgeui %0, 2, 1b"
24 : "=r" (loops) : "0" (loops));
25}
26
27static __inline__ u32 xtensa_get_ccount(void)
28{
29 u32 ccount;
30 asm volatile ("rsr %0, 234; # CCOUNT\n" : "=r" (ccount));
31 return ccount;
32}
33
34/* For SMP/NUMA systems, change boot_cpu_data to something like
35 * local_cpu_data->... where local_cpu_data points to the current
36 * cpu. */
37
38static __inline__ void udelay (unsigned long usecs)
39{
40 unsigned long start = xtensa_get_ccount();
41 unsigned long cycles = usecs * (loops_per_jiffy / (1000000UL / HZ));
42
43 /* Note: all variables are unsigned (can wrap around)! */
44 while (((unsigned long)xtensa_get_ccount()) - start < cycles)
45 ;
46}
47
48#endif
49
diff --git a/include/asm-xtensa/device.h b/include/asm-xtensa/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-xtensa/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#include <asm-generic/device.h>
7
diff --git a/include/asm-xtensa/div64.h b/include/asm-xtensa/div64.h
deleted file mode 100644
index f35678cb0a9b..000000000000
--- a/include/asm-xtensa/div64.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/div64.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_DIV64_H
12#define _XTENSA_DIV64_H
13
14#include <asm-generic/div64.h>
15
16#endif /* _XTENSA_DIV64_H */
diff --git a/include/asm-xtensa/dma-mapping.h b/include/asm-xtensa/dma-mapping.h
deleted file mode 100644
index 51882ae3db4d..000000000000
--- a/include/asm-xtensa/dma-mapping.h
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * include/asm-xtensa/dma-mapping.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_DMA_MAPPING_H
12#define _XTENSA_DMA_MAPPING_H
13
14#include <asm/cache.h>
15#include <asm/io.h>
16#include <linux/mm.h>
17#include <linux/scatterlist.h>
18
19/*
20 * DMA-consistent mapping functions.
21 */
22
23extern void *consistent_alloc(int, size_t, dma_addr_t, unsigned long);
24extern void consistent_free(void*, size_t, dma_addr_t);
25extern void consistent_sync(void*, size_t, int);
26
27#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
28#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
29
30void *dma_alloc_coherent(struct device *dev, size_t size,
31 dma_addr_t *dma_handle, gfp_t flag);
32
33void dma_free_coherent(struct device *dev, size_t size,
34 void *vaddr, dma_addr_t dma_handle);
35
36static inline dma_addr_t
37dma_map_single(struct device *dev, void *ptr, size_t size,
38 enum dma_data_direction direction)
39{
40 BUG_ON(direction == DMA_NONE);
41 consistent_sync(ptr, size, direction);
42 return virt_to_phys(ptr);
43}
44
45static inline void
46dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
47 enum dma_data_direction direction)
48{
49 BUG_ON(direction == DMA_NONE);
50}
51
52static inline int
53dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
54 enum dma_data_direction direction)
55{
56 int i;
57
58 BUG_ON(direction == DMA_NONE);
59
60 for (i = 0; i < nents; i++, sg++ ) {
61 BUG_ON(!sg_page(sg));
62
63 sg->dma_address = sg_phys(sg);
64 consistent_sync(sg_virt(sg), sg->length, direction);
65 }
66
67 return nents;
68}
69
70static inline dma_addr_t
71dma_map_page(struct device *dev, struct page *page, unsigned long offset,
72 size_t size, enum dma_data_direction direction)
73{
74 BUG_ON(direction == DMA_NONE);
75 return (dma_addr_t)(page_to_pfn(page)) * PAGE_SIZE + offset;
76}
77
78static inline void
79dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
80 enum dma_data_direction direction)
81{
82 BUG_ON(direction == DMA_NONE);
83}
84
85
86static inline void
87dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
88 enum dma_data_direction direction)
89{
90 BUG_ON(direction == DMA_NONE);
91}
92
93static inline void
94dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
95 enum dma_data_direction direction)
96{
97 consistent_sync((void *)bus_to_virt(dma_handle), size, direction);
98}
99
100static inline void
101dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
102 enum dma_data_direction direction)
103{
104 consistent_sync((void *)bus_to_virt(dma_handle), size, direction);
105}
106
107static inline void
108dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
109 unsigned long offset, size_t size,
110 enum dma_data_direction direction)
111{
112
113 consistent_sync((void *)bus_to_virt(dma_handle)+offset,size,direction);
114}
115
116static inline void
117dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
118 unsigned long offset, size_t size,
119 enum dma_data_direction direction)
120{
121
122 consistent_sync((void *)bus_to_virt(dma_handle)+offset,size,direction);
123}
124static inline void
125dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
126 enum dma_data_direction dir)
127{
128 int i;
129 for (i = 0; i < nelems; i++, sg++)
130 consistent_sync(sg_virt(sg), sg->length, dir);
131}
132
133static inline void
134dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
135 enum dma_data_direction dir)
136{
137 int i;
138 for (i = 0; i < nelems; i++, sg++)
139 consistent_sync(sg_virt(sg), sg->length, dir);
140}
141static inline int
142dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
143{
144 return 0;
145}
146
147static inline int
148dma_supported(struct device *dev, u64 mask)
149{
150 return 1;
151}
152
153static inline int
154dma_set_mask(struct device *dev, u64 mask)
155{
156 if(!dev->dma_mask || !dma_supported(dev, mask))
157 return -EIO;
158
159 *dev->dma_mask = mask;
160
161 return 0;
162}
163
164static inline int
165dma_get_cache_alignment(void)
166{
167 return L1_CACHE_BYTES;
168}
169
170#define dma_is_consistent(d, h) (1)
171
172static inline void
173dma_cache_sync(struct device *dev, void *vaddr, size_t size,
174 enum dma_data_direction direction)
175{
176 consistent_sync(vaddr, size, direction);
177}
178
179#endif /* _XTENSA_DMA_MAPPING_H */
diff --git a/include/asm-xtensa/dma.h b/include/asm-xtensa/dma.h
deleted file mode 100644
index e30f3abf48f0..000000000000
--- a/include/asm-xtensa/dma.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * include/asm-xtensa/dma.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_DMA_H
12#define _XTENSA_DMA_H
13
14#include <asm/io.h> /* need byte IO */
15
16/*
17 * This is only to be defined if we have PC-like DMA.
18 * By default this is not true on an Xtensa processor,
19 * however on boards with a PCI bus, such functionality
20 * might be emulated externally.
21 *
22 * NOTE: there still exists driver code that assumes
23 * this is defined, eg. drivers/sound/soundcard.c (as of 2.4).
24 */
25#define MAX_DMA_CHANNELS 8
26
27/*
28 * The maximum virtual address to which DMA transfers
29 * can be performed on this platform.
30 *
31 * NOTE: This is board (platform) specific, not processor-specific!
32 *
33 * NOTE: This assumes DMA transfers can only be performed on
34 * the section of physical memory contiguously mapped in virtual
35 * space for the kernel. For the Xtensa architecture, this
36 * means the maximum possible size of this DMA area is
37 * the size of the statically mapped kernel segment
38 * (XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB.
39 *
40 * NOTE: When the entire KSEG area is DMA capable, we substract
41 * one from the max address so that the virt_to_phys() macro
42 * works correctly on the address (otherwise the address
43 * enters another area, and virt_to_phys() may not return
44 * the value desired).
45 */
46
47#define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
48
49
50/* Reserve and release a DMA channel */
51extern int request_dma(unsigned int dmanr, const char * device_id);
52extern void free_dma(unsigned int dmanr);
53
54#ifdef CONFIG_PCI
55extern int isa_dma_bridge_buggy;
56#else
57#define isa_dma_bridge_buggy (0)
58#endif
59
60
61#endif
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
deleted file mode 100644
index c3f53e755ca5..000000000000
--- a/include/asm-xtensa/elf.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * include/asm-xtensa/elf.h
3 *
4 * ELF register definitions
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_ELF_H
14#define _XTENSA_ELF_H
15
16#include <asm/ptrace.h>
17
18/* Xtensa processor ELF architecture-magic number */
19
20#define EM_XTENSA 94
21#define EM_XTENSA_OLD 0xABC7
22
23/* Xtensa relocations defined by the ABIs */
24
25#define R_XTENSA_NONE 0
26#define R_XTENSA_32 1
27#define R_XTENSA_RTLD 2
28#define R_XTENSA_GLOB_DAT 3
29#define R_XTENSA_JMP_SLOT 4
30#define R_XTENSA_RELATIVE 5
31#define R_XTENSA_PLT 6
32#define R_XTENSA_OP0 8
33#define R_XTENSA_OP1 9
34#define R_XTENSA_OP2 10
35#define R_XTENSA_ASM_EXPAND 11
36#define R_XTENSA_ASM_SIMPLIFY 12
37#define R_XTENSA_GNU_VTINHERIT 15
38#define R_XTENSA_GNU_VTENTRY 16
39#define R_XTENSA_DIFF8 17
40#define R_XTENSA_DIFF16 18
41#define R_XTENSA_DIFF32 19
42#define R_XTENSA_SLOT0_OP 20
43#define R_XTENSA_SLOT1_OP 21
44#define R_XTENSA_SLOT2_OP 22
45#define R_XTENSA_SLOT3_OP 23
46#define R_XTENSA_SLOT4_OP 24
47#define R_XTENSA_SLOT5_OP 25
48#define R_XTENSA_SLOT6_OP 26
49#define R_XTENSA_SLOT7_OP 27
50#define R_XTENSA_SLOT8_OP 28
51#define R_XTENSA_SLOT9_OP 29
52#define R_XTENSA_SLOT10_OP 30
53#define R_XTENSA_SLOT11_OP 31
54#define R_XTENSA_SLOT12_OP 32
55#define R_XTENSA_SLOT13_OP 33
56#define R_XTENSA_SLOT14_OP 34
57#define R_XTENSA_SLOT0_ALT 35
58#define R_XTENSA_SLOT1_ALT 36
59#define R_XTENSA_SLOT2_ALT 37
60#define R_XTENSA_SLOT3_ALT 38
61#define R_XTENSA_SLOT4_ALT 39
62#define R_XTENSA_SLOT5_ALT 40
63#define R_XTENSA_SLOT6_ALT 41
64#define R_XTENSA_SLOT7_ALT 42
65#define R_XTENSA_SLOT8_ALT 43
66#define R_XTENSA_SLOT9_ALT 44
67#define R_XTENSA_SLOT10_ALT 45
68#define R_XTENSA_SLOT11_ALT 46
69#define R_XTENSA_SLOT12_ALT 47
70#define R_XTENSA_SLOT13_ALT 48
71#define R_XTENSA_SLOT14_ALT 49
72
73/* ELF register definitions. This is needed for core dump support. */
74
75typedef unsigned long elf_greg_t;
76
77typedef struct {
78 elf_greg_t pc;
79 elf_greg_t ps;
80 elf_greg_t lbeg;
81 elf_greg_t lend;
82 elf_greg_t lcount;
83 elf_greg_t sar;
84 elf_greg_t windowstart;
85 elf_greg_t windowbase;
86 elf_greg_t reserved[8+48];
87 elf_greg_t a[64];
88} xtensa_gregset_t;
89
90#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
91
92typedef elf_greg_t elf_gregset_t[ELF_NGREG];
93
94#define ELF_NFPREG 18
95
96typedef unsigned int elf_fpreg_t;
97typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
98
99#define ELF_CORE_COPY_REGS(_eregs, _pregs) \
100 xtensa_elf_core_copy_regs ((xtensa_gregset_t*)&(_eregs), _pregs);
101
102extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
103
104/*
105 * This is used to ensure we don't load something for the wrong architecture.
106 */
107
108#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA ) || \
109 ( (x)->e_machine == EM_XTENSA_OLD ) )
110
111/*
112 * These are used to set parameters in the core dumps.
113 */
114
115#ifdef __XTENSA_EL__
116# define ELF_DATA ELFDATA2LSB
117#elif defined(__XTENSA_EB__)
118# define ELF_DATA ELFDATA2MSB
119#else
120# error processor byte order undefined!
121#endif
122
123#define ELF_CLASS ELFCLASS32
124#define ELF_ARCH EM_XTENSA
125
126#define USE_ELF_CORE_DUMP
127#define ELF_EXEC_PAGESIZE PAGE_SIZE
128
129/*
130 * This is the location that an ET_DYN program is loaded if exec'ed. Typical
131 * use of this is to invoke "./ld.so someprog" to test out a new version of
132 * the loader. We need to make sure that it is out of the way of the program
133 * that it will "exec", and that there is sufficient room for the brk.
134 */
135
136#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
137
138/*
139 * This yields a mask that user programs can use to figure out what
140 * instruction set this CPU supports. This could be done in user space,
141 * but it's not easy, and we've already done it here.
142 */
143
144#define ELF_HWCAP (0)
145
146/*
147 * This yields a string that ld.so will use to load implementation
148 * specific libraries for optimization. This is more specific in
149 * intent than poking at uname or /proc/cpuinfo.
150 * For the moment, we have only optimizations for the Intel generations,
151 * but that could change...
152 */
153
154#define ELF_PLATFORM (NULL)
155
156/*
157 * The Xtensa processor ABI says that when the program starts, a2
158 * contains a pointer to a function which might be registered using
159 * `atexit'. This provides a mean for the dynamic linker to call
160 * DT_FINI functions for shared libraries that have been loaded before
161 * the code runs.
162 *
163 * A value of 0 tells we have no such handler.
164 *
165 * We might as well make sure everything else is cleared too (except
166 * for the stack pointer in a1), just to make things more
167 * deterministic. Also, clearing a0 terminates debugger backtraces.
168 */
169
170#define ELF_PLAT_INIT(_r, load_addr) \
171 do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0; _r->areg[3]=0; \
172 _r->areg[4]=0; _r->areg[5]=0; _r->areg[6]=0; _r->areg[7]=0; \
173 _r->areg[8]=0; _r->areg[9]=0; _r->areg[10]=0; _r->areg[11]=0; \
174 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
175 } while (0)
176
177typedef struct {
178 xtregs_opt_t opt;
179 xtregs_user_t user;
180#if XTENSA_HAVE_COPROCESSORS
181 xtregs_cp0_t cp0;
182 xtregs_cp1_t cp1;
183 xtregs_cp2_t cp2;
184 xtregs_cp3_t cp3;
185 xtregs_cp4_t cp4;
186 xtregs_cp5_t cp5;
187 xtregs_cp6_t cp6;
188 xtregs_cp7_t cp7;
189#endif
190} elf_xtregs_t;
191
192#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
193
194struct task_struct;
195
196extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*,
197 struct task_struct*);
198extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*,
199 struct task_struct*);
200extern void do_save_fpregs (elf_fpregset_t*, struct pt_regs*,
201 struct task_struct*);
202extern int do_restore_fpregs (elf_fpregset_t*, struct pt_regs*,
203 struct task_struct*);
204
205#endif /* _XTENSA_ELF_H */
diff --git a/include/asm-xtensa/emergency-restart.h b/include/asm-xtensa/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-xtensa/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-xtensa/errno.h b/include/asm-xtensa/errno.h
deleted file mode 100644
index a0f3b96b79b4..000000000000
--- a/include/asm-xtensa/errno.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/errno.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2002 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_ERRNO_H
12#define _XTENSA_ERRNO_H
13
14#include <asm-generic/errno.h>
15
16#endif /* _XTENSA_ERRNO_H */
diff --git a/include/asm-xtensa/fb.h b/include/asm-xtensa/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/include/asm-xtensa/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3#include <linux/fb.h>
4
5#define fb_pgprotect(...) do {} while (0)
6
7static inline int fb_is_primary_device(struct fb_info *info)
8{
9 return 0;
10}
11
12#endif /* _ASM_FB_H_ */
diff --git a/include/asm-xtensa/fcntl.h b/include/asm-xtensa/fcntl.h
deleted file mode 100644
index 46ab12db5739..000000000000
--- a/include/asm-xtensa/fcntl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/fcntl.h>
diff --git a/include/asm-xtensa/futex.h b/include/asm-xtensa/futex.h
deleted file mode 100644
index 0b745828f42b..000000000000
--- a/include/asm-xtensa/futex.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/futex.h>
diff --git a/include/asm-xtensa/hardirq.h b/include/asm-xtensa/hardirq.h
deleted file mode 100644
index 87cb19d1b10c..000000000000
--- a/include/asm-xtensa/hardirq.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * include/asm-xtensa/hardirq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2002 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_HARDIRQ_H
12#define _XTENSA_HARDIRQ_H
13
14#include <linux/cache.h>
15#include <asm/irq.h>
16
17/* headers.S is sensitive to the offsets of these fields */
18typedef struct {
19 unsigned int __softirq_pending;
20 unsigned int __syscall_count;
21 struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
22 unsigned int __nmi_count; /* arch dependent */
23} ____cacheline_aligned irq_cpustat_t;
24
25void ack_bad_irq(unsigned int irq);
26#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
27
28#endif /* _XTENSA_HARDIRQ_H */
diff --git a/include/asm-xtensa/highmem.h b/include/asm-xtensa/highmem.h
deleted file mode 100644
index 0a046ca5a687..000000000000
--- a/include/asm-xtensa/highmem.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * include/asm-xtensa/highmem.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_HIGHMEM_H
12#define _XTENSA_HIGHMEM_H
13
14extern void flush_cache_kmaps(void);
15
16#endif
17
diff --git a/include/asm-xtensa/hw_irq.h b/include/asm-xtensa/hw_irq.h
deleted file mode 100644
index 3ddbea759b2b..000000000000
--- a/include/asm-xtensa/hw_irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * include/asm-xtensa/hw_irq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2002 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_HW_IRQ_H
12#define _XTENSA_HW_IRQ_H
13
14#endif
diff --git a/include/asm-xtensa/io.h b/include/asm-xtensa/io.h
deleted file mode 100644
index 07b7299dab20..000000000000
--- a/include/asm-xtensa/io.h
+++ /dev/null
@@ -1,200 +0,0 @@
1/*
2 * include/asm-xtensa/io.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_IO_H
12#define _XTENSA_IO_H
13
14#ifdef __KERNEL__
15#include <asm/byteorder.h>
16#include <asm/page.h>
17#include <linux/kernel.h>
18
19#include <linux/types.h>
20
21#define XCHAL_KIO_CACHED_VADDR 0xe0000000
22#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
23#define XCHAL_KIO_PADDR 0xf0000000
24#define XCHAL_KIO_SIZE 0x10000000
25
26#define IOADDR(x) (XCHAL_KIO_BYPASS_VADDR + (x))
27
28/*
29 * swap functions to change byte order from little-endian to big-endian and
30 * vice versa.
31 */
32
33static inline unsigned short _swapw (unsigned short v)
34{
35 return (v << 8) | (v >> 8);
36}
37
38static inline unsigned int _swapl (unsigned int v)
39{
40 return (v << 24) | ((v & 0xff00) << 8) | ((v >> 8) & 0xff00) | (v >> 24);
41}
42
43/*
44 * Change virtual addresses to physical addresses and vv.
45 * These are trivial on the 1:1 Linux/Xtensa mapping
46 */
47
48static inline unsigned long virt_to_phys(volatile void * address)
49{
50 return __pa(address);
51}
52
53static inline void * phys_to_virt(unsigned long address)
54{
55 return __va(address);
56}
57
58/*
59 * virt_to_bus and bus_to_virt are deprecated.
60 */
61
62#define virt_to_bus(x) virt_to_phys(x)
63#define bus_to_virt(x) phys_to_virt(x)
64
65/*
66 * Return the virtual (cached) address for the specified bus memory.
67 * Note that we currently don't support any address outside the KIO segment.
68 */
69
70static inline void *ioremap(unsigned long offset, unsigned long size)
71{
72 if (offset >= XCHAL_KIO_PADDR
73 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
74 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
75
76 else
77 BUG();
78}
79
80static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
81{
82 if (offset >= XCHAL_KIO_PADDR
83 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
84 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
85 else
86 BUG();
87}
88
89static inline void iounmap(void *addr)
90{
91}
92
93/*
94 * Generic I/O
95 */
96
97#define readb(addr) \
98 ({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
99#define readw(addr) \
100 ({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; })
101#define readl(addr) \
102 ({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; })
103#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
104#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b))
105#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b))
106
107static inline __u8 __raw_readb(const volatile void __iomem *addr)
108{
109 return *(__force volatile __u8 *)(addr);
110}
111static inline __u16 __raw_readw(const volatile void __iomem *addr)
112{
113 return *(__force volatile __u16 *)(addr);
114}
115static inline __u32 __raw_readl(const volatile void __iomem *addr)
116{
117 return *(__force volatile __u32 *)(addr);
118}
119static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
120{
121 *(__force volatile __u8 *)(addr) = b;
122}
123static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
124{
125 *(__force volatile __u16 *)(addr) = b;
126}
127static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
128{
129 *(__force volatile __u32 *)(addr) = b;
130}
131
132/* These are the definitions for the x86 IO instructions
133 * inb/inw/inl/outb/outw/outl, the "string" versions
134 * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
135 * inb_p/inw_p/...
136 * The macros don't do byte-swapping.
137 */
138
139#define inb(port) readb((u8 *)((port)))
140#define outb(val, port) writeb((val),(u8 *)((unsigned long)(port)))
141#define inw(port) readw((u16 *)((port)))
142#define outw(val, port) writew((val),(u16 *)((unsigned long)(port)))
143#define inl(port) readl((u32 *)((port)))
144#define outl(val, port) writel((val),(u32 *)((unsigned long)(port)))
145
146#define inb_p(port) inb((port))
147#define outb_p(val, port) outb((val), (port))
148#define inw_p(port) inw((port))
149#define outw_p(val, port) outw((val), (port))
150#define inl_p(port) inl((port))
151#define outl_p(val, port) outl((val), (port))
152
153extern void insb (unsigned long port, void *dst, unsigned long count);
154extern void insw (unsigned long port, void *dst, unsigned long count);
155extern void insl (unsigned long port, void *dst, unsigned long count);
156extern void outsb (unsigned long port, const void *src, unsigned long count);
157extern void outsw (unsigned long port, const void *src, unsigned long count);
158extern void outsl (unsigned long port, const void *src, unsigned long count);
159
160#define IO_SPACE_LIMIT ~0
161
162#define memset_io(a,b,c) memset((void *)(a),(b),(c))
163#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
164#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
165
166/* At this point the Xtensa doesn't provide byte swap instructions */
167
168#ifdef __XTENSA_EB__
169# define in_8(addr) (*(u8*)(addr))
170# define in_le16(addr) _swapw(*(u16*)(addr))
171# define in_le32(addr) _swapl(*(u32*)(addr))
172# define out_8(b, addr) *(u8*)(addr) = (b)
173# define out_le16(b, addr) *(u16*)(addr) = _swapw(b)
174# define out_le32(b, addr) *(u32*)(addr) = _swapl(b)
175#elif defined(__XTENSA_EL__)
176# define in_8(addr) (*(u8*)(addr))
177# define in_le16(addr) (*(u16*)(addr))
178# define in_le32(addr) (*(u32*)(addr))
179# define out_8(b, addr) *(u8*)(addr) = (b)
180# define out_le16(b, addr) *(u16*)(addr) = (b)
181# define out_le32(b, addr) *(u32*)(addr) = (b)
182#else
183# error processor byte order undefined!
184#endif
185
186
187/*
188 * Convert a physical pointer to a virtual kernel pointer for /dev/mem access
189 */
190#define xlate_dev_mem_ptr(p) __va(p)
191
192/*
193 * Convert a virtual cached pointer to an uncached pointer
194 */
195#define xlate_dev_kmem_ptr(p) p
196
197
198#endif /* __KERNEL__ */
199
200#endif /* _XTENSA_IO_H */
diff --git a/include/asm-xtensa/ioctl.h b/include/asm-xtensa/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-xtensa/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/ioctl.h>
diff --git a/include/asm-xtensa/ioctls.h b/include/asm-xtensa/ioctls.h
deleted file mode 100644
index 0ffa942954b9..000000000000
--- a/include/asm-xtensa/ioctls.h
+++ /dev/null
@@ -1,116 +0,0 @@
1/*
2 * include/asm-xtensa/ioctls.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2003 - 2005 Tensilica Inc.
9 *
10 * Derived from "include/asm-i386/ioctls.h"
11 */
12
13#ifndef _XTENSA_IOCTLS_H
14#define _XTENSA_IOCTLS_H
15
16#include <asm/ioctl.h>
17
18#define FIOCLEX _IO('f', 1)
19#define FIONCLEX _IO('f', 2)
20#define FIOASYNC _IOW('f', 125, int)
21#define FIONBIO _IOW('f', 126, int)
22#define FIONREAD _IOR('f', 127, int)
23#define TIOCINQ FIONREAD
24#define FIOQSIZE _IOR('f', 128, loff_t)
25
26#define TCGETS 0x5401
27#define TCSETS 0x5402
28#define TCSETSW 0x5403
29#define TCSETSF 0x5404
30
31#define TCGETA _IOR('t', 23, struct termio)
32#define TCSETA _IOW('t', 24, struct termio)
33#define TCSETAW _IOW('t', 25, struct termio)
34#define TCSETAF _IOW('t', 28, struct termio)
35
36#define TCSBRK _IO('t', 29)
37#define TCXONC _IO('t', 30)
38#define TCFLSH _IO('t', 31)
39
40#define TIOCSWINSZ _IOW('t', 103, struct winsize)
41#define TIOCGWINSZ _IOR('t', 104, struct winsize)
42#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
43#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
44#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
45
46#define TIOCSPGRP _IOW('t', 118, int)
47#define TIOCGPGRP _IOR('t', 119, int)
48
49#define TIOCEXCL _IO('T', 12)
50#define TIOCNXCL _IO('T', 13)
51#define TIOCSCTTY _IO('T', 14)
52
53#define TIOCSTI _IOW('T', 18, char)
54#define TIOCMGET _IOR('T', 21, unsigned int)
55#define TIOCMBIS _IOW('T', 22, unsigned int)
56#define TIOCMBIC _IOW('T', 23, unsigned int)
57#define TIOCMSET _IOW('T', 24, unsigned int)
58# define TIOCM_LE 0x001
59# define TIOCM_DTR 0x002
60# define TIOCM_RTS 0x004
61# define TIOCM_ST 0x008
62# define TIOCM_SR 0x010
63# define TIOCM_CTS 0x020
64# define TIOCM_CAR 0x040
65# define TIOCM_RNG 0x080
66# define TIOCM_DSR 0x100
67# define TIOCM_CD TIOCM_CAR
68# define TIOCM_RI TIOCM_RNG
69
70#define TIOCGSOFTCAR _IOR('T', 25, unsigned int)
71#define TIOCSSOFTCAR _IOW('T', 26, unsigned int)
72#define TIOCLINUX _IOW('T', 28, char)
73#define TIOCCONS _IO('T', 29)
74#define TIOCGSERIAL _IOR('T', 30, struct serial_struct)
75#define TIOCSSERIAL _IOW('T', 31, struct serial_struct)
76#define TIOCPKT _IOW('T', 32, int)
77# define TIOCPKT_DATA 0
78# define TIOCPKT_FLUSHREAD 1
79# define TIOCPKT_FLUSHWRITE 2
80# define TIOCPKT_STOP 4
81# define TIOCPKT_START 8
82# define TIOCPKT_NOSTOP 16
83# define TIOCPKT_DOSTOP 32
84
85
86#define TIOCNOTTY _IO('T', 34)
87#define TIOCSETD _IOW('T', 35, int)
88#define TIOCGETD _IOR('T', 36, int)
89#define TCSBRKP _IOW('T', 37, int) /* Needed for POSIX tcsendbreak()*/
90#define TIOCTTYGSTRUCT _IOR('T', 38, struct tty_struct) /* For debugging only*/
91#define TIOCSBRK _IO('T', 39) /* BSD compatibility */
92#define TIOCCBRK _IO('T', 40) /* BSD compatibility */
93#define TIOCGSID _IOR('T', 41, pid_t) /* Return the session ID of FD*/
94#define TCGETS2 _IOR('T', 42, struct termios2)
95#define TCSETS2 _IOW('T', 43, struct termios2)
96#define TCSETSW2 _IOW('T', 44, struct termios2)
97#define TCSETSF2 _IOW('T', 45, struct termios2)
98#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
99#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
100
101#define TIOCSERCONFIG _IO('T', 83)
102#define TIOCSERGWILD _IOR('T', 84, int)
103#define TIOCSERSWILD _IOW('T', 85, int)
104#define TIOCGLCKTRMIOS 0x5456
105#define TIOCSLCKTRMIOS 0x5457
106#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
107#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* Get line status reg. */
108 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
109# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
110#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* Get multiport config */
111#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* Set multiport config */
112
113#define TIOCMIWAIT _IO('T', 92) /* wait for a change on serial input line(s) */
114#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
115
116#endif /* _XTENSA_IOCTLS_H */
diff --git a/include/asm-xtensa/ipcbuf.h b/include/asm-xtensa/ipcbuf.h
deleted file mode 100644
index c33aa6a42145..000000000000
--- a/include/asm-xtensa/ipcbuf.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * include/asm-xtensa/ipcbuf.h
3 *
4 * The ipc64_perm structure for the Xtensa architecture.
5 * Note extra padding because this structure is passed back and forth
6 * between kernel and user space.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_IPCBUF_H
12#define _XTENSA_IPCBUF_H
13
14/*
15 * Pad space is left for:
16 * - 32-bit mode_t and seq
17 * - 2 miscellaneous 32-bit values
18 *
19 * This file is subject to the terms and conditions of the GNU General
20 * Public License. See the file "COPYING" in the main directory of
21 * this archive for more details.
22 */
23
24struct ipc64_perm
25{
26 __kernel_key_t key;
27 __kernel_uid32_t uid;
28 __kernel_gid32_t gid;
29 __kernel_uid32_t cuid;
30 __kernel_gid32_t cgid;
31 __kernel_mode_t mode;
32 unsigned long seq;
33 unsigned long __unused1;
34 unsigned long __unused2;
35};
36
37#endif /* _XTENSA_IPCBUF_H */
diff --git a/include/asm-xtensa/irq.h b/include/asm-xtensa/irq.h
deleted file mode 100644
index fc73b7f11aff..000000000000
--- a/include/asm-xtensa/irq.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * include/asm-xtensa/irq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_IRQ_H
12#define _XTENSA_IRQ_H
13
14#include <asm/platform/hardware.h>
15#include <asm/variant/core.h>
16
17#ifndef PLATFORM_NR_IRQS
18# define PLATFORM_NR_IRQS 0
19#endif
20#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
21#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
22
23static __inline__ int irq_canonicalize(int irq)
24{
25 return (irq);
26}
27
28struct irqaction;
29
30#endif /* _XTENSA_IRQ_H */
diff --git a/include/asm-xtensa/irq_regs.h b/include/asm-xtensa/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-xtensa/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/irq_regs.h>
diff --git a/include/asm-xtensa/kdebug.h b/include/asm-xtensa/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-xtensa/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/kdebug.h>
diff --git a/include/asm-xtensa/kmap_types.h b/include/asm-xtensa/kmap_types.h
deleted file mode 100644
index 9e822d2e3bce..000000000000
--- a/include/asm-xtensa/kmap_types.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * include/asm-xtensa/kmap_types.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_KMAP_TYPES_H
12#define _XTENSA_KMAP_TYPES_H
13
14enum km_type {
15 KM_BOUNCE_READ,
16 KM_SKB_SUNRPC_DATA,
17 KM_SKB_DATA_SOFTIRQ,
18 KM_USER0,
19 KM_USER1,
20 KM_BIO_SRC_IRQ,
21 KM_BIO_DST_IRQ,
22 KM_PTE0,
23 KM_PTE1,
24 KM_IRQ0,
25 KM_IRQ1,
26 KM_SOFTIRQ0,
27 KM_SOFTIRQ1,
28 KM_TYPE_NR
29};
30
31#endif /* _XTENSA_KMAP_TYPES_H */
diff --git a/include/asm-xtensa/linkage.h b/include/asm-xtensa/linkage.h
deleted file mode 100644
index bf2128a99d79..000000000000
--- a/include/asm-xtensa/linkage.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/linkage.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_LINKAGE_H
12#define _XTENSA_LINKAGE_H
13
14/* Nothing to do here ... */
15
16#endif /* _XTENSA_LINKAGE_H */
diff --git a/include/asm-xtensa/local.h b/include/asm-xtensa/local.h
deleted file mode 100644
index 48723e550d14..000000000000
--- a/include/asm-xtensa/local.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/local.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_LOCAL_H
12#define _XTENSA_LOCAL_H
13
14#include <asm-generic/local.h>
15
16#endif /* _XTENSA_LOCAL_H */
diff --git a/include/asm-xtensa/mman.h b/include/asm-xtensa/mman.h
deleted file mode 100644
index 9b92620c8a1e..000000000000
--- a/include/asm-xtensa/mman.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * include/asm-xtensa/mman.h
3 *
4 * Xtensa Processor memory-manager definitions
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1995 by Ralf Baechle
11 * Copyright (C) 2001 - 2005 Tensilica Inc.
12 */
13
14#ifndef _XTENSA_MMAN_H
15#define _XTENSA_MMAN_H
16
17/*
18 * Protections are chosen from these bits, OR'd together. The
19 * implementation does not necessarily support PROT_EXEC or PROT_WRITE
20 * without PROT_READ. The only guarantees are that no writing will be
21 * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
22 */
23
24#define PROT_NONE 0x0 /* page can not be accessed */
25#define PROT_READ 0x1 /* page can be read */
26#define PROT_WRITE 0x2 /* page can be written */
27#define PROT_EXEC 0x4 /* page can be executed */
28
29#define PROT_SEM 0x10 /* page may be used for atomic ops */
30#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
31#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end fo growsup vma */
32
33/*
34 * Flags for mmap
35 */
36#define MAP_SHARED 0x001 /* Share changes */
37#define MAP_PRIVATE 0x002 /* Changes are private */
38#define MAP_TYPE 0x00f /* Mask for type of mapping */
39#define MAP_FIXED 0x010 /* Interpret addr exactly */
40
41/* not used by linux, but here to make sure we don't clash with ABI defines */
42#define MAP_RENAME 0x020 /* Assign page to file */
43#define MAP_AUTOGROW 0x040 /* File may grow by writing */
44#define MAP_LOCAL 0x080 /* Copy on fork/sproc */
45#define MAP_AUTORSRV 0x100 /* Logical swap reserved on demand */
46
47/* These are linux-specific */
48#define MAP_NORESERVE 0x0400 /* don't check for reservations */
49#define MAP_ANONYMOUS 0x0800 /* don't use a file */
50#define MAP_GROWSDOWN 0x1000 /* stack-like segment */
51#define MAP_DENYWRITE 0x2000 /* ETXTBSY */
52#define MAP_EXECUTABLE 0x4000 /* mark it as an executable */
53#define MAP_LOCKED 0x8000 /* pages are locked */
54#define MAP_POPULATE 0x10000 /* populate (prefault) pagetables */
55#define MAP_NONBLOCK 0x20000 /* do not block on IO */
56
57/*
58 * Flags for msync
59 */
60#define MS_ASYNC 0x0001 /* sync memory asynchronously */
61#define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */
62#define MS_SYNC 0x0004 /* synchronous memory sync */
63
64/*
65 * Flags for mlockall
66 */
67#define MCL_CURRENT 1 /* lock all current mappings */
68#define MCL_FUTURE 2 /* lock all future mappings */
69
70#define MADV_NORMAL 0 /* no further special treatment */
71#define MADV_RANDOM 1 /* expect random page references */
72#define MADV_SEQUENTIAL 2 /* expect sequential page references */
73#define MADV_WILLNEED 3 /* will need these pages */
74#define MADV_DONTNEED 4 /* don't need these pages */
75
76/* common parameters: try to keep these consistent across architectures */
77#define MADV_REMOVE 9 /* remove these pages & resources */
78#define MADV_DONTFORK 10 /* don't inherit across fork */
79#define MADV_DOFORK 11 /* do inherit across fork */
80
81/* compatibility flags */
82#define MAP_FILE 0
83
84#endif /* _XTENSA_MMAN_H */
diff --git a/include/asm-xtensa/mmu.h b/include/asm-xtensa/mmu.h
deleted file mode 100644
index 44c5bb04c55c..000000000000
--- a/include/asm-xtensa/mmu.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * include/asm-xtensa/mmu.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_MMU_H
12#define _XTENSA_MMU_H
13
14/* Default "unsigned long" context */
15typedef unsigned long mm_context_t;
16
17#endif /* _XTENSA_MMU_H */
diff --git a/include/asm-xtensa/mmu_context.h b/include/asm-xtensa/mmu_context.h
deleted file mode 100644
index c0fd8e5b4513..000000000000
--- a/include/asm-xtensa/mmu_context.h
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * include/asm-xtensa/mmu_context.h
3 *
4 * Switch an MMU context.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_MMU_CONTEXT_H
14#define _XTENSA_MMU_CONTEXT_H
15
16#include <linux/stringify.h>
17#include <linux/sched.h>
18
19#include <asm/pgtable.h>
20#include <asm/cacheflush.h>
21#include <asm/tlbflush.h>
22#include <asm-generic/mm_hooks.h>
23
24#define XCHAL_MMU_ASID_BITS 8
25
26#if (XCHAL_HAVE_TLBS != 1)
27# error "Linux must have an MMU!"
28#endif
29
30extern unsigned long asid_cache;
31
32/*
33 * NO_CONTEXT is the invalid ASID value that we don't ever assign to
34 * any user or kernel context.
35 *
36 * 0 invalid
37 * 1 kernel
38 * 2 reserved
39 * 3 reserved
40 * 4...255 available
41 */
42
43#define NO_CONTEXT 0
44#define ASID_USER_FIRST 4
45#define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
46#define ASID_INSERT(x) (0x03020001 | (((x) & ASID_MASK) << 8))
47
48static inline void set_rasid_register (unsigned long val)
49{
50 __asm__ __volatile__ (" wsr %0, "__stringify(RASID)"\n\t"
51 " isync\n" : : "a" (val));
52}
53
54static inline unsigned long get_rasid_register (void)
55{
56 unsigned long tmp;
57 __asm__ __volatile__ (" rsr %0,"__stringify(RASID)"\n\t" : "=a" (tmp));
58 return tmp;
59}
60
61static inline void
62__get_new_mmu_context(struct mm_struct *mm)
63{
64 extern void flush_tlb_all(void);
65 if (! (++asid_cache & ASID_MASK) ) {
66 flush_tlb_all(); /* start new asid cycle */
67 asid_cache += ASID_USER_FIRST;
68 }
69 mm->context = asid_cache;
70}
71
72static inline void
73__load_mmu_context(struct mm_struct *mm)
74{
75 set_rasid_register(ASID_INSERT(mm->context));
76 invalidate_page_directory();
77}
78
79/*
80 * Initialize the context related info for a new mm_struct
81 * instance.
82 */
83
84static inline int
85init_new_context(struct task_struct *tsk, struct mm_struct *mm)
86{
87 mm->context = NO_CONTEXT;
88 return 0;
89}
90
91/*
92 * After we have set current->mm to a new value, this activates
93 * the context for the new mm so we see the new mappings.
94 */
95static inline void
96activate_mm(struct mm_struct *prev, struct mm_struct *next)
97{
98 /* Unconditionally get a new ASID. */
99
100 __get_new_mmu_context(next);
101 __load_mmu_context(next);
102}
103
104
105static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
106 struct task_struct *tsk)
107{
108 unsigned long asid = asid_cache;
109
110 /* Check if our ASID is of an older version and thus invalid */
111
112 if (next->context == NO_CONTEXT || ((next->context^asid) & ~ASID_MASK))
113 __get_new_mmu_context(next);
114
115 __load_mmu_context(next);
116}
117
118#define deactivate_mm(tsk, mm) do { } while(0)
119
120/*
121 * Destroy context related info for an mm_struct that is about
122 * to be put to rest.
123 */
124static inline void destroy_context(struct mm_struct *mm)
125{
126 invalidate_page_directory();
127}
128
129
130static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
131{
132 /* Nothing to do. */
133
134}
135
136#endif /* _XTENSA_MMU_CONTEXT_H */
diff --git a/include/asm-xtensa/module.h b/include/asm-xtensa/module.h
deleted file mode 100644
index d9b34bee4d42..000000000000
--- a/include/asm-xtensa/module.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * include/asm-xtensa/module.h
3 *
4 * This file contains the module code specific to the Xtensa architecture.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_MODULE_H
14#define _XTENSA_MODULE_H
15
16struct mod_arch_specific
17{
18 /* No special elements, yet. */
19};
20
21#define MODULE_ARCH_VERMAGIC "xtensa-" __stringify(XCHAL_CORE_ID) " "
22
23#define Elf_Shdr Elf32_Shdr
24#define Elf_Sym Elf32_Sym
25#define Elf_Ehdr Elf32_Ehdr
26
27#endif /* _XTENSA_MODULE_H */
diff --git a/include/asm-xtensa/msgbuf.h b/include/asm-xtensa/msgbuf.h
deleted file mode 100644
index 693c96755280..000000000000
--- a/include/asm-xtensa/msgbuf.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * include/asm-xtensa/msgbuf.h
3 *
4 * The msqid64_ds structure for the Xtensa architecture.
5 * Note extra padding because this structure is passed back and forth
6 * between kernel and user space.
7 *
8 * Pad space is left for:
9 * - 64-bit time_t to solve y2038 problem
10 * - 2 miscellaneous 32-bit values
11 *
12 * This file is subject to the terms and conditions of the GNU General
13 * Public License. See the file "COPYING" in the main directory of
14 * this archive for more details.
15 */
16
17#ifndef _XTENSA_MSGBUF_H
18#define _XTENSA_MSGBUF_H
19
20struct msqid64_ds {
21 struct ipc64_perm msg_perm;
22#ifdef __XTENSA_EB__
23 unsigned int __unused1;
24 __kernel_time_t msg_stime; /* last msgsnd time */
25 unsigned int __unused2;
26 __kernel_time_t msg_rtime; /* last msgrcv time */
27 unsigned int __unused3;
28 __kernel_time_t msg_ctime; /* last change time */
29#elif defined(__XTENSA_EL__)
30 __kernel_time_t msg_stime; /* last msgsnd time */
31 unsigned int __unused1;
32 __kernel_time_t msg_rtime; /* last msgrcv time */
33 unsigned int __unused2;
34 __kernel_time_t msg_ctime; /* last change time */
35 unsigned int __unused3;
36#else
37# error processor byte order undefined!
38#endif
39 unsigned long msg_cbytes; /* current number of bytes on queue */
40 unsigned long msg_qnum; /* number of messages in queue */
41 unsigned long msg_qbytes; /* max number of bytes on queue */
42 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
43 __kernel_pid_t msg_lrpid; /* last receive pid */
44 unsigned long __unused4;
45 unsigned long __unused5;
46};
47
48#endif /* _XTENSA_MSGBUF_H */
diff --git a/include/asm-xtensa/mutex.h b/include/asm-xtensa/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-xtensa/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/*
2 * Pull in the generic implementation for the mutex fastpath.
3 *
4 * TODO: implement optimized primitives instead, or leave the generic
5 * implementation in place, or pick the atomic_xchg() based generic
6 * implementation. (see asm-generic/mutex-xchg.h for details)
7 */
8
9#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-xtensa/page.h b/include/asm-xtensa/page.h
deleted file mode 100644
index 11f7dc2dbec7..000000000000
--- a/include/asm-xtensa/page.h
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * include/asm-xtensa/page.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PAGE_H
12#define _XTENSA_PAGE_H
13
14#include <asm/processor.h>
15#include <asm/types.h>
16#include <asm/cache.h>
17
18/*
19 * Fixed TLB translations in the processor.
20 */
21
22#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
23#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
24#define XCHAL_KSEG_PADDR 0x00000000
25#define XCHAL_KSEG_SIZE 0x08000000
26
27/*
28 * PAGE_SHIFT determines the page size
29 */
30
31#define PAGE_SHIFT 12
32#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
33#define PAGE_MASK (~(PAGE_SIZE-1))
34
35#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
36#define MAX_MEM_PFN XCHAL_KSEG_SIZE
37#define PGTABLE_START 0x80000000
38
39/*
40 * Cache aliasing:
41 *
42 * If the cache size for one way is greater than the page size, we have to
43 * deal with cache aliasing. The cache index is wider than the page size:
44 *
45 * | |cache| cache index
46 * | pfn |off| virtual address
47 * |xxxx:X|zzz|
48 * | : | |
49 * | \ / | |
50 * |trans.| |
51 * | / \ | |
52 * |yyyy:Y|zzz| physical address
53 *
54 * When the page number is translated to the physical page address, the lowest
55 * bit(s) (X) that are part of the cache index are also translated (Y).
56 * If this translation changes bit(s) (X), the cache index is also afected,
57 * thus resulting in a different cache line than before.
58 * The kernel does not provide a mechanism to ensure that the page color
59 * (represented by this bit) remains the same when allocated or when pages
60 * are remapped. When user pages are mapped into kernel space, the color of
61 * the page might also change.
62 *
63 * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
64 * to temporarily map a patch so we can match the color.
65 */
66
67#if DCACHE_WAY_SIZE > PAGE_SIZE
68# define DCACHE_ALIAS_ORDER (DCACHE_WAY_SHIFT - PAGE_SHIFT)
69# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
70# define DCACHE_ALIAS(a) (((a) & DCACHE_ALIAS_MASK) >> PAGE_SHIFT)
71# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
72#else
73# define DCACHE_ALIAS_ORDER 0
74#endif
75
76#if ICACHE_WAY_SIZE > PAGE_SIZE
77# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT)
78# define ICACHE_ALIAS_MASK (PAGE_MASK & (ICACHE_WAY_SIZE - 1))
79# define ICACHE_ALIAS(a) (((a) & ICACHE_ALIAS_MASK) >> PAGE_SHIFT)
80# define ICACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & ICACHE_ALIAS_MASK) == 0)
81#else
82# define ICACHE_ALIAS_ORDER 0
83#endif
84
85
86#ifdef __ASSEMBLY__
87
88#define __pgprot(x) (x)
89
90#else
91
92/*
93 * These are used to make use of C type-checking..
94 */
95
96typedef struct { unsigned long pte; } pte_t; /* page table entry */
97typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
98typedef struct { unsigned long pgprot; } pgprot_t;
99typedef struct page *pgtable_t;
100
101#define pte_val(x) ((x).pte)
102#define pgd_val(x) ((x).pgd)
103#define pgprot_val(x) ((x).pgprot)
104
105#define __pte(x) ((pte_t) { (x) } )
106#define __pgd(x) ((pgd_t) { (x) } )
107#define __pgprot(x) ((pgprot_t) { (x) } )
108
109/*
110 * Pure 2^n version of get_order
111 * Use 'nsau' instructions if supported by the processor or the generic version.
112 */
113
114#if XCHAL_HAVE_NSA
115
116static inline __attribute_const__ int get_order(unsigned long size)
117{
118 int lz;
119 asm ("nsau %0, %1" : "=r" (lz) : "r" ((size - 1) >> PAGE_SHIFT));
120 return 32 - lz;
121}
122
123#else
124
125# include <asm-generic/page.h>
126
127#endif
128
129struct page;
130extern void clear_page(void *page);
131extern void copy_page(void *to, void *from);
132
133/*
134 * If we have cache aliasing and writeback caches, we might have to do
135 * some extra work
136 */
137
138#if DCACHE_WAY_SIZE > PAGE_SIZE
139extern void clear_user_page(void*, unsigned long, struct page*);
140extern void copy_user_page(void*, void*, unsigned long, struct page*);
141#else
142# define clear_user_page(page, vaddr, pg) clear_page(page)
143# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
144#endif
145
146/*
147 * This handles the memory map. We handle pages at
148 * XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
149 * These macros are for conversion of kernel address, not user
150 * addresses.
151 */
152
153#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
154#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
155#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr)
156#ifdef CONFIG_DISCONTIGMEM
157# error CONFIG_DISCONTIGMEM not supported
158#endif
159
160#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
161#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
162#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
163#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
164
165#define WANT_PAGE_VIRTUAL
166
167
168#endif /* __ASSEMBLY__ */
169
170#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
171 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
172
173#include <asm-generic/memory_model.h>
174#endif /* _XTENSA_PAGE_H */
diff --git a/include/asm-xtensa/param.h b/include/asm-xtensa/param.h
deleted file mode 100644
index ba03d5aeab6b..000000000000
--- a/include/asm-xtensa/param.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * include/asm-xtensa/param.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PARAM_H
12#define _XTENSA_PARAM_H
13
14#ifdef __KERNEL__
15# define HZ CONFIG_HZ /* internal timer frequency */
16# define USER_HZ 100 /* for user interfaces in "ticks" */
17# define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */
18#else
19# define HZ 100
20#endif
21
22#define EXEC_PAGESIZE 4096
23
24#ifndef NGROUPS
25#define NGROUPS 32
26#endif
27
28#ifndef NOGROUP
29#define NOGROUP (-1)
30#endif
31
32#define MAXHOSTNAMELEN 64 /* max length of hostname */
33
34#endif /* _XTENSA_PARAM_H */
diff --git a/include/asm-xtensa/pci-bridge.h b/include/asm-xtensa/pci-bridge.h
deleted file mode 100644
index 00fcbd7c534a..000000000000
--- a/include/asm-xtensa/pci-bridge.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * include/asm-xtensa/pci-bridge.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PCI_BRIDGE_H
12#define _XTENSA_PCI_BRIDGE_H
13
14#ifdef __KERNEL__
15
16struct device_node;
17struct pci_controller;
18
19/*
20 * pciauto_bus_scan() enumerates the pci space.
21 */
22
23extern int pciauto_bus_scan(struct pci_controller *, int);
24
25struct pci_space {
26 unsigned long start;
27 unsigned long end;
28 unsigned long base;
29};
30
31/*
32 * Structure of a PCI controller (host bridge)
33 */
34
35struct pci_controller {
36 int index; /* used for pci_controller_num */
37 struct pci_controller *next;
38 struct pci_bus *bus;
39 void *arch_data;
40
41 int first_busno;
42 int last_busno;
43
44 struct pci_ops *ops;
45 volatile unsigned int *cfg_addr;
46 volatile unsigned char *cfg_data;
47
48 /* Currently, we limit ourselves to 1 IO range and 3 mem
49 * ranges since the common pci_bus structure can't handle more
50 */
51 struct resource io_resource;
52 struct resource mem_resources[3];
53 int mem_resource_count;
54
55 /* Host bridge I/O and Memory space
56 * Used for BAR placement algorithms
57 */
58 struct pci_space io_space;
59 struct pci_space mem_space;
60
61 /* Return the interrupt number fo a device. */
62 int (*map_irq)(struct pci_dev*, u8, u8);
63
64};
65
66static inline void pcibios_init_resource(struct resource *res,
67 unsigned long start, unsigned long end, int flags, char *name)
68{
69 res->start = start;
70 res->end = end;
71 res->flags = flags;
72 res->name = name;
73 res->parent = NULL;
74 res->sibling = NULL;
75 res->child = NULL;
76}
77
78
79/* These are used for config access before all the PCI probing has been done. */
80int early_read_config_byte(struct pci_controller*, int, int, int, u8*);
81int early_read_config_word(struct pci_controller*, int, int, int, u16*);
82int early_read_config_dword(struct pci_controller*, int, int, int, u32*);
83int early_write_config_byte(struct pci_controller*, int, int, int, u8);
84int early_write_config_word(struct pci_controller*, int, int, int, u16);
85int early_write_config_dword(struct pci_controller*, int, int, int, u32);
86
87#endif /* __KERNEL__ */
88#endif /* _XTENSA_PCI_BRIDGE_H */
diff --git a/include/asm-xtensa/pci.h b/include/asm-xtensa/pci.h
deleted file mode 100644
index 66410acf18b4..000000000000
--- a/include/asm-xtensa/pci.h
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * linux/include/asm-xtensa/pci.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PCI_H
12#define _XTENSA_PCI_H
13
14#ifdef __KERNEL__
15
16/* Can be used to override the logic in pci_scan_bus for skipping
17 * already-configured bus numbers - to be used for buggy BIOSes
18 * or architectures with incomplete PCI setup by the loader
19 */
20
21#define pcibios_assign_all_busses() 0
22
23extern struct pci_controller* pcibios_alloc_controller(void);
24
25static inline void pcibios_set_master(struct pci_dev *dev)
26{
27 /* No special bus mastering setup handling */
28}
29
30static inline void pcibios_penalize_isa_irq(int irq)
31{
32 /* We don't do dynamic PCI IRQ allocation */
33}
34
35/* Assume some values. (We should revise them, if necessary) */
36
37#define PCIBIOS_MIN_IO 0x2000
38#define PCIBIOS_MIN_MEM 0x10000000
39
40/* Dynamic DMA mapping stuff.
41 * Xtensa has everything mapped statically like x86.
42 */
43
44#include <linux/types.h>
45#include <linux/slab.h>
46#include <asm/scatterlist.h>
47#include <linux/string.h>
48#include <asm/io.h>
49
50struct pci_dev;
51
52/* The PCI address space does equal the physical memory address space.
53 * The networking and block device layers use this boolean for bounce buffer
54 * decisions.
55 */
56
57#define PCI_DMA_BUS_IS_PHYS (1)
58
59/* pci_unmap_{page,single} is a no-op, so */
60#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
61#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
62#define pci_unmap_addr(PTR, ADDR_NAME) (0)
63#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
64#define pci_ubnmap_len(PTR, LEN_NAME) (0)
65#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
66
67/* Map a range of PCI memory or I/O space for a device into user space */
68int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
69 enum pci_mmap_state mmap_state, int write_combine);
70
71/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
72#define HAVE_PCI_MMAP 1
73
74#endif /* __KERNEL__ */
75
76/* Implement the pci_ DMA API in terms of the generic device dma_ one */
77#include <asm-generic/pci-dma-compat.h>
78
79/* Generic PCI */
80#include <asm-generic/pci.h>
81
82#endif /* _XTENSA_PCI_H */
diff --git a/include/asm-xtensa/percpu.h b/include/asm-xtensa/percpu.h
deleted file mode 100644
index 6d2bc2ada9d1..000000000000
--- a/include/asm-xtensa/percpu.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * linux/include/asm-xtensa/percpu.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PERCPU__
12#define _XTENSA_PERCPU__
13
14#include <asm-generic/percpu.h>
15
16#endif /* _XTENSA_PERCPU__ */
diff --git a/include/asm-xtensa/pgalloc.h b/include/asm-xtensa/pgalloc.h
deleted file mode 100644
index 4f4a7987eded..000000000000
--- a/include/asm-xtensa/pgalloc.h
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * include/asm-xtensa/pgalloc.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001-2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PGALLOC_H
12#define _XTENSA_PGALLOC_H
13
14#ifdef __KERNEL__
15
16#include <linux/highmem.h>
17
18/*
19 * Allocating and freeing a pmd is trivial: the 1-entry pmd is
20 * inside the pgd, so has no extra memory associated with it.
21 */
22
23#define pmd_populate_kernel(mm, pmdp, ptep) \
24 (pmd_val(*(pmdp)) = ((unsigned long)ptep))
25#define pmd_populate(mm, pmdp, page) \
26 (pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page)))
27#define pmd_pgtable(pmd) pmd_page(pmd)
28
29static inline pgd_t*
30pgd_alloc(struct mm_struct *mm)
31{
32 return (pgd_t*) __get_free_pages(GFP_KERNEL | __GFP_ZERO, PGD_ORDER);
33}
34
35static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
36{
37 free_page((unsigned long)pgd);
38}
39
40/* Use a slab cache for the pte pages (see also sparc64 implementation) */
41
42extern struct kmem_cache *pgtable_cache;
43
44static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
45 unsigned long address)
46{
47 return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT);
48}
49
50static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
51 unsigned long addr)
52{
53 struct page *page;
54
55 page = virt_to_page(pte_alloc_one_kernel(mm, addr));
56 pgtable_page_ctor(page);
57 return page;
58}
59
60static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
61{
62 kmem_cache_free(pgtable_cache, pte);
63}
64
65static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
66{
67 pgtable_page_dtor(pte);
68 kmem_cache_free(pgtable_cache, page_address(pte));
69}
70#define pmd_pgtable(pmd) pmd_page(pmd)
71
72#endif /* __KERNEL__ */
73#endif /* _XTENSA_PGALLOC_H */
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
deleted file mode 100644
index 8014d96b21f1..000000000000
--- a/include/asm-xtensa/pgtable.h
+++ /dev/null
@@ -1,416 +0,0 @@
1/*
2 * include/asm-xtensa/pgtable.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PGTABLE_H
12#define _XTENSA_PGTABLE_H
13
14#include <asm-generic/pgtable-nopmd.h>
15#include <asm/page.h>
16
17/*
18 * We only use two ring levels, user and kernel space.
19 */
20
21#define USER_RING 1 /* user ring level */
22#define KERNEL_RING 0 /* kernel ring level */
23
24/*
25 * The Xtensa architecture port of Linux has a two-level page table system,
26 * i.e. the logical three-level Linux page table layout is folded.
27 * Each task has the following memory page tables:
28 *
29 * PGD table (page directory), ie. 3rd-level page table:
30 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
31 * (Architectures that don't have the PMD folded point to the PMD tables)
32 *
33 * The pointer to the PGD table for a given task can be retrieved from
34 * the task structure (struct task_struct*) t, e.g. current():
35 * (t->mm ? t->mm : t->active_mm)->pgd
36 *
37 * PMD tables (page middle-directory), ie. 2nd-level page tables:
38 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
39 *
40 * PTE tables (page table entry), ie. 1st-level page tables:
41 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
42 * invalid_pte_table for absent mappings.
43 *
44 * The individual pages are 4 kB big with special pages for the empty_zero_page.
45 */
46
47#define PGDIR_SHIFT 22
48#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
49#define PGDIR_MASK (~(PGDIR_SIZE-1))
50
51/*
52 * Entries per page directory level: we use two-level, so
53 * we don't really have any PMD directory physically.
54 */
55#define PTRS_PER_PTE 1024
56#define PTRS_PER_PTE_SHIFT 10
57#define PTRS_PER_PGD 1024
58#define PGD_ORDER 0
59#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
60#define FIRST_USER_ADDRESS 0
61#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
62
63/*
64 * Virtual memory area. We keep a distance to other memory regions to be
65 * on the safe side. We also use this area for cache aliasing.
66 */
67
68#define VMALLOC_START 0xC0000000
69#define VMALLOC_END 0xC7FEFFFF
70#define TLBTEMP_BASE_1 0xC7FF0000
71#define TLBTEMP_BASE_2 0xC7FF8000
72
73/*
74 * Xtensa Linux config PTE layout (when present):
75 * 31-12: PPN
76 * 11-6: Software
77 * 5-4: RING
78 * 3-0: CA
79 *
80 * Similar to the Alpha and MIPS ports, we need to keep track of the ref
81 * and mod bits in software. We have a software "you can read
82 * from this page" bit, and a hardware one which actually lets the
83 * process read from the page. On the same token we have a software
84 * writable bit and the real hardware one which actually lets the
85 * process write to the page.
86 *
87 * See further below for PTE layout for swapped-out pages.
88 */
89
90#define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
91#define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
92
93#define _PAGE_FILE (1<<1) /* non-linear mapping, if !present */
94#define _PAGE_PROTNONE (3<<0) /* special case for VM_PROT_NONE */
95
96/* None of these cache modes include MP coherency: */
97#define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
98#define _PAGE_CA_WB (1<<2) /* write-back */
99#define _PAGE_CA_WT (2<<2) /* write-through */
100#define _PAGE_CA_MASK (3<<2)
101#define _PAGE_INVALID (3<<2)
102
103#define _PAGE_USER (1<<4) /* user access (ring=1) */
104
105/* Software */
106#define _PAGE_WRITABLE_BIT 6
107#define _PAGE_WRITABLE (1<<6) /* software: page writable */
108#define _PAGE_DIRTY (1<<7) /* software: page dirty */
109#define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
110
111/* On older HW revisions, we always have to set bit 0 */
112#if XCHAL_HW_VERSION_MAJOR < 2000
113# define _PAGE_VALID (1<<0)
114#else
115# define _PAGE_VALID 0
116#endif
117
118#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
119#define _PAGE_PRESENT (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
120
121#ifdef CONFIG_MMU
122
123#define PAGE_NONE __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
124#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
125#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
126#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
127#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
128#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
129#define PAGE_SHARED_EXEC \
130 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
131#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
132#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
133
134#if (DCACHE_WAY_SIZE > PAGE_SIZE)
135# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
136#else
137# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
138#endif
139
140#else /* no mmu */
141
142# define PAGE_NONE __pgprot(0)
143# define PAGE_SHARED __pgprot(0)
144# define PAGE_COPY __pgprot(0)
145# define PAGE_READONLY __pgprot(0)
146# define PAGE_KERNEL __pgprot(0)
147
148#endif
149
150/*
151 * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
152 * the MMU can't do page protection for execute, and considers that the same as
153 * read. Also, write permissions may imply read permissions.
154 * What follows is the closest we can get by reasonable means..
155 * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
156 */
157#define __P000 PAGE_NONE /* private --- */
158#define __P001 PAGE_READONLY /* private --r */
159#define __P010 PAGE_COPY /* private -w- */
160#define __P011 PAGE_COPY /* private -wr */
161#define __P100 PAGE_READONLY_EXEC /* private x-- */
162#define __P101 PAGE_READONLY_EXEC /* private x-r */
163#define __P110 PAGE_COPY_EXEC /* private xw- */
164#define __P111 PAGE_COPY_EXEC /* private xwr */
165
166#define __S000 PAGE_NONE /* shared --- */
167#define __S001 PAGE_READONLY /* shared --r */
168#define __S010 PAGE_SHARED /* shared -w- */
169#define __S011 PAGE_SHARED /* shared -wr */
170#define __S100 PAGE_READONLY_EXEC /* shared x-- */
171#define __S101 PAGE_READONLY_EXEC /* shared x-r */
172#define __S110 PAGE_SHARED_EXEC /* shared xw- */
173#define __S111 PAGE_SHARED_EXEC /* shared xwr */
174
175#ifndef __ASSEMBLY__
176
177#define pte_ERROR(e) \
178 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
179#define pgd_ERROR(e) \
180 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
181
182extern unsigned long empty_zero_page[1024];
183
184#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
185
186extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
187
188/*
189 * The pmd contains the kernel virtual address of the pte page.
190 */
191#define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
192#define pmd_page(pmd) virt_to_page(pmd_val(pmd))
193
194/*
195 * pte status.
196 */
197#define pte_none(pte) (pte_val(pte) == _PAGE_INVALID)
198#define pte_present(pte) \
199 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID) \
200 || ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
201#define pte_clear(mm,addr,ptep) \
202 do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
203
204#define pmd_none(pmd) (!pmd_val(pmd))
205#define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
206#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
207#define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
208
209static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
210static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
211static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
212static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
213static inline int pte_special(pte_t pte) { return 0; }
214
215static inline pte_t pte_wrprotect(pte_t pte)
216 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
217static inline pte_t pte_mkclean(pte_t pte)
218 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
219static inline pte_t pte_mkold(pte_t pte)
220 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
221static inline pte_t pte_mkdirty(pte_t pte)
222 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
223static inline pte_t pte_mkyoung(pte_t pte)
224 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
225static inline pte_t pte_mkwrite(pte_t pte)
226 { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
227static inline pte_t pte_mkspecial(pte_t pte)
228 { return pte; }
229
230/*
231 * Conversion functions: convert a page and protection to a page entry,
232 * and a page entry and page directory to the page they refer to.
233 */
234
235#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
236#define pte_same(a,b) (pte_val(a) == pte_val(b))
237#define pte_page(x) pfn_to_page(pte_pfn(x))
238#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
239#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
240
241static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
242{
243 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
244}
245
246/*
247 * Certain architectures need to do special things when pte's
248 * within a page table are directly modified. Thus, the following
249 * hook is made available.
250 */
251static inline void update_pte(pte_t *ptep, pte_t pteval)
252{
253 *ptep = pteval;
254#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
255 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
256#endif
257
258}
259
260struct mm_struct;
261
262static inline void
263set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
264{
265 update_pte(ptep, pteval);
266}
267
268
269static inline void
270set_pmd(pmd_t *pmdp, pmd_t pmdval)
271{
272 *pmdp = pmdval;
273}
274
275struct vm_area_struct;
276
277static inline int
278ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
279 pte_t *ptep)
280{
281 pte_t pte = *ptep;
282 if (!pte_young(pte))
283 return 0;
284 update_pte(ptep, pte_mkold(pte));
285 return 1;
286}
287
288static inline pte_t
289ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
290{
291 pte_t pte = *ptep;
292 pte_clear(mm, addr, ptep);
293 return pte;
294}
295
296static inline void
297ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
298{
299 pte_t pte = *ptep;
300 update_pte(ptep, pte_wrprotect(pte));
301}
302
303/* to find an entry in a kernel page-table-directory */
304#define pgd_offset_k(address) pgd_offset(&init_mm, address)
305
306/* to find an entry in a page-table-directory */
307#define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address))
308
309#define pgd_index(address) ((address) >> PGDIR_SHIFT)
310
311/* Find an entry in the second-level page table.. */
312#define pmd_offset(dir,address) ((pmd_t*)(dir))
313
314/* Find an entry in the third-level page table.. */
315#define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
316#define pte_offset_kernel(dir,addr) \
317 ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
318#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))
319#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
320
321#define pte_unmap(pte) do { } while (0)
322#define pte_unmap_nested(pte) do { } while (0)
323
324
325/*
326 * Encode and decode a swap entry.
327 *
328 * Format of swap pte:
329 * bit 0 MBZ
330 * bit 1 page-file (must be zero)
331 * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
332 * bits 4 - 5 ring protection (must be 01: _PAGE_USER)
333 * bits 6 - 10 swap type (5 bits -> 32 types)
334 * bits 11 - 31 swap offset / PAGE_SIZE (21 bits -> 8GB)
335
336 * Format of file pte:
337 * bit 0 MBZ
338 * bit 1 page-file (must be one: _PAGE_FILE)
339 * bits 2 - 3 page hw access mode (must be 11: _PAGE_INVALID)
340 * bits 4 - 5 ring protection (must be 01: _PAGE_USER)
341 * bits 6 - 31 file offset / PAGE_SIZE
342 */
343
344#define __swp_type(entry) (((entry).val >> 6) & 0x1f)
345#define __swp_offset(entry) ((entry).val >> 11)
346#define __swp_entry(type,offs) \
347 ((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
348#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
349#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
350
351#define PTE_FILE_MAX_BITS 28
352#define pte_to_pgoff(pte) (pte_val(pte) >> 4)
353#define pgoff_to_pte(off) \
354 ((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })
355
356#endif /* !defined (__ASSEMBLY__) */
357
358
359#ifdef __ASSEMBLY__
360
361/* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
362 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
363 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
364 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
365 *
366 * Note: We require an additional temporary register which can be the same as
367 * the register that holds the address.
368 *
369 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
370 *
371 */
372#define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
373#define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
374
375#define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
376 _PGD_INDEX(tmp, adr); \
377 addx4 mm, tmp, mm
378
379#define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
380 srli pmd, pmd, PAGE_SHIFT; \
381 slli pmd, pmd, PAGE_SHIFT; \
382 addx4 pmd, tmp, pmd
383
384#else
385
386extern void paging_init(void);
387
388#define kern_addr_valid(addr) (1)
389
390extern void update_mmu_cache(struct vm_area_struct * vma,
391 unsigned long address, pte_t pte);
392
393/*
394 * remap a physical page `pfn' of size `size' with page protection `prot'
395 * into virtual address `from'
396 */
397
398#define io_remap_pfn_range(vma,from,pfn,size,prot) \
399 remap_pfn_range(vma, from, pfn, size, prot)
400
401
402extern void pgtable_cache_init(void);
403
404typedef pte_t *pte_addr_t;
405
406#endif /* !defined (__ASSEMBLY__) */
407
408#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
409#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
410#define __HAVE_ARCH_PTEP_SET_WRPROTECT
411#define __HAVE_ARCH_PTEP_MKDIRTY
412#define __HAVE_ARCH_PTE_SAME
413
414#include <asm-generic/pgtable.h>
415
416#endif /* _XTENSA_PGTABLE_H */
diff --git a/include/asm-xtensa/platform-iss/hardware.h b/include/asm-xtensa/platform-iss/hardware.h
deleted file mode 100644
index 6930c12adc16..000000000000
--- a/include/asm-xtensa/platform-iss/hardware.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * include/asm-xtensa/platform-iss/hardware.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Tensilica Inc.
9 */
10
11/*
12 * This file contains the default configuration of ISS.
13 */
14
15#ifndef _XTENSA_PLATFORM_ISS_HARDWARE_H
16#define _XTENSA_PLATFORM_ISS_HARDWARE_H
17
18/*
19 * Memory configuration.
20 */
21
22#define PLATFORM_DEFAULT_MEM_START 0x00000000
23#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
24
25/*
26 * Interrupt configuration.
27 */
28
29#endif /* _XTENSA_PLATFORM_ISS_HARDWARE_H */
diff --git a/include/asm-xtensa/platform-iss/simcall.h b/include/asm-xtensa/platform-iss/simcall.h
deleted file mode 100644
index b7952c06a2b7..000000000000
--- a/include/asm-xtensa/platform-iss/simcall.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * include/asm-xtensa/platform-iss/simcall.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PLATFORM_ISS_SIMCALL_H
12#define _XTENSA_PLATFORM_ISS_SIMCALL_H
13
14
15/*
16 * System call like services offered by the simulator host.
17 */
18
19#define SYS_nop 0 /* unused */
20#define SYS_exit 1 /*x*/
21#define SYS_fork 2
22#define SYS_read 3 /*x*/
23#define SYS_write 4 /*x*/
24#define SYS_open 5 /*x*/
25#define SYS_close 6 /*x*/
26#define SYS_rename 7 /*x 38 - waitpid */
27#define SYS_creat 8 /*x*/
28#define SYS_link 9 /*x (not implemented on WIN32) */
29#define SYS_unlink 10 /*x*/
30#define SYS_execv 11 /* n/a - execve */
31#define SYS_execve 12 /* 11 - chdir */
32#define SYS_pipe 13 /* 42 - time */
33#define SYS_stat 14 /* 106 - mknod */
34#define SYS_chmod 15
35#define SYS_chown 16 /* 202 - lchown */
36#define SYS_utime 17 /* 30 - break */
37#define SYS_wait 18 /* n/a - oldstat */
38#define SYS_lseek 19 /*x*/
39#define SYS_getpid 20
40#define SYS_isatty 21 /* n/a - mount */
41#define SYS_fstat 22 /* 108 - oldumount */
42#define SYS_time 23 /* 13 - setuid */
43#define SYS_gettimeofday 24 /*x 78 - getuid (not implemented on WIN32) */
44#define SYS_times 25 /*X 43 - stime (Xtensa-specific implementation) */
45#define SYS_socket 26
46#define SYS_sendto 27
47#define SYS_recvfrom 28
48#define SYS_select_one 29 /* not compitible select, one file descriptor at the time */
49#define SYS_bind 30
50#define SYS_ioctl 31
51
52/*
53 * SYS_select_one specifiers
54 */
55
56#define XTISS_SELECT_ONE_READ 1
57#define XTISS_SELECT_ONE_WRITE 2
58#define XTISS_SELECT_ONE_EXCEPT 3
59
60
61#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_H */
62
diff --git a/include/asm-xtensa/platform.h b/include/asm-xtensa/platform.h
deleted file mode 100644
index 48135a9718b0..000000000000
--- a/include/asm-xtensa/platform.h
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * include/asm-xtensa/platform.h
3 *
4 * Platform specific functions
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of
8 * this archive for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_PLATFORM_H
14#define _XTENSA_PLATFORM_H
15
16#include <linux/types.h>
17#include <linux/pci.h>
18
19#include <asm/bootparam.h>
20
21/*
22 * platform_init is called before the mmu is initialized to give the
23 * platform a early hook-up. bp_tag_t is a list of configuration tags
24 * passed from the boot-loader.
25 */
26extern void platform_init(bp_tag_t*);
27
28/*
29 * platform_setup is called from setup_arch with a pointer to the command-line
30 * string.
31 */
32extern void platform_setup (char **);
33
34/*
35 * platform_init_irq is called from init_IRQ.
36 */
37extern void platform_init_irq (void);
38
39/*
40 * platform_restart is called to restart the system.
41 */
42extern void platform_restart (void);
43
44/*
45 * platform_halt is called to stop the system and halt.
46 */
47extern void platform_halt (void);
48
49/*
50 * platform_power_off is called to stop the system and power it off.
51 */
52extern void platform_power_off (void);
53
54/*
55 * platform_idle is called from the idle function.
56 */
57extern void platform_idle (void);
58
59/*
60 * platform_heartbeat is called every HZ
61 */
62extern void platform_heartbeat (void);
63
64/*
65 * platform_pcibios_init is called to allow the platform to setup the pci bus.
66 */
67extern void platform_pcibios_init (void);
68
69/*
70 * platform_pcibios_fixup allows to modify the PCI configuration.
71 */
72extern int platform_pcibios_fixup (void);
73
74/*
75 * platform_calibrate_ccount calibrates cpu clock freq (CONFIG_XTENSA_CALIBRATE)
76 */
77extern void platform_calibrate_ccount (void);
78
79/*
80 * platform_get_rtc_time returns RTC seconds (returns 0 for no error)
81 */
82extern int platform_get_rtc_time(time_t*);
83
84/*
85 * platform_set_rtc_time set RTC seconds (returns 0 for no error)
86 */
87extern int platform_set_rtc_time(time_t);
88
89
90#endif /* _XTENSA_PLATFORM_H */
91
diff --git a/include/asm-xtensa/poll.h b/include/asm-xtensa/poll.h
deleted file mode 100644
index 9d2d5993f068..000000000000
--- a/include/asm-xtensa/poll.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * include/asm-xtensa/poll.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_POLL_H
12#define _XTENSA_POLL_H
13
14#define POLLWRNORM POLLOUT
15#define POLLWRBAND 0x0100
16#define POLLREMOVE 0x0800
17
18#include <asm-generic/poll.h>
19
20#endif /* _XTENSA_POLL_H */
diff --git a/include/asm-xtensa/posix_types.h b/include/asm-xtensa/posix_types.h
deleted file mode 100644
index 43f9dd1126a4..000000000000
--- a/include/asm-xtensa/posix_types.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * include/asm-xtensa/posix_types.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Largely copied from include/asm-ppc/posix_types.h
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_POSIX_TYPES_H
14#define _XTENSA_POSIX_TYPES_H
15
16/*
17 * This file is generally used by user-level software, so you need to
18 * be a little careful about namespace pollution etc. Also, we cannot
19 * assume GCC is being used.
20 */
21
22typedef unsigned long __kernel_ino_t;
23typedef unsigned int __kernel_mode_t;
24typedef unsigned long __kernel_nlink_t;
25typedef long __kernel_off_t;
26typedef int __kernel_pid_t;
27typedef unsigned short __kernel_ipc_pid_t;
28typedef unsigned int __kernel_uid_t;
29typedef unsigned int __kernel_gid_t;
30typedef unsigned int __kernel_size_t;
31typedef int __kernel_ssize_t;
32typedef long __kernel_ptrdiff_t;
33typedef long __kernel_time_t;
34typedef long __kernel_suseconds_t;
35typedef long __kernel_clock_t;
36typedef int __kernel_timer_t;
37typedef int __kernel_clockid_t;
38typedef int __kernel_daddr_t;
39typedef char * __kernel_caddr_t;
40typedef unsigned short __kernel_uid16_t;
41typedef unsigned short __kernel_gid16_t;
42typedef unsigned int __kernel_uid32_t;
43typedef unsigned int __kernel_gid32_t;
44
45typedef unsigned short __kernel_old_uid_t;
46typedef unsigned short __kernel_old_gid_t;
47typedef unsigned short __kernel_old_dev_t;
48
49#ifdef __GNUC__
50typedef long long __kernel_loff_t;
51#endif
52
53typedef struct {
54 int val[2];
55} __kernel_fsid_t;
56
57#ifndef __GNUC__
58
59#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
60#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
61#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
62#define __FD_ZERO(set) \
63 ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
64
65#else /* __GNUC__ */
66
67#if defined(__KERNEL__)
68/* With GNU C, use inline functions instead so args are evaluated only once: */
69
70#undef __FD_SET
71static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
72{
73 unsigned long _tmp = fd / __NFDBITS;
74 unsigned long _rem = fd % __NFDBITS;
75 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
76}
77
78#undef __FD_CLR
79static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
80{
81 unsigned long _tmp = fd / __NFDBITS;
82 unsigned long _rem = fd % __NFDBITS;
83 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
84}
85
86#undef __FD_ISSET
87static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
88{
89 unsigned long _tmp = fd / __NFDBITS;
90 unsigned long _rem = fd % __NFDBITS;
91 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
92}
93
94/*
95 * This will unroll the loop for the normal constant case (8 ints,
96 * for a 256-bit fd_set)
97 */
98#undef __FD_ZERO
99static __inline__ void __FD_ZERO(__kernel_fd_set *p)
100{
101 unsigned int *tmp = (unsigned int *)p->fds_bits;
102 int i;
103
104 if (__builtin_constant_p(__FDSET_LONGS)) {
105 switch (__FDSET_LONGS) {
106 case 8:
107 tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
108 tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
109 return;
110 }
111 }
112 i = __FDSET_LONGS;
113 while (i) {
114 i--;
115 *tmp = 0;
116 tmp++;
117 }
118}
119
120#endif /* defined(__KERNEL__) */
121#endif /* __GNUC__ */
122#endif /* _XTENSA_POSIX_TYPES_H */
diff --git a/include/asm-xtensa/processor.h b/include/asm-xtensa/processor.h
deleted file mode 100644
index 4918a4e96d42..000000000000
--- a/include/asm-xtensa/processor.h
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * include/asm-xtensa/processor.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PROCESSOR_H
12#define _XTENSA_PROCESSOR_H
13
14#include <asm/variant/core.h>
15#include <asm/coprocessor.h>
16
17#include <linux/compiler.h>
18#include <asm/ptrace.h>
19#include <asm/types.h>
20#include <asm/regs.h>
21
22/* Assertions. */
23
24#if (XCHAL_HAVE_WINDOWED != 1)
25# error Linux requires the Xtensa Windowed Registers Option.
26#endif
27
28/*
29 * User space process size: 1 GB.
30 * Windowed call ABI requires caller and callee to be located within the same
31 * 1 GB region. The C compiler places trampoline code on the stack for sources
32 * that take the address of a nested C function (a feature used by glibc), so
33 * the 1 GB requirement applies to the stack as well.
34 */
35
36#define TASK_SIZE __XTENSA_UL_CONST(0x40000000)
37#define STACK_TOP TASK_SIZE
38#define STACK_TOP_MAX STACK_TOP
39
40/*
41 * General exception cause assigned to debug exceptions. Debug exceptions go
42 * to their own vector, rather than the general exception vectors (user,
43 * kernel, double); and their specific causes are reported via DEBUGCAUSE
44 * rather than EXCCAUSE. However it is sometimes convenient to redirect debug
45 * exceptions to the general exception mechanism. To do this, an otherwise
46 * unused EXCCAUSE value was assigned to debug exceptions for this purpose.
47 */
48
49#define EXCCAUSE_MAPPED_DEBUG 63
50
51/*
52 * We use DEPC also as a flag to distinguish between double and regular
53 * exceptions. For performance reasons, DEPC might contain the value of
54 * EXCCAUSE for regular exceptions, so we use this definition to mark a
55 * valid double exception address.
56 * (Note: We use it in bgeui, so it should be 64, 128, or 256)
57 */
58
59#define VALID_DOUBLE_EXCEPTION_ADDRESS 64
60
61/* LOCKLEVEL defines the interrupt level that masks all
62 * general-purpose interrupts.
63 */
64#define LOCKLEVEL 1
65
66/* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE
67 * registers
68 */
69#define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */
70#define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */
71
72#ifndef __ASSEMBLY__
73
74/* Build a valid return address for the specified call winsize.
75 * winsize must be 1 (call4), 2 (call8), or 3 (call12)
76 */
77#define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30)
78
79/* Convert return address to a valid pc
80 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra
81 */
82#define MAKE_PC_FROM_RA(ra,sp) (((ra) & 0x3fffffff) | ((sp) & 0xc0000000))
83
84typedef struct {
85 unsigned long seg;
86} mm_segment_t;
87
88struct thread_struct {
89
90 /* kernel's return address and stack pointer for context switching */
91 unsigned long ra; /* kernel's a0: return address and window call size */
92 unsigned long sp; /* kernel's a1: stack pointer */
93
94 mm_segment_t current_ds; /* see uaccess.h for example uses */
95
96 /* struct xtensa_cpuinfo info; */
97
98 unsigned long bad_vaddr; /* last user fault */
99 unsigned long bad_uaddr; /* last kernel fault accessing user space */
100 unsigned long error_code;
101
102 unsigned long ibreak[XCHAL_NUM_IBREAK];
103 unsigned long dbreaka[XCHAL_NUM_DBREAK];
104 unsigned long dbreakc[XCHAL_NUM_DBREAK];
105
106 /* Make structure 16 bytes aligned. */
107 int align[0] __attribute__ ((aligned(16)));
108};
109
110
111/*
112 * Default implementation of macro that returns current
113 * instruction pointer ("program counter").
114 */
115#define current_text_addr() ({ __label__ _l; _l: &&_l;})
116
117
118/* This decides where the kernel will search for a free chunk of vm
119 * space during mmap's.
120 */
121#define TASK_UNMAPPED_BASE (TASK_SIZE / 2)
122
123#define INIT_THREAD \
124{ \
125 ra: 0, \
126 sp: sizeof(init_stack) + (long) &init_stack, \
127 current_ds: {0}, \
128 /*info: {0}, */ \
129 bad_vaddr: 0, \
130 bad_uaddr: 0, \
131 error_code: 0, \
132}
133
134
135/*
136 * Do necessary setup to start up a newly executed thread.
137 * Note: We set-up ps as if we did a call4 to the new pc.
138 * set_thread_state in signal.c depends on it.
139 */
140#define USER_PS_VALUE ((1 << PS_WOE_BIT) | \
141 (1 << PS_CALLINC_SHIFT) | \
142 (USER_RING << PS_RING_SHIFT) | \
143 (1 << PS_UM_BIT) | \
144 (1 << PS_EXCM_BIT))
145
146/* Clearing a0 terminates the backtrace. */
147#define start_thread(regs, new_pc, new_sp) \
148 regs->pc = new_pc; \
149 regs->ps = USER_PS_VALUE; \
150 regs->areg[1] = new_sp; \
151 regs->areg[0] = 0; \
152 regs->wmask = 1; \
153 regs->depc = 0; \
154 regs->windowbase = 0; \
155 regs->windowstart = 1;
156
157/* Forward declaration */
158struct task_struct;
159struct mm_struct;
160
161/* Free all resources held by a thread. */
162#define release_thread(thread) do { } while(0)
163
164/* Prepare to copy thread state - unlazy all lazy status */
165extern void prepare_to_copy(struct task_struct*);
166
167/* Create a kernel thread without removing it from tasklists */
168extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
169
170/* Copy and release all segment info associated with a VM */
171#define copy_segments(p, mm) do { } while(0)
172#define release_segments(mm) do { } while(0)
173#define forget_segments() do { } while (0)
174
175#define thread_saved_pc(tsk) (task_pt_regs(tsk)->pc)
176
177extern unsigned long get_wchan(struct task_struct *p);
178
179#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
180#define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1])
181
182#define cpu_relax() barrier()
183
184/* Special register access. */
185
186#define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
187#define RSR(v,sr) __asm__ __volatile__ ("rsr %0,"__stringify(sr) : "=a"(v));
188
189#define set_sr(x,sr) ({unsigned int v=(unsigned int)x; WSR(v,sr);})
190#define get_sr(sr) ({unsigned int v; RSR(v,sr); v; })
191
192#endif /* __ASSEMBLY__ */
193#endif /* _XTENSA_PROCESSOR_H */
diff --git a/include/asm-xtensa/ptrace.h b/include/asm-xtensa/ptrace.h
deleted file mode 100644
index 089b0db44816..000000000000
--- a/include/asm-xtensa/ptrace.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * include/asm-xtensa/ptrace.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PTRACE_H
12#define _XTENSA_PTRACE_H
13
14/*
15 * Kernel stack
16 *
17 * +-----------------------+ -------- STACK_SIZE
18 * | register file | |
19 * +-----------------------+ |
20 * | struct pt_regs | |
21 * +-----------------------+ | ------ PT_REGS_OFFSET
22 * double : 16 bytes spill area : | ^
23 * excetion :- - - - - - - - - - - -: | |
24 * frame : struct pt_regs : | |
25 * :- - - - - - - - - - - -: | |
26 * | | | |
27 * | memory stack | | |
28 * | | | |
29 * ~ ~ ~ ~
30 * ~ ~ ~ ~
31 * | | | |
32 * | | | |
33 * +-----------------------+ | | --- STACK_BIAS
34 * | struct task_struct | | | ^
35 * current --> +-----------------------+ | | |
36 * | struct thread_info | | | |
37 * +-----------------------+ --------
38 */
39
40#define KERNEL_STACK_SIZE (2 * PAGE_SIZE)
41
42/* Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables). */
43
44#define EXC_TABLE_KSTK 0x004 /* Kernel Stack */
45#define EXC_TABLE_DOUBLE_SAVE 0x008 /* Double exception save area for a0 */
46#define EXC_TABLE_FIXUP 0x00c /* Fixup handler */
47#define EXC_TABLE_PARAM 0x010 /* For passing a parameter to fixup */
48#define EXC_TABLE_SYSCALL_SAVE 0x014 /* For fast syscall handler */
49#define EXC_TABLE_FAST_USER 0x100 /* Fast user exception handler */
50#define EXC_TABLE_FAST_KERNEL 0x200 /* Fast kernel exception handler */
51#define EXC_TABLE_DEFAULT 0x300 /* Default C-Handler */
52#define EXC_TABLE_SIZE 0x400
53
54/* Registers used by strace */
55
56#define REG_A_BASE 0x0000
57#define REG_AR_BASE 0x0100
58#define REG_PC 0x0020
59#define REG_PS 0x02e6
60#define REG_WB 0x0248
61#define REG_WS 0x0249
62#define REG_LBEG 0x0200
63#define REG_LEND 0x0201
64#define REG_LCOUNT 0x0202
65#define REG_SAR 0x0203
66
67#define SYSCALL_NR 0x00ff
68
69/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */
70
71#define PTRACE_GETREGS 12
72#define PTRACE_SETREGS 13
73#define PTRACE_GETXTREGS 18
74#define PTRACE_SETXTREGS 19
75
76#ifdef __KERNEL__
77
78#ifndef __ASSEMBLY__
79
80/*
81 * This struct defines the way the registers are stored on the
82 * kernel stack during a system call or other kernel entry.
83 */
84struct pt_regs {
85 unsigned long pc; /* 4 */
86 unsigned long ps; /* 8 */
87 unsigned long depc; /* 12 */
88 unsigned long exccause; /* 16 */
89 unsigned long excvaddr; /* 20 */
90 unsigned long debugcause; /* 24 */
91 unsigned long wmask; /* 28 */
92 unsigned long lbeg; /* 32 */
93 unsigned long lend; /* 36 */
94 unsigned long lcount; /* 40 */
95 unsigned long sar; /* 44 */
96 unsigned long windowbase; /* 48 */
97 unsigned long windowstart; /* 52 */
98 unsigned long syscall; /* 56 */
99 unsigned long icountlevel; /* 60 */
100 int reserved[1]; /* 64 */
101
102 /* Additional configurable registers that are used by the compiler. */
103 xtregs_opt_t xtregs_opt;
104
105 /* Make sure the areg field is 16 bytes aligned. */
106 int align[0] __attribute__ ((aligned(16)));
107
108 /* current register frame.
109 * Note: The ESF for kernel exceptions ends after 16 registers!
110 */
111 unsigned long areg[16]; /* 128 (64) */
112};
113
114#include <asm/variant/core.h>
115
116# define task_pt_regs(tsk) ((struct pt_regs*) \
117 (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1)
118# define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
119# define instruction_pointer(regs) ((regs)->pc)
120extern void show_regs(struct pt_regs *);
121
122# ifndef CONFIG_SMP
123# define profile_pc(regs) instruction_pointer(regs)
124# endif
125
126#else /* __ASSEMBLY__ */
127
128# include <asm/asm-offsets.h>
129#define PT_REGS_OFFSET (KERNEL_STACK_SIZE - PT_USER_SIZE)
130
131#endif /* !__ASSEMBLY__ */
132
133#endif /* __KERNEL__ */
134
135#endif /* _XTENSA_PTRACE_H */
diff --git a/include/asm-xtensa/regs.h b/include/asm-xtensa/regs.h
deleted file mode 100644
index d4baed246928..000000000000
--- a/include/asm-xtensa/regs.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of version 2.1 of the GNU Lesser General Public
6 * License as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * Further, this software is distributed without any warranty that it is
13 * free of the rightful claim of any third person regarding infringement
14 * or the like. Any license provided herein, whether implied or
15 * otherwise, applies only to this software file. Patent licenses, if
16 * any, provided herein do not apply to combinations of this program with
17 * other software, or any other product whatsoever.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this program; if not, write the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
22 * USA.
23 */
24
25#ifndef _XTENSA_REGS_H
26#define _XTENSA_REGS_H
27
28/* Special registers. */
29
30#define LBEG 0
31#define LEND 1
32#define LCOUNT 2
33#define SAR 3
34#define BR 4
35#define SCOMPARE1 12
36#define ACCHI 16
37#define ACCLO 17
38#define MR 32
39#define WINDOWBASE 72
40#define WINDOWSTART 73
41#define PTEVADDR 83
42#define RASID 90
43#define ITLBCFG 91
44#define DTLBCFG 92
45#define IBREAKENABLE 96
46#define DDR 104
47#define IBREAKA 128
48#define DBREAKA 144
49#define DBREAKC 160
50#define EPC 176
51#define EPC_1 177
52#define DEPC 192
53#define EPS 192
54#define EPS_1 193
55#define EXCSAVE 208
56#define EXCSAVE_1 209
57#define INTERRUPT 226
58#define INTENABLE 228
59#define PS 230
60#define THREADPTR 231
61#define EXCCAUSE 232
62#define DEBUGCAUSE 233
63#define CCOUNT 234
64#define PRID 235
65#define ICOUNT 236
66#define ICOUNTLEVEL 237
67#define EXCVADDR 238
68#define CCOMPARE 240
69#define MISC 244
70
71/* Special names for read-only and write-only interrupt registers. */
72
73#define INTREAD 226
74#define INTSET 226
75#define INTCLEAR 227
76
77/* EXCCAUSE register fields */
78
79#define EXCCAUSE_EXCCAUSE_SHIFT 0
80#define EXCCAUSE_EXCCAUSE_MASK 0x3F
81
82#define EXCCAUSE_ILLEGAL_INSTRUCTION 0
83#define EXCCAUSE_SYSTEM_CALL 1
84#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
85#define EXCCAUSE_LOAD_STORE_ERROR 3
86#define EXCCAUSE_LEVEL1_INTERRUPT 4
87#define EXCCAUSE_ALLOCA 5
88#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
89#define EXCCAUSE_SPECULATION 7
90#define EXCCAUSE_PRIVILEGED 8
91#define EXCCAUSE_UNALIGNED 9
92#define EXCCAUSE_ITLB_MISS 16
93#define EXCCAUSE_ITLB_MULTIHIT 17
94#define EXCCAUSE_ITLB_PRIVILEGE 18
95#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
96#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
97#define EXCCAUSE_DTLB_MISS 24
98#define EXCCAUSE_DTLB_MULTIHIT 25
99#define EXCCAUSE_DTLB_PRIVILEGE 26
100#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
101#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
102#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
103#define EXCCAUSE_COPROCESSOR0_DISABLED 32
104#define EXCCAUSE_COPROCESSOR1_DISABLED 33
105#define EXCCAUSE_COPROCESSOR2_DISABLED 34
106#define EXCCAUSE_COPROCESSOR3_DISABLED 35
107#define EXCCAUSE_COPROCESSOR4_DISABLED 36
108#define EXCCAUSE_COPROCESSOR5_DISABLED 37
109#define EXCCAUSE_COPROCESSOR6_DISABLED 38
110#define EXCCAUSE_COPROCESSOR7_DISABLED 39
111
112/* PS register fields. */
113
114#define PS_WOE_BIT 18
115#define PS_CALLINC_SHIFT 16
116#define PS_CALLINC_MASK 0x00030000
117#define PS_OWB_SHIFT 8
118#define PS_OWB_MASK 0x00000F00
119#define PS_RING_SHIFT 6
120#define PS_RING_MASK 0x000000C0
121#define PS_UM_BIT 5
122#define PS_EXCM_BIT 4
123#define PS_INTLEVEL_SHIFT 0
124#define PS_INTLEVEL_MASK 0x0000000F
125
126/* DBREAKCn register fields. */
127
128#define DBREAKC_MASK_BIT 0
129#define DBREAKC_MASK_MASK 0x0000003F
130#define DBREAKC_LOAD_BIT 30
131#define DBREAKC_LOAD_MASK 0x40000000
132#define DBREAKC_STOR_BIT 31
133#define DBREAKC_STOR_MASK 0x80000000
134
135/* DEBUGCAUSE register fields. */
136
137#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
138#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
139#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
140#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
141#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
142#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
143
144#endif /* _XTENSA_SPECREG_H */
145
diff --git a/include/asm-xtensa/resource.h b/include/asm-xtensa/resource.h
deleted file mode 100644
index 17b5ab311771..000000000000
--- a/include/asm-xtensa/resource.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/resource.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_RESOURCE_H
12#define _XTENSA_RESOURCE_H
13
14#include <asm-generic/resource.h>
15
16#endif /* _XTENSA_RESOURCE_H */
diff --git a/include/asm-xtensa/rmap.h b/include/asm-xtensa/rmap.h
deleted file mode 100644
index 649588b7e9ad..000000000000
--- a/include/asm-xtensa/rmap.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/rmap.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_RMAP_H
12#define _XTENSA_RMAP_H
13
14#include <asm-generic/rmap.h>
15
16#endif
diff --git a/include/asm-xtensa/rwsem.h b/include/asm-xtensa/rwsem.h
deleted file mode 100644
index e39edf5c86f2..000000000000
--- a/include/asm-xtensa/rwsem.h
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * include/asm-xtensa/rwsem.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Largely copied from include/asm-ppc/rwsem.h
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_RWSEM_H
14#define _XTENSA_RWSEM_H
15
16#ifndef _LINUX_RWSEM_H
17#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
18#endif
19
20#include <linux/list.h>
21#include <linux/spinlock.h>
22#include <asm/atomic.h>
23#include <asm/system.h>
24
25/*
26 * the semaphore definition
27 */
28struct rw_semaphore {
29 signed long count;
30#define RWSEM_UNLOCKED_VALUE 0x00000000
31#define RWSEM_ACTIVE_BIAS 0x00000001
32#define RWSEM_ACTIVE_MASK 0x0000ffff
33#define RWSEM_WAITING_BIAS (-0x00010000)
34#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
35#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
36 spinlock_t wait_lock;
37 struct list_head wait_list;
38};
39
40#define __RWSEM_INITIALIZER(name) \
41 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
42 LIST_HEAD_INIT((name).wait_list) }
43
44#define DECLARE_RWSEM(name) \
45 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
46
47extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
48extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
49extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
50extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
51
52static inline void init_rwsem(struct rw_semaphore *sem)
53{
54 sem->count = RWSEM_UNLOCKED_VALUE;
55 spin_lock_init(&sem->wait_lock);
56 INIT_LIST_HEAD(&sem->wait_list);
57}
58
59/*
60 * lock for reading
61 */
62static inline void __down_read(struct rw_semaphore *sem)
63{
64 if (atomic_add_return(1,(atomic_t *)(&sem->count)) > 0)
65 smp_wmb();
66 else
67 rwsem_down_read_failed(sem);
68}
69
70static inline int __down_read_trylock(struct rw_semaphore *sem)
71{
72 int tmp;
73
74 while ((tmp = sem->count) >= 0) {
75 if (tmp == cmpxchg(&sem->count, tmp,
76 tmp + RWSEM_ACTIVE_READ_BIAS)) {
77 smp_wmb();
78 return 1;
79 }
80 }
81 return 0;
82}
83
84/*
85 * lock for writing
86 */
87static inline void __down_write(struct rw_semaphore *sem)
88{
89 int tmp;
90
91 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
92 (atomic_t *)(&sem->count));
93 if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
94 smp_wmb();
95 else
96 rwsem_down_write_failed(sem);
97}
98
99static inline int __down_write_trylock(struct rw_semaphore *sem)
100{
101 int tmp;
102
103 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
104 RWSEM_ACTIVE_WRITE_BIAS);
105 smp_wmb();
106 return tmp == RWSEM_UNLOCKED_VALUE;
107}
108
109/*
110 * unlock after reading
111 */
112static inline void __up_read(struct rw_semaphore *sem)
113{
114 int tmp;
115
116 smp_wmb();
117 tmp = atomic_sub_return(1,(atomic_t *)(&sem->count));
118 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
119 rwsem_wake(sem);
120}
121
122/*
123 * unlock after writing
124 */
125static inline void __up_write(struct rw_semaphore *sem)
126{
127 smp_wmb();
128 if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
129 (atomic_t *)(&sem->count)) < 0)
130 rwsem_wake(sem);
131}
132
133/*
134 * implement atomic add functionality
135 */
136static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
137{
138 atomic_add(delta, (atomic_t *)(&sem->count));
139}
140
141/*
142 * downgrade write lock to read lock
143 */
144static inline void __downgrade_write(struct rw_semaphore *sem)
145{
146 int tmp;
147
148 smp_wmb();
149 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
150 if (tmp < 0)
151 rwsem_downgrade_wake(sem);
152}
153
154/*
155 * implement exchange and add functionality
156 */
157static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
158{
159 smp_mb();
160 return atomic_add_return(delta, (atomic_t *)(&sem->count));
161}
162
163static inline int rwsem_is_locked(struct rw_semaphore *sem)
164{
165 return (sem->count != 0);
166}
167
168#endif /* _XTENSA_RWSEM_H */
diff --git a/include/asm-xtensa/scatterlist.h b/include/asm-xtensa/scatterlist.h
deleted file mode 100644
index 810080bb0a2b..000000000000
--- a/include/asm-xtensa/scatterlist.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * include/asm-xtensa/scatterlist.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SCATTERLIST_H
12#define _XTENSA_SCATTERLIST_H
13
14#include <asm/types.h>
15
16struct scatterlist {
17#ifdef CONFIG_DEBUG_SG
18 unsigned long sg_magic;
19#endif
20 unsigned long page_link;
21 unsigned int offset;
22 dma_addr_t dma_address;
23 unsigned int length;
24};
25
26/*
27 * These macros should be used after a pci_map_sg call has been done
28 * to get bus addresses of each of the SG entries and their lengths.
29 * You should only work with the number of sg entries pci_map_sg
30 * returns, or alternatively stop on the first sg_dma_len(sg) which
31 * is 0.
32 */
33#define sg_dma_address(sg) ((sg)->dma_address)
34#define sg_dma_len(sg) ((sg)->length)
35
36
37#define ISA_DMA_THRESHOLD (~0UL)
38
39#endif /* _XTENSA_SCATTERLIST_H */
diff --git a/include/asm-xtensa/sections.h b/include/asm-xtensa/sections.h
deleted file mode 100644
index 40b5191b55a2..000000000000
--- a/include/asm-xtensa/sections.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/sections.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SECTIONS_H
12#define _XTENSA_SECTIONS_H
13
14#include <asm-generic/sections.h>
15
16#endif /* _XTENSA_SECTIONS_H */
diff --git a/include/asm-xtensa/segment.h b/include/asm-xtensa/segment.h
deleted file mode 100644
index a2eb547a1a75..000000000000
--- a/include/asm-xtensa/segment.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/segment.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SEGMENT_H
12#define _XTENSA_SEGMENT_H
13
14#include <asm/uaccess.h>
15
16#endif /* _XTENSA_SEGEMENT_H */
diff --git a/include/asm-xtensa/sembuf.h b/include/asm-xtensa/sembuf.h
deleted file mode 100644
index c15870493b33..000000000000
--- a/include/asm-xtensa/sembuf.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-xtensa/sembuf.h
3 *
4 * The semid64_ds structure for Xtensa architecture.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 *
12 * Note extra padding because this structure is passed back and forth
13 * between kernel and user space.
14 *
15 * Pad space is left for:
16 * - 64-bit time_t to solve y2038 problem
17 * - 2 miscellaneous 32-bit values
18 *
19 */
20
21#ifndef _XTENSA_SEMBUF_H
22#define _XTENSA_SEMBUF_H
23
24#include <asm/byteorder.h>
25
26struct semid64_ds {
27 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
28#ifdef __XTENSA_EL__
29 __kernel_time_t sem_otime; /* last semop time */
30 unsigned long __unused1;
31 __kernel_time_t sem_ctime; /* last change time */
32 unsigned long __unused2;
33#else
34 unsigned long __unused1;
35 __kernel_time_t sem_otime; /* last semop time */
36 unsigned long __unused2;
37 __kernel_time_t sem_ctime; /* last change time */
38#endif
39 unsigned long sem_nsems; /* no. of semaphores in array */
40 unsigned long __unused3;
41 unsigned long __unused4;
42};
43
44#endif /* __ASM_XTENSA_SEMBUF_H */
diff --git a/include/asm-xtensa/serial.h b/include/asm-xtensa/serial.h
deleted file mode 100644
index ec04114fcf0b..000000000000
--- a/include/asm-xtensa/serial.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * include/asm-xtensa/serial.h
3 *
4 * Configuration details for 8250, 16450, 16550, etc. serial ports
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_SERIAL_H
14#define _XTENSA_SERIAL_H
15
16#include <asm/platform/serial.h>
17
18#endif /* _XTENSA_SERIAL_H */
diff --git a/include/asm-xtensa/setup.h b/include/asm-xtensa/setup.h
deleted file mode 100644
index e3636520d8cc..000000000000
--- a/include/asm-xtensa/setup.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/setup.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SETUP_H
12#define _XTENSA_SETUP_H
13
14#define COMMAND_LINE_SIZE 256
15
16#endif
diff --git a/include/asm-xtensa/shmbuf.h b/include/asm-xtensa/shmbuf.h
deleted file mode 100644
index ad4b0121782c..000000000000
--- a/include/asm-xtensa/shmbuf.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * include/asm-xtensa/shmbuf.h
3 *
4 * The shmid64_ds structure for Xtensa architecture.
5 * Note extra padding because this structure is passed back and forth
6 * between kernel and user space.
7 *
8 * Pad space is left for:
9 * - 64-bit time_t to solve y2038 problem
10 * - 2 miscellaneous 32-bit values
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 *
16 * Copyright (C) 2001 - 2005 Tensilica Inc.
17 */
18
19#ifndef _XTENSA_SHMBUF_H
20#define _XTENSA_SHMBUF_H
21
22#if defined (__XTENSA_EL__)
23struct shmid64_ds {
24 struct ipc64_perm shm_perm; /* operation perms */
25 size_t shm_segsz; /* size of segment (bytes) */
26 __kernel_time_t shm_atime; /* last attach time */
27 unsigned long __unused1;
28 __kernel_time_t shm_dtime; /* last detach time */
29 unsigned long __unused2;
30 __kernel_time_t shm_ctime; /* last change time */
31 unsigned long __unused3;
32 __kernel_pid_t shm_cpid; /* pid of creator */
33 __kernel_pid_t shm_lpid; /* pid of last operator */
34 unsigned long shm_nattch; /* no. of current attaches */
35 unsigned long __unused4;
36 unsigned long __unused5;
37};
38#elif defined (__XTENSA_EB__)
39struct shmid64_ds {
40 struct ipc64_perm shm_perm; /* operation perms */
41 size_t shm_segsz; /* size of segment (bytes) */
42 __kernel_time_t shm_atime; /* last attach time */
43 unsigned long __unused1;
44 __kernel_time_t shm_dtime; /* last detach time */
45 unsigned long __unused2;
46 __kernel_time_t shm_ctime; /* last change time */
47 unsigned long __unused3;
48 __kernel_pid_t shm_cpid; /* pid of creator */
49 __kernel_pid_t shm_lpid; /* pid of last operator */
50 unsigned long shm_nattch; /* no. of current attaches */
51 unsigned long __unused4;
52 unsigned long __unused5;
53};
54#else
55# error endian order not defined
56#endif
57
58
59struct shminfo64 {
60 unsigned long shmmax;
61 unsigned long shmmin;
62 unsigned long shmmni;
63 unsigned long shmseg;
64 unsigned long shmall;
65 unsigned long __unused1;
66 unsigned long __unused2;
67 unsigned long __unused3;
68 unsigned long __unused4;
69};
70
71#endif /* _XTENSA_SHMBUF_H */
diff --git a/include/asm-xtensa/shmparam.h b/include/asm-xtensa/shmparam.h
deleted file mode 100644
index c8cc16c3da9e..000000000000
--- a/include/asm-xtensa/shmparam.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * include/asm-xtensa/shmparam.h
3 *
4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of
6 * this archive for more details.
7 */
8
9#ifndef _XTENSA_SHMPARAM_H
10#define _XTENSA_SHMPARAM_H
11
12/*
13 * Xtensa can have variable size caches, and if
14 * the size of single way is larger than the page size,
15 * then we have to start worrying about cache aliasing
16 * problems.
17 */
18
19#define SHMLBA ((PAGE_SIZE > DCACHE_WAY_SIZE)? PAGE_SIZE : DCACHE_WAY_SIZE)
20
21#endif /* _XTENSA_SHMPARAM_H */
diff --git a/include/asm-xtensa/sigcontext.h b/include/asm-xtensa/sigcontext.h
deleted file mode 100644
index 03383af8c3b7..000000000000
--- a/include/asm-xtensa/sigcontext.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * include/asm-xtensa/sigcontext.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SIGCONTEXT_H
12#define _XTENSA_SIGCONTEXT_H
13
14
15struct sigcontext {
16 unsigned long sc_pc;
17 unsigned long sc_ps;
18 unsigned long sc_lbeg;
19 unsigned long sc_lend;
20 unsigned long sc_lcount;
21 unsigned long sc_sar;
22 unsigned long sc_acclo;
23 unsigned long sc_acchi;
24 unsigned long sc_a[16];
25 void *sc_xtregs;
26};
27
28#endif /* _XTENSA_SIGCONTEXT_H */
diff --git a/include/asm-xtensa/siginfo.h b/include/asm-xtensa/siginfo.h
deleted file mode 100644
index 6916248295df..000000000000
--- a/include/asm-xtensa/siginfo.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/siginfo.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SIGINFO_H
12#define _XTENSA_SIGINFO_H
13
14#include <asm-generic/siginfo.h>
15
16#endif /* _XTENSA_SIGINFO_H */
diff --git a/include/asm-xtensa/signal.h b/include/asm-xtensa/signal.h
deleted file mode 100644
index 633ba73bc4d2..000000000000
--- a/include/asm-xtensa/signal.h
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * include/asm-xtensa/signal.h
3 *
4 * Swiped from SH.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_SIGNAL_H
14#define _XTENSA_SIGNAL_H
15
16
17#define _NSIG 64
18#define _NSIG_BPW 32
19#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
20
21#ifndef __ASSEMBLY__
22
23#include <linux/types.h>
24
25/* Avoid too many header ordering problems. */
26struct siginfo;
27typedef unsigned long old_sigset_t; /* at least 32 bits */
28typedef struct {
29 unsigned long sig[_NSIG_WORDS];
30} sigset_t;
31
32#endif
33
34#define SIGHUP 1
35#define SIGINT 2
36#define SIGQUIT 3
37#define SIGILL 4
38#define SIGTRAP 5
39#define SIGABRT 6
40#define SIGIOT 6
41#define SIGBUS 7
42#define SIGFPE 8
43#define SIGKILL 9
44#define SIGUSR1 10
45#define SIGSEGV 11
46#define SIGUSR2 12
47#define SIGPIPE 13
48#define SIGALRM 14
49#define SIGTERM 15
50#define SIGSTKFLT 16
51#define SIGCHLD 17
52#define SIGCONT 18
53#define SIGSTOP 19
54#define SIGTSTP 20
55#define SIGTTIN 21
56#define SIGTTOU 22
57#define SIGURG 23
58#define SIGXCPU 24
59#define SIGXFSZ 25
60#define SIGVTALRM 26
61#define SIGPROF 27
62#define SIGWINCH 28
63#define SIGIO 29
64#define SIGPOLL SIGIO
65/* #define SIGLOST 29 */
66#define SIGPWR 30
67#define SIGSYS 31
68#define SIGUNUSED 31
69
70/* These should not be considered constants from userland. */
71#define SIGRTMIN 32
72#define SIGRTMAX (_NSIG-1)
73
74/*
75 * SA_FLAGS values:
76 *
77 * SA_ONSTACK indicates that a registered stack_t will be used.
78 * SA_RESTART flag to get restarting signals (which were the default long ago)
79 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
80 * SA_RESETHAND clears the handler when the signal is delivered.
81 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
82 * SA_NODEFER prevents the current signal from being masked in the handler.
83 *
84 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
85 * Unix names RESETHAND and NODEFER respectively.
86 */
87#define SA_NOCLDSTOP 0x00000001
88#define SA_NOCLDWAIT 0x00000002 /* not supported yet */
89#define SA_SIGINFO 0x00000004
90#define SA_ONSTACK 0x08000000
91#define SA_RESTART 0x10000000
92#define SA_NODEFER 0x40000000
93#define SA_RESETHAND 0x80000000
94
95#define SA_NOMASK SA_NODEFER
96#define SA_ONESHOT SA_RESETHAND
97
98#define SA_RESTORER 0x04000000
99
100/*
101 * sigaltstack controls
102 */
103#define SS_ONSTACK 1
104#define SS_DISABLE 2
105
106#define MINSIGSTKSZ 2048
107#define SIGSTKSZ 8192
108
109#ifndef __ASSEMBLY__
110
111#define SIG_BLOCK 0 /* for blocking signals */
112#define SIG_UNBLOCK 1 /* for unblocking signals */
113#define SIG_SETMASK 2 /* for setting the signal mask */
114
115/* Type of a signal handler. */
116typedef void (*__sighandler_t)(int);
117
118#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
119#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
120#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
121
122#ifdef __KERNEL__
123struct old_sigaction {
124 __sighandler_t sa_handler;
125 old_sigset_t sa_mask;
126 unsigned long sa_flags;
127 void (*sa_restorer)(void);
128};
129
130struct sigaction {
131 __sighandler_t sa_handler;
132 unsigned long sa_flags;
133 void (*sa_restorer)(void);
134 sigset_t sa_mask; /* mask last for extensibility */
135};
136
137struct k_sigaction {
138 struct sigaction sa;
139};
140
141#else
142
143/* Here we must cater to libcs that poke about in kernel headers. */
144
145struct sigaction {
146 union {
147 __sighandler_t _sa_handler;
148 void (*_sa_sigaction)(int, struct siginfo *, void *);
149 } _u;
150 sigset_t sa_mask;
151 unsigned long sa_flags;
152 void (*sa_restorer)(void);
153};
154
155#define sa_handler _u._sa_handler
156#define sa_sigaction _u._sa_sigaction
157
158#endif /* __KERNEL__ */
159
160typedef struct sigaltstack {
161 void *ss_sp;
162 int ss_flags;
163 size_t ss_size;
164} stack_t;
165
166#ifdef __KERNEL__
167#include <asm/sigcontext.h>
168#define ptrace_signal_deliver(regs, cookie) do { } while (0)
169
170#endif /* __KERNEL__ */
171#endif /* __ASSEMBLY__ */
172#endif /* _XTENSA_SIGNAL_H */
diff --git a/include/asm-xtensa/smp.h b/include/asm-xtensa/smp.h
deleted file mode 100644
index 83c569e3bdbd..000000000000
--- a/include/asm-xtensa/smp.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * include/asm-xtensa/smp.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SMP_H
12#define _XTENSA_SMP_H
13
14extern struct xtensa_cpuinfo boot_cpu_data;
15
16#define cpu_data (&boot_cpu_data)
17#define current_cpu_data boot_cpu_data
18
19struct xtensa_cpuinfo {
20 unsigned long *pgd_cache;
21 unsigned long *pte_cache;
22 unsigned long pgtable_cache_sz;
23};
24
25#define cpu_logical_map(cpu) (cpu)
26
27#endif /* _XTENSA_SMP_H */
diff --git a/include/asm-xtensa/socket.h b/include/asm-xtensa/socket.h
deleted file mode 100644
index 6100682b1da2..000000000000
--- a/include/asm-xtensa/socket.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * include/asm-xtensa/socket.h
3 *
4 * Copied from i386.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef _XTENSA_SOCKET_H
12#define _XTENSA_SOCKET_H
13
14#include <asm/sockios.h>
15
16/* For setsockoptions(2) */
17#define SOL_SOCKET 1
18
19#define SO_DEBUG 1
20#define SO_REUSEADDR 2
21#define SO_TYPE 3
22#define SO_ERROR 4
23#define SO_DONTROUTE 5
24#define SO_BROADCAST 6
25#define SO_SNDBUF 7
26#define SO_RCVBUF 8
27#define SO_SNDBUFFORCE 32
28#define SO_RCVBUFFORCE 33
29#define SO_KEEPALIVE 9
30#define SO_OOBINLINE 10
31#define SO_NO_CHECK 11
32#define SO_PRIORITY 12
33#define SO_LINGER 13
34#define SO_BSDCOMPAT 14
35/* To add :#define SO_REUSEPORT 15 */
36#define SO_PASSCRED 16
37#define SO_PEERCRED 17
38#define SO_RCVLOWAT 18
39#define SO_SNDLOWAT 19
40#define SO_RCVTIMEO 20
41#define SO_SNDTIMEO 21
42
43/* Security levels - as per NRL IPv6 - don't actually do anything */
44
45#define SO_SECURITY_AUTHENTICATION 22
46#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
47#define SO_SECURITY_ENCRYPTION_NETWORK 24
48
49#define SO_BINDTODEVICE 25
50
51/* Socket filtering */
52
53#define SO_ATTACH_FILTER 26
54#define SO_DETACH_FILTER 27
55
56#define SO_PEERNAME 28
57#define SO_TIMESTAMP 29
58#define SCM_TIMESTAMP SO_TIMESTAMP
59
60#define SO_ACCEPTCONN 30
61#define SO_PEERSEC 31
62#define SO_PASSSEC 34
63#define SO_TIMESTAMPNS 35
64#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
65
66#define SO_MARK 36
67
68#endif /* _XTENSA_SOCKET_H */
diff --git a/include/asm-xtensa/sockios.h b/include/asm-xtensa/sockios.h
deleted file mode 100644
index efe0af379f01..000000000000
--- a/include/asm-xtensa/sockios.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * include/asm-xtensa/sockios.h
3 *
4 * Socket-level I/O control calls. Copied from MIPS.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1995 by Ralf Baechle
11 * Copyright (C) 2001 Tensilica Inc.
12 */
13
14#ifndef _XTENSA_SOCKIOS_H
15#define _XTENSA_SOCKIOS_H
16
17#include <asm/ioctl.h>
18
19/* Socket-level I/O control calls. */
20
21#define FIOGETOWN _IOR('f', 123, int)
22#define FIOSETOWN _IOW('f', 124, int)
23
24#define SIOCATMARK _IOR('s', 7, int)
25#define SIOCSPGRP _IOW('s', 8, pid_t)
26#define SIOCGPGRP _IOR('s', 9, pid_t)
27
28#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
29#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
30
31#endif /* _XTENSA_SOCKIOS_H */
diff --git a/include/asm-xtensa/spinlock.h b/include/asm-xtensa/spinlock.h
deleted file mode 100644
index 8ff23649581b..000000000000
--- a/include/asm-xtensa/spinlock.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/spinlock.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SPINLOCK_H
12#define _XTENSA_SPINLOCK_H
13
14#include <linux/spinlock.h>
15
16#endif /* _XTENSA_SPINLOCK_H */
diff --git a/include/asm-xtensa/stat.h b/include/asm-xtensa/stat.h
deleted file mode 100644
index c4992038cee0..000000000000
--- a/include/asm-xtensa/stat.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * include/asm-xtensa/stat.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_STAT_H
12#define _XTENSA_STAT_H
13
14#define STAT_HAVE_NSEC 1
15
16struct stat {
17 unsigned long st_dev;
18 unsigned long st_ino;
19 unsigned int st_mode;
20 unsigned int st_nlink;
21 unsigned int st_uid;
22 unsigned int st_gid;
23 unsigned long st_rdev;
24 long st_size;
25 unsigned long st_blksize;
26 unsigned long st_blocks;
27 unsigned long st_atime;
28 unsigned long st_atime_nsec;
29 unsigned long st_mtime;
30 unsigned long st_mtime_nsec;
31 unsigned long st_ctime;
32 unsigned long st_ctime_nsec;
33 unsigned long __unused4;
34 unsigned long __unused5;
35};
36
37struct stat64 {
38 unsigned long long st_dev; /* Device */
39 unsigned long long st_ino; /* File serial number */
40 unsigned int st_mode; /* File mode. */
41 unsigned int st_nlink; /* Link count. */
42 unsigned int st_uid; /* User ID of the file's owner. */
43 unsigned int st_gid; /* Group ID of the file's group. */
44 unsigned long long st_rdev; /* Device number, if device. */
45 long long st_size; /* Size of file, in bytes. */
46 unsigned long st_blksize; /* Optimal block size for I/O. */
47 unsigned long __unused2;
48 unsigned long long st_blocks; /* Number 512-byte blocks allocated. */
49 unsigned long st_atime; /* Time of last access. */
50 unsigned long st_atime_nsec;
51 unsigned long st_mtime; /* Time of last modification. */
52 unsigned long st_mtime_nsec;
53 unsigned long st_ctime; /* Time of last status change. */
54 unsigned long st_ctime_nsec;
55 unsigned long __unused4;
56 unsigned long __unused5;
57};
58
59#endif /* _XTENSA_STAT_H */
diff --git a/include/asm-xtensa/statfs.h b/include/asm-xtensa/statfs.h
deleted file mode 100644
index 9c3d1a213136..000000000000
--- a/include/asm-xtensa/statfs.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * include/asm-xtensa/statfs.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_STATFS_H
12#define _XTENSA_STATFS_H
13
14#include <asm-generic/statfs.h>
15
16#endif /* _XTENSA_STATFS_H */
17
diff --git a/include/asm-xtensa/string.h b/include/asm-xtensa/string.h
deleted file mode 100644
index 5fb8c27cbef5..000000000000
--- a/include/asm-xtensa/string.h
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * include/asm-xtensa/string.h
3 *
4 * These trivial string functions are considered part of the public domain.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13/* We should optimize these. See arch/xtensa/lib/strncpy_user.S */
14
15#ifndef _XTENSA_STRING_H
16#define _XTENSA_STRING_H
17
18#define __HAVE_ARCH_STRCPY
19static inline char *strcpy(char *__dest, const char *__src)
20{
21 register char *__xdest = __dest;
22 unsigned long __dummy;
23
24 __asm__ __volatile__("1:\n\t"
25 "l8ui %2, %1, 0\n\t"
26 "s8i %2, %0, 0\n\t"
27 "addi %1, %1, 1\n\t"
28 "addi %0, %0, 1\n\t"
29 "bnez %2, 1b\n\t"
30 : "=r" (__dest), "=r" (__src), "=&r" (__dummy)
31 : "0" (__dest), "1" (__src)
32 : "memory");
33
34 return __xdest;
35}
36
37#define __HAVE_ARCH_STRNCPY
38static inline char *strncpy(char *__dest, const char *__src, size_t __n)
39{
40 register char *__xdest = __dest;
41 unsigned long __dummy;
42
43 if (__n == 0)
44 return __xdest;
45
46 __asm__ __volatile__(
47 "1:\n\t"
48 "l8ui %2, %1, 0\n\t"
49 "s8i %2, %0, 0\n\t"
50 "addi %1, %1, 1\n\t"
51 "addi %0, %0, 1\n\t"
52 "beqz %2, 2f\n\t"
53 "bne %1, %5, 1b\n"
54 "2:"
55 : "=r" (__dest), "=r" (__src), "=&r" (__dummy)
56 : "0" (__dest), "1" (__src), "r" (__src+__n)
57 : "memory");
58
59 return __xdest;
60}
61
62#define __HAVE_ARCH_STRCMP
63static inline int strcmp(const char *__cs, const char *__ct)
64{
65 register int __res;
66 unsigned long __dummy;
67
68 __asm__ __volatile__(
69 "1:\n\t"
70 "l8ui %3, %1, 0\n\t"
71 "addi %1, %1, 1\n\t"
72 "l8ui %2, %0, 0\n\t"
73 "addi %0, %0, 1\n\t"
74 "beqz %2, 2f\n\t"
75 "beq %2, %3, 1b\n"
76 "2:\n\t"
77 "sub %2, %3, %2"
78 : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
79 : "0" (__cs), "1" (__ct));
80
81 return __res;
82}
83
84#define __HAVE_ARCH_STRNCMP
85static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
86{
87 register int __res;
88 unsigned long __dummy;
89
90 __asm__ __volatile__(
91 "mov %2, %3\n"
92 "1:\n\t"
93 "beq %0, %6, 2f\n\t"
94 "l8ui %3, %1, 0\n\t"
95 "addi %1, %1, 1\n\t"
96 "l8ui %2, %0, 0\n\t"
97 "addi %0, %0, 1\n\t"
98 "beqz %2, 2f\n\t"
99 "beqz %3, 2f\n\t"
100 "beq %2, %3, 1b\n"
101 "2:\n\t"
102 "sub %2, %3, %2"
103 : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&r" (__dummy)
104 : "0" (__cs), "1" (__ct), "r" (__cs+__n));
105
106 return __res;
107}
108
109#define __HAVE_ARCH_MEMSET
110extern void *memset(void *__s, int __c, size_t __count);
111
112#define __HAVE_ARCH_MEMCPY
113extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
114
115#define __HAVE_ARCH_MEMMOVE
116extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
117
118/* Don't build bcopy at all ... */
119#define __HAVE_ARCH_BCOPY
120
121#define __HAVE_ARCH_MEMSCAN
122#define memscan memchr
123
124#endif /* _XTENSA_STRING_H */
diff --git a/include/asm-xtensa/syscall.h b/include/asm-xtensa/syscall.h
deleted file mode 100644
index 05cebf8f62b1..000000000000
--- a/include/asm-xtensa/syscall.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-xtensa/syscall.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11struct pt_regs;
12struct sigaction;
13asmlinkage long xtensa_execve(char*, char**, char**, struct pt_regs*);
14asmlinkage long xtensa_clone(unsigned long, unsigned long, struct pt_regs*);
15asmlinkage long xtensa_pipe(int __user *);
16asmlinkage long xtensa_mmap2(unsigned long, unsigned long, unsigned long,
17 unsigned long, unsigned long, unsigned long);
18asmlinkage long xtensa_ptrace(long, long, long, long);
19asmlinkage long xtensa_sigreturn(struct pt_regs*);
20asmlinkage long xtensa_rt_sigreturn(struct pt_regs*);
21asmlinkage long xtensa_sigsuspend(struct pt_regs*);
22asmlinkage long xtensa_rt_sigsuspend(struct pt_regs*);
23asmlinkage long xtensa_sigaction(int, const struct old_sigaction*,
24 struct old_sigaction*);
25asmlinkage long xtensa_sigaltstack(struct pt_regs *regs);
26asmlinkage long sys_rt_sigaction(int,
27 const struct sigaction __user *,
28 struct sigaction __user *,
29 size_t);
30asmlinkage long xtensa_shmat(int, char __user *, int);
31asmlinkage long xtensa_fadvise64_64(int, int,
32 unsigned long long, unsigned long long);
33
34/* Should probably move to linux/syscalls.h */
35struct pollfd;
36asmlinkage long sys_pselect6(int n, fd_set __user *inp, fd_set __user *outp,
37 fd_set __user *exp, struct timespec __user *tsp, void __user *sig);
38asmlinkage long sys_ppoll(struct pollfd __user *ufds, unsigned int nfds,
39 struct timespec __user *tsp, const sigset_t __user *sigmask,
40 size_t sigsetsize);
41
42
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
deleted file mode 100644
index 62b1e8f3c13c..000000000000
--- a/include/asm-xtensa/system.h
+++ /dev/null
@@ -1,215 +0,0 @@
1/*
2 * include/asm-xtensa/system.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SYSTEM_H
12#define _XTENSA_SYSTEM_H
13
14#include <linux/stringify.h>
15
16#include <asm/processor.h>
17
18/* interrupt control */
19
20#define local_save_flags(x) \
21 __asm__ __volatile__ ("rsr %0,"__stringify(PS) : "=a" (x));
22#define local_irq_restore(x) do { \
23 __asm__ __volatile__ ("wsr %0, "__stringify(PS)" ; rsync" \
24 :: "a" (x) : "memory"); } while(0);
25#define local_irq_save(x) do { \
26 __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL) \
27 : "=a" (x) :: "memory");} while(0);
28
29static inline void local_irq_disable(void)
30{
31 unsigned long flags;
32 __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)
33 : "=a" (flags) :: "memory");
34}
35static inline void local_irq_enable(void)
36{
37 unsigned long flags;
38 __asm__ __volatile__ ("rsil %0, 0" : "=a" (flags) :: "memory");
39
40}
41
42static inline int irqs_disabled(void)
43{
44 unsigned long flags;
45 local_save_flags(flags);
46 return flags & 0xf;
47}
48
49
50#define smp_read_barrier_depends() do { } while(0)
51#define read_barrier_depends() do { } while(0)
52
53#define mb() barrier()
54#define rmb() mb()
55#define wmb() mb()
56
57#ifdef CONFIG_SMP
58#error smp_* not defined
59#else
60#define smp_mb() barrier()
61#define smp_rmb() barrier()
62#define smp_wmb() barrier()
63#endif
64
65#define set_mb(var, value) do { var = value; mb(); } while (0)
66
67#if !defined (__ASSEMBLY__)
68
69/* * switch_to(n) should switch tasks to task nr n, first
70 * checking that n isn't the current task, in which case it does nothing.
71 */
72extern void *_switch_to(void *last, void *next);
73
74#endif /* __ASSEMBLY__ */
75
76#define switch_to(prev,next,last) \
77do { \
78 (last) = _switch_to(prev, next); \
79} while(0)
80
81/*
82 * cmpxchg
83 */
84
85static inline unsigned long
86__cmpxchg_u32(volatile int *p, int old, int new)
87{
88 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
89 "l32i %0, %1, 0 \n\t"
90 "bne %0, %2, 1f \n\t"
91 "s32i %3, %1, 0 \n\t"
92 "1: \n\t"
93 "wsr a15, "__stringify(PS)" \n\t"
94 "rsync \n\t"
95 : "=&a" (old)
96 : "a" (p), "a" (old), "r" (new)
97 : "a15", "memory");
98 return old;
99}
100/* This function doesn't exist, so you'll get a linker error
101 * if something tries to do an invalid cmpxchg(). */
102
103extern void __cmpxchg_called_with_bad_pointer(void);
104
105static __inline__ unsigned long
106__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
107{
108 switch (size) {
109 case 4: return __cmpxchg_u32(ptr, old, new);
110 default: __cmpxchg_called_with_bad_pointer();
111 return old;
112 }
113}
114
115#define cmpxchg(ptr,o,n) \
116 ({ __typeof__(*(ptr)) _o_ = (o); \
117 __typeof__(*(ptr)) _n_ = (n); \
118 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
119 (unsigned long)_n_, sizeof (*(ptr))); \
120 })
121
122#include <asm-generic/cmpxchg-local.h>
123
124static inline unsigned long __cmpxchg_local(volatile void *ptr,
125 unsigned long old,
126 unsigned long new, int size)
127{
128 switch (size) {
129 case 4:
130 return __cmpxchg_u32(ptr, old, new);
131 default:
132 return __cmpxchg_local_generic(ptr, old, new, size);
133 }
134
135 return old;
136}
137
138/*
139 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
140 * them available.
141 */
142#define cmpxchg_local(ptr, o, n) \
143 ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
144 (unsigned long)(n), sizeof(*(ptr))))
145#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
146
147/*
148 * xchg_u32
149 *
150 * Note that a15 is used here because the register allocation
151 * done by the compiler is not guaranteed and a window overflow
152 * may not occur between the rsil and wsr instructions. By using
153 * a15 in the rsil, the machine is guaranteed to be in a state
154 * where no register reference will cause an overflow.
155 */
156
157static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
158{
159 unsigned long tmp;
160 __asm__ __volatile__("rsil a15, "__stringify(LOCKLEVEL)"\n\t"
161 "l32i %0, %1, 0 \n\t"
162 "s32i %2, %1, 0 \n\t"
163 "wsr a15, "__stringify(PS)" \n\t"
164 "rsync \n\t"
165 : "=&a" (tmp)
166 : "a" (m), "a" (val)
167 : "a15", "memory");
168 return tmp;
169}
170
171#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
172
173/*
174 * This only works if the compiler isn't horribly bad at optimizing.
175 * gcc-2.5.8 reportedly can't handle this, but I define that one to
176 * be dead anyway.
177 */
178
179extern void __xchg_called_with_bad_pointer(void);
180
181static __inline__ unsigned long
182__xchg(unsigned long x, volatile void * ptr, int size)
183{
184 switch (size) {
185 case 4:
186 return xchg_u32(ptr, x);
187 }
188 __xchg_called_with_bad_pointer();
189 return x;
190}
191
192extern void set_except_vector(int n, void *addr);
193
194static inline void spill_registers(void)
195{
196 unsigned int a0, ps;
197
198 __asm__ __volatile__ (
199 "movi a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
200 "mov a12, a0\n\t"
201 "rsr a13," __stringify(SAR) "\n\t"
202 "xsr a14," __stringify(PS) "\n\t"
203 "movi a0, _spill_registers\n\t"
204 "rsync\n\t"
205 "callx0 a0\n\t"
206 "mov a0, a12\n\t"
207 "wsr a13," __stringify(SAR) "\n\t"
208 "wsr a14," __stringify(PS) "\n\t"
209 :: "a" (&a0), "a" (&ps)
210 : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
211}
212
213#define arch_align_stack(x) (x)
214
215#endif /* _XTENSA_SYSTEM_H */
diff --git a/include/asm-xtensa/termbits.h b/include/asm-xtensa/termbits.h
deleted file mode 100644
index 85aa6a3c0b6e..000000000000
--- a/include/asm-xtensa/termbits.h
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * include/asm-xtensa/termbits.h
3 *
4 * Copied from SH.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_TERMBITS_H
14#define _XTENSA_TERMBITS_H
15
16
17#include <linux/posix_types.h>
18
19typedef unsigned char cc_t;
20typedef unsigned int speed_t;
21typedef unsigned int tcflag_t;
22
23#define NCCS 19
24struct termios {
25 tcflag_t c_iflag; /* input mode flags */
26 tcflag_t c_oflag; /* output mode flags */
27 tcflag_t c_cflag; /* control mode flags */
28 tcflag_t c_lflag; /* local mode flags */
29 cc_t c_line; /* line discipline */
30 cc_t c_cc[NCCS]; /* control characters */
31};
32
33struct termios2 {
34 tcflag_t c_iflag; /* input mode flags */
35 tcflag_t c_oflag; /* output mode flags */
36 tcflag_t c_cflag; /* control mode flags */
37 tcflag_t c_lflag; /* local mode flags */
38 cc_t c_line; /* line discipline */
39 cc_t c_cc[NCCS]; /* control characters */
40 speed_t c_ispeed; /* input speed */
41 speed_t c_ospeed; /* output speed */
42};
43
44struct ktermios {
45 tcflag_t c_iflag; /* input mode flags */
46 tcflag_t c_oflag; /* output mode flags */
47 tcflag_t c_cflag; /* control mode flags */
48 tcflag_t c_lflag; /* local mode flags */
49 cc_t c_line; /* line discipline */
50 cc_t c_cc[NCCS]; /* control characters */
51 speed_t c_ispeed; /* input speed */
52 speed_t c_ospeed; /* output speed */
53};
54
55/* c_cc characters */
56
57#define VINTR 0
58#define VQUIT 1
59#define VERASE 2
60#define VKILL 3
61#define VEOF 4
62#define VTIME 5
63#define VMIN 6
64#define VSWTC 7
65#define VSTART 8
66#define VSTOP 9
67#define VSUSP 10
68#define VEOL 11
69#define VREPRINT 12
70#define VDISCARD 13
71#define VWERASE 14
72#define VLNEXT 15
73#define VEOL2 16
74
75/* c_iflag bits */
76
77#define IGNBRK 0000001
78#define BRKINT 0000002
79#define IGNPAR 0000004
80#define PARMRK 0000010
81#define INPCK 0000020
82#define ISTRIP 0000040
83#define INLCR 0000100
84#define IGNCR 0000200
85#define ICRNL 0000400
86#define IUCLC 0001000
87#define IXON 0002000
88#define IXANY 0004000
89#define IXOFF 0010000
90#define IMAXBEL 0020000
91#define IUTF8 0040000
92
93/* c_oflag bits */
94
95#define OPOST 0000001
96#define OLCUC 0000002
97#define ONLCR 0000004
98#define OCRNL 0000010
99#define ONOCR 0000020
100#define ONLRET 0000040
101#define OFILL 0000100
102#define OFDEL 0000200
103#define NLDLY 0000400
104#define NL0 0000000
105#define NL1 0000400
106#define CRDLY 0003000
107#define CR0 0000000
108#define CR1 0001000
109#define CR2 0002000
110#define CR3 0003000
111#define TABDLY 0014000
112#define TAB0 0000000
113#define TAB1 0004000
114#define TAB2 0010000
115#define TAB3 0014000
116#define XTABS 0014000
117#define BSDLY 0020000
118#define BS0 0000000
119#define BS1 0020000
120#define VTDLY 0040000
121#define VT0 0000000
122#define VT1 0040000
123#define FFDLY 0100000
124#define FF0 0000000
125#define FF1 0100000
126
127/* c_cflag bit meaning */
128
129#define CBAUD 0010017
130#define B0 0000000 /* hang up */
131#define B50 0000001
132#define B75 0000002
133#define B110 0000003
134#define B134 0000004
135#define B150 0000005
136#define B200 0000006
137#define B300 0000007
138#define B600 0000010
139#define B1200 0000011
140#define B1800 0000012
141#define B2400 0000013
142#define B4800 0000014
143#define B9600 0000015
144#define B19200 0000016
145#define B38400 0000017
146#define EXTA B19200
147#define EXTB B38400
148#define CSIZE 0000060
149#define CS5 0000000
150#define CS6 0000020
151#define CS7 0000040
152#define CS8 0000060
153#define CSTOPB 0000100
154#define CREAD 0000200
155#define PARENB 0000400
156#define PARODD 0001000
157#define HUPCL 0002000
158#define CLOCAL 0004000
159#define CBAUDEX 0010000
160#define BOTHER 0010000
161#define B57600 0010001
162#define B115200 0010002
163#define B230400 0010003
164#define B460800 0010004
165#define B500000 0010005
166#define B576000 0010006
167#define B921600 0010007
168#define B1000000 0010010
169#define B1152000 0010011
170#define B1500000 0010012
171#define B2000000 0010013
172#define B2500000 0010014
173#define B3000000 0010015
174#define B3500000 0010016
175#define B4000000 0010017
176#define CIBAUD 002003600000 /* input baud rate */
177#define CMSPAR 010000000000 /* mark or space (stick) parity */
178#define CRTSCTS 020000000000 /* flow control */
179
180#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
181
182/* c_lflag bits */
183
184#define ISIG 0000001
185#define ICANON 0000002
186#define XCASE 0000004
187#define ECHO 0000010
188#define ECHOE 0000020
189#define ECHOK 0000040
190#define ECHONL 0000100
191#define NOFLSH 0000200
192#define TOSTOP 0000400
193#define ECHOCTL 0001000
194#define ECHOPRT 0002000
195#define ECHOKE 0004000
196#define FLUSHO 0010000
197#define PENDIN 0040000
198#define IEXTEN 0100000
199
200/* tcflow() and TCXONC use these */
201
202#define TCOOFF 0
203#define TCOON 1
204#define TCIOFF 2
205#define TCION 3
206
207/* tcflush() and TCFLSH use these */
208
209#define TCIFLUSH 0
210#define TCOFLUSH 1
211#define TCIOFLUSH 2
212
213/* tcsetattr uses these */
214
215#define TCSANOW 0
216#define TCSADRAIN 1
217#define TCSAFLUSH 2
218
219#endif /* _XTENSA_TERMBITS_H */
diff --git a/include/asm-xtensa/termios.h b/include/asm-xtensa/termios.h
deleted file mode 100644
index 4673f42f88a7..000000000000
--- a/include/asm-xtensa/termios.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * include/asm-xtensa/termios.h
3 *
4 * Copied from SH.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_TERMIOS_H
14#define _XTENSA_TERMIOS_H
15
16#include <asm/termbits.h>
17#include <asm/ioctls.h>
18
19struct winsize {
20 unsigned short ws_row;
21 unsigned short ws_col;
22 unsigned short ws_xpixel;
23 unsigned short ws_ypixel;
24};
25
26#define NCC 8
27struct termio {
28 unsigned short c_iflag; /* input mode flags */
29 unsigned short c_oflag; /* output mode flags */
30 unsigned short c_cflag; /* control mode flags */
31 unsigned short c_lflag; /* local mode flags */
32 unsigned char c_line; /* line discipline */
33 unsigned char c_cc[NCC]; /* control characters */
34};
35
36/* Modem lines */
37
38#define TIOCM_LE 0x001
39#define TIOCM_DTR 0x002
40#define TIOCM_RTS 0x004
41#define TIOCM_ST 0x008
42#define TIOCM_SR 0x010
43#define TIOCM_CTS 0x020
44#define TIOCM_CAR 0x040
45#define TIOCM_RNG 0x080
46#define TIOCM_DSR 0x100
47#define TIOCM_CD TIOCM_CAR
48#define TIOCM_RI TIOCM_RNG
49#define TIOCM_OUT1 0x2000
50#define TIOCM_OUT2 0x4000
51#define TIOCM_LOOP 0x8000
52
53/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
54
55#ifdef __KERNEL__
56
57/* intr=^C quit=^\ erase=del kill=^U
58 eof=^D vtime=\0 vmin=\1 sxtc=\0
59 start=^Q stop=^S susp=^Z eol=\0
60 reprint=^R discard=^U werase=^W lnext=^V
61 eol2=\0
62*/
63#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
64
65/*
66 * Translate a "termio" structure into a "termios". Ugh.
67 */
68
69#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
70 unsigned short __tmp; \
71 get_user(__tmp,&(termio)->x); \
72 *(unsigned short *) &(termios)->x = __tmp; \
73}
74
75#define user_termio_to_kernel_termios(termios, termio) \
76({ \
77 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
78 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
79 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
80 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
81 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
82})
83
84/*
85 * Translate a "termios" structure into a "termio". Ugh.
86 */
87
88#define kernel_termios_to_user_termio(termio, termios) \
89({ \
90 put_user((termios)->c_iflag, &(termio)->c_iflag); \
91 put_user((termios)->c_oflag, &(termio)->c_oflag); \
92 put_user((termios)->c_cflag, &(termio)->c_cflag); \
93 put_user((termios)->c_lflag, &(termio)->c_lflag); \
94 put_user((termios)->c_line, &(termio)->c_line); \
95 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
96})
97
98#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
99#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
100#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
101#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
102
103#endif /* __KERNEL__ */
104
105#endif /* _XTENSA_TERMIOS_H */
diff --git a/include/asm-xtensa/thread_info.h b/include/asm-xtensa/thread_info.h
deleted file mode 100644
index 0f4fe1faf9ba..000000000000
--- a/include/asm-xtensa/thread_info.h
+++ /dev/null
@@ -1,164 +0,0 @@
1/*
2 * include/asm-xtensa/thread_info.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_THREAD_INFO_H
12#define _XTENSA_THREAD_INFO_H
13
14#ifdef __KERNEL__
15
16#ifndef __ASSEMBLY__
17# include <asm/processor.h>
18#endif
19
20/*
21 * low level task data that entry.S needs immediate access to
22 * - this struct should fit entirely inside of one cache line
23 * - this struct shares the supervisor stack pages
24 * - if the contents of this structure are changed, the assembly constants
25 * must also be changed
26 */
27
28#ifndef __ASSEMBLY__
29
30#if XTENSA_HAVE_COPROCESSORS
31
32typedef struct xtregs_coprocessor {
33 xtregs_cp0_t cp0;
34 xtregs_cp1_t cp1;
35 xtregs_cp2_t cp2;
36 xtregs_cp3_t cp3;
37 xtregs_cp4_t cp4;
38 xtregs_cp5_t cp5;
39 xtregs_cp6_t cp6;
40 xtregs_cp7_t cp7;
41} xtregs_coprocessor_t;
42
43#endif
44
45struct thread_info {
46 struct task_struct *task; /* main task structure */
47 struct exec_domain *exec_domain; /* execution domain */
48 unsigned long flags; /* low level flags */
49 unsigned long status; /* thread-synchronous flags */
50 __u32 cpu; /* current CPU */
51 __s32 preempt_count; /* 0 => preemptable,< 0 => BUG*/
52
53 mm_segment_t addr_limit; /* thread address space */
54 struct restart_block restart_block;
55
56 unsigned long cpenable;
57
58 /* Allocate storage for extra user states and coprocessor states. */
59#if XTENSA_HAVE_COPROCESSORS
60 xtregs_coprocessor_t xtregs_cp;
61#endif
62 xtregs_user_t xtregs_user;
63};
64
65#else /* !__ASSEMBLY__ */
66
67/* offsets into the thread_info struct for assembly code access */
68#define TI_TASK 0x00000000
69#define TI_EXEC_DOMAIN 0x00000004
70#define TI_FLAGS 0x00000008
71#define TI_STATUS 0x0000000C
72#define TI_CPU 0x00000010
73#define TI_PRE_COUNT 0x00000014
74#define TI_ADDR_LIMIT 0x00000018
75#define TI_RESTART_BLOCK 0x000001C
76
77#endif
78
79#define PREEMPT_ACTIVE 0x10000000
80
81/*
82 * macros/functions for gaining access to the thread information structure
83 *
84 * preempt_count needs to be 1 initially, until the scheduler is functional.
85 */
86
87#ifndef __ASSEMBLY__
88
89#define INIT_THREAD_INFO(tsk) \
90{ \
91 .task = &tsk, \
92 .exec_domain = &default_exec_domain, \
93 .flags = 0, \
94 .cpu = 0, \
95 .preempt_count = 1, \
96 .addr_limit = KERNEL_DS, \
97 .restart_block = { \
98 .fn = do_no_restart_syscall, \
99 }, \
100}
101
102#define init_thread_info (init_thread_union.thread_info)
103#define init_stack (init_thread_union.stack)
104
105/* how to get the thread information struct from C */
106static inline struct thread_info *current_thread_info(void)
107{
108 struct thread_info *ti;
109 __asm__("extui %0,a1,0,13\n\t"
110 "xor %0, a1, %0" : "=&r" (ti) : );
111 return ti;
112}
113
114#else /* !__ASSEMBLY__ */
115
116/* how to get the thread information struct from ASM */
117#define GET_THREAD_INFO(reg,sp) \
118 extui reg, sp, 0, 13; \
119 xor reg, sp, reg
120#endif
121
122
123/*
124 * thread information flags
125 * - these are process state flags that various assembly files may need to access
126 * - pending work-to-be-done flags are in LSW
127 * - other flags in MSW
128 */
129#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
130#define TIF_SIGPENDING 1 /* signal pending */
131#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
132#define TIF_SINGLESTEP 3 /* restore singlestep on return to user mode */
133#define TIF_IRET 4 /* return with iret */
134#define TIF_MEMDIE 5
135#define TIF_RESTORE_SIGMASK 6 /* restore signal mask in do_signal() */
136#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
137#define TIF_FREEZE 17 /* is freezing for suspend */
138
139#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
140#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
141#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
142#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
143#define _TIF_IRET (1<<TIF_IRET)
144#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
145#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
146#define _TIF_FREEZE (1<<TIF_FREEZE)
147
148#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
149#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
150
151/*
152 * Thread-synchronous status.
153 *
154 * This is different from the flags in that nobody else
155 * ever touches our thread-synchronous status, so we don't
156 * have to worry about atomic accesses.
157 */
158#define TS_USEDFPU 0x0001 /* FPU was used by this task this quantum (SMP) */
159
160#define THREAD_SIZE 8192 //(2*PAGE_SIZE)
161#define THREAD_SIZE_ORDER 1
162
163#endif /* __KERNEL__ */
164#endif /* _XTENSA_THREAD_INFO */
diff --git a/include/asm-xtensa/timex.h b/include/asm-xtensa/timex.h
deleted file mode 100644
index b83a8181d448..000000000000
--- a/include/asm-xtensa/timex.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * include/asm-xtensa/timex.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TIMEX_H
12#define _XTENSA_TIMEX_H
13
14#ifdef __KERNEL__
15
16#include <asm/processor.h>
17#include <linux/stringify.h>
18
19#define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
20#define INTLEVEL(x) _INTLEVEL(x)
21
22#if INTLEVEL(XCHAL_TIMER0_INTERRUPT) == 1
23# define LINUX_TIMER 0
24# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
25#elif INTLEVEL(XCHAL_TIMER1_INTERRUPT) == 1
26# define LINUX_TIMER 1
27# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
28#elif INTLEVEL(XCHAL_TIMER2_INTERRUPT) == 1
29# define LINUX_TIMER 2
30# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
31#else
32# error "Bad timer number for Linux configurations!"
33#endif
34
35#define LINUX_TIMER_MASK (1L << LINUX_TIMER_INT)
36
37#define CLOCK_TICK_RATE 1193180 /* (everyone is using this value) */
38#define CLOCK_TICK_FACTOR 20 /* Factor of both 10^6 and CLOCK_TICK_RATE */
39
40#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
41extern unsigned long ccount_per_jiffy;
42extern unsigned long ccount_nsec;
43#define CCOUNT_PER_JIFFY ccount_per_jiffy
44#define NSEC_PER_CCOUNT ccount_nsec
45#else
46#define CCOUNT_PER_JIFFY (CONFIG_XTENSA_CPU_CLOCK*(1000000UL/HZ))
47#define NSEC_PER_CCOUNT (1000UL / CONFIG_XTENSA_CPU_CLOCK)
48#endif
49
50
51typedef unsigned long long cycles_t;
52
53/*
54 * Only used for SMP.
55 */
56
57extern cycles_t cacheflush_time;
58
59#define get_cycles() (0)
60
61
62/*
63 * Register access.
64 */
65
66#define WSR_CCOUNT(r) asm volatile ("wsr %0,"__stringify(CCOUNT) :: "a" (r))
67#define RSR_CCOUNT(r) asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (r))
68#define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(CCOMPARE)"+"__stringify(x) :: "a"(r))
69#define RSR_CCOMPARE(x,r) asm volatile ("rsr %0,"__stringify(CCOMPARE)"+"__stringify(x) : "=a"(r))
70
71static inline unsigned long get_ccount (void)
72{
73 unsigned long ccount;
74 RSR_CCOUNT(ccount);
75 return ccount;
76}
77
78static inline void set_ccount (unsigned long ccount)
79{
80 WSR_CCOUNT(ccount);
81}
82
83static inline unsigned long get_linux_timer (void)
84{
85 unsigned ccompare;
86 RSR_CCOMPARE(LINUX_TIMER, ccompare);
87 return ccompare;
88}
89
90static inline void set_linux_timer (unsigned long ccompare)
91{
92 WSR_CCOMPARE(LINUX_TIMER, ccompare);
93}
94
95#endif /* __KERNEL__ */
96#endif /* _XTENSA_TIMEX_H */
diff --git a/include/asm-xtensa/tlb.h b/include/asm-xtensa/tlb.h
deleted file mode 100644
index 31c220faca02..000000000000
--- a/include/asm-xtensa/tlb.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * include/asm-xtensa/tlb.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TLB_H
12#define _XTENSA_TLB_H
13
14#include <asm/cache.h>
15#include <asm/page.h>
16
17#if (DCACHE_WAY_SIZE <= PAGE_SIZE)
18
19/* Note, read http://lkml.org/lkml/2004/1/15/6 */
20
21# define tlb_start_vma(tlb,vma) do { } while (0)
22# define tlb_end_vma(tlb,vma) do { } while (0)
23
24#else
25
26# define tlb_start_vma(tlb, vma) \
27 do { \
28 if (!tlb->fullmm) \
29 flush_cache_range(vma, vma->vm_start, vma->vm_end); \
30 } while(0)
31
32# define tlb_end_vma(tlb, vma) \
33 do { \
34 if (!tlb->fullmm) \
35 flush_tlb_range(vma, vma->vm_start, vma->vm_end); \
36 } while(0)
37
38#endif
39
40#define __tlb_remove_tlb_entry(tlb,pte,addr) do { } while (0)
41#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
42
43#include <asm-generic/tlb.h>
44
45#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
46
47#endif /* _XTENSA_TLB_H */
diff --git a/include/asm-xtensa/tlbflush.h b/include/asm-xtensa/tlbflush.h
deleted file mode 100644
index 46d240074f74..000000000000
--- a/include/asm-xtensa/tlbflush.h
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * include/asm-xtensa/tlbflush.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TLBFLUSH_H
12#define _XTENSA_TLBFLUSH_H
13
14#ifdef __KERNEL__
15
16#include <linux/stringify.h>
17#include <asm/processor.h>
18
19#define DTLB_WAY_PGD 7
20
21#define ITLB_ARF_WAYS 4
22#define DTLB_ARF_WAYS 4
23
24#define ITLB_HIT_BIT 3
25#define DTLB_HIT_BIT 4
26
27#ifndef __ASSEMBLY__
28
29/* TLB flushing:
30 *
31 * - flush_tlb_all() flushes all processes TLB entries
32 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
33 * - flush_tlb_page(mm, vmaddr) flushes a single page
34 * - flush_tlb_range(mm, start, end) flushes a range of pages
35 */
36
37extern void flush_tlb_all(void);
38extern void flush_tlb_mm(struct mm_struct*);
39extern void flush_tlb_page(struct vm_area_struct*,unsigned long);
40extern void flush_tlb_range(struct vm_area_struct*,unsigned long,unsigned long);
41
42#define flush_tlb_kernel_range(start,end) flush_tlb_all()
43
44/* TLB operations. */
45
46static inline unsigned long itlb_probe(unsigned long addr)
47{
48 unsigned long tmp;
49 __asm__ __volatile__("pitlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
50 return tmp;
51}
52
53static inline unsigned long dtlb_probe(unsigned long addr)
54{
55 unsigned long tmp;
56 __asm__ __volatile__("pdtlb %0, %1\n\t" : "=a" (tmp) : "a" (addr));
57 return tmp;
58}
59
60static inline void invalidate_itlb_entry (unsigned long probe)
61{
62 __asm__ __volatile__("iitlb %0; isync\n\t" : : "a" (probe));
63}
64
65static inline void invalidate_dtlb_entry (unsigned long probe)
66{
67 __asm__ __volatile__("idtlb %0; dsync\n\t" : : "a" (probe));
68}
69
70/* Use the .._no_isync functions with caution. Generally, these are
71 * handy for bulk invalidates followed by a single 'isync'. The
72 * caller must follow up with an 'isync', which can be relatively
73 * expensive on some Xtensa implementations.
74 */
75static inline void invalidate_itlb_entry_no_isync (unsigned entry)
76{
77 /* Caller must follow up with 'isync'. */
78 __asm__ __volatile__ ("iitlb %0\n" : : "a" (entry) );
79}
80
81static inline void invalidate_dtlb_entry_no_isync (unsigned entry)
82{
83 /* Caller must follow up with 'isync'. */
84 __asm__ __volatile__ ("idtlb %0\n" : : "a" (entry) );
85}
86
87static inline void set_itlbcfg_register (unsigned long val)
88{
89 __asm__ __volatile__("wsr %0, "__stringify(ITLBCFG)"\n\t" "isync\n\t"
90 : : "a" (val));
91}
92
93static inline void set_dtlbcfg_register (unsigned long val)
94{
95 __asm__ __volatile__("wsr %0, "__stringify(DTLBCFG)"; dsync\n\t"
96 : : "a" (val));
97}
98
99static inline void set_ptevaddr_register (unsigned long val)
100{
101 __asm__ __volatile__(" wsr %0, "__stringify(PTEVADDR)"; isync\n"
102 : : "a" (val));
103}
104
105static inline unsigned long read_ptevaddr_register (void)
106{
107 unsigned long tmp;
108 __asm__ __volatile__("rsr %0, "__stringify(PTEVADDR)"\n\t" : "=a" (tmp));
109 return tmp;
110}
111
112static inline void write_dtlb_entry (pte_t entry, int way)
113{
114 __asm__ __volatile__("wdtlb %1, %0; dsync\n\t"
115 : : "r" (way), "r" (entry) );
116}
117
118static inline void write_itlb_entry (pte_t entry, int way)
119{
120 __asm__ __volatile__("witlb %1, %0; isync\n\t"
121 : : "r" (way), "r" (entry) );
122}
123
124static inline void invalidate_page_directory (void)
125{
126 invalidate_dtlb_entry (DTLB_WAY_PGD);
127 invalidate_dtlb_entry (DTLB_WAY_PGD+1);
128 invalidate_dtlb_entry (DTLB_WAY_PGD+2);
129}
130
131static inline void invalidate_itlb_mapping (unsigned address)
132{
133 unsigned long tlb_entry;
134 if (((tlb_entry = itlb_probe(address)) & (1 << ITLB_HIT_BIT)) != 0)
135 invalidate_itlb_entry(tlb_entry);
136}
137
138static inline void invalidate_dtlb_mapping (unsigned address)
139{
140 unsigned long tlb_entry;
141 if (((tlb_entry = dtlb_probe(address)) & (1 << DTLB_HIT_BIT)) != 0)
142 invalidate_dtlb_entry(tlb_entry);
143}
144
145#define check_pgt_cache() do { } while (0)
146
147
148/*
149 * DO NOT USE THESE FUNCTIONS. These instructions aren't part of the Xtensa
150 * ISA and exist only for test purposes..
151 * You may find it helpful for MMU debugging, however.
152 *
153 * 'at' is the unmodified input register
154 * 'as' is the output register, as follows (specific to the Linux config):
155 *
156 * as[31..12] contain the virtual address
157 * as[11..08] are meaningless
158 * as[07..00] contain the asid
159 */
160
161static inline unsigned long read_dtlb_virtual (int way)
162{
163 unsigned long tmp;
164 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way));
165 return tmp;
166}
167
168static inline unsigned long read_dtlb_translation (int way)
169{
170 unsigned long tmp;
171 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way));
172 return tmp;
173}
174
175static inline unsigned long read_itlb_virtual (int way)
176{
177 unsigned long tmp;
178 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way));
179 return tmp;
180}
181
182static inline unsigned long read_itlb_translation (int way)
183{
184 unsigned long tmp;
185 __asm__ __volatile__("ritlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way));
186 return tmp;
187}
188
189#endif /* __ASSEMBLY__ */
190#endif /* __KERNEL__ */
191#endif /* _XTENSA_TLBFLUSH_H */
diff --git a/include/asm-xtensa/topology.h b/include/asm-xtensa/topology.h
deleted file mode 100644
index 7309e38a0ccb..000000000000
--- a/include/asm-xtensa/topology.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/topology.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TOPOLOGY_H
12#define _XTENSA_TOPOLOGY_H
13
14#include <asm-generic/topology.h>
15
16#endif /* _XTENSA_TOPOLOGY_H */
diff --git a/include/asm-xtensa/types.h b/include/asm-xtensa/types.h
deleted file mode 100644
index c89569a8da0c..000000000000
--- a/include/asm-xtensa/types.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-xtensa/types.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_TYPES_H
12#define _XTENSA_TYPES_H
13
14#include <asm-generic/int-ll64.h>
15
16#ifdef __ASSEMBLY__
17# define __XTENSA_UL(x) (x)
18# define __XTENSA_UL_CONST(x) x
19#else
20# define __XTENSA_UL(x) ((unsigned long)(x))
21# define __XTENSA_UL_CONST(x) x##UL
22#endif
23
24#ifndef __ASSEMBLY__
25
26typedef unsigned short umode_t;
27
28/*
29 * These aren't exported outside the kernel to avoid name space clashes
30 */
31#ifdef __KERNEL__
32
33#define BITS_PER_LONG 32
34
35/* Dma addresses are 32-bits wide. */
36
37typedef u32 dma_addr_t;
38
39#endif /* __KERNEL__ */
40#endif
41
42#endif /* _XTENSA_TYPES_H */
diff --git a/include/asm-xtensa/uaccess.h b/include/asm-xtensa/uaccess.h
deleted file mode 100644
index b8528426ab1f..000000000000
--- a/include/asm-xtensa/uaccess.h
+++ /dev/null
@@ -1,500 +0,0 @@
1/*
2 * include/asm-xtensa/uaccess.h
3 *
4 * User space memory access functions
5 *
6 * These routines provide basic accessing functions to the user memory
7 * space for the kernel. This header file provides fuctions such as:
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 *
13 * Copyright (C) 2001 - 2005 Tensilica Inc.
14 */
15
16#ifndef _XTENSA_UACCESS_H
17#define _XTENSA_UACCESS_H
18
19#include <linux/errno.h>
20
21#define VERIFY_READ 0
22#define VERIFY_WRITE 1
23
24#ifdef __ASSEMBLY__
25
26#include <asm/current.h>
27#include <asm/asm-offsets.h>
28#include <asm/processor.h>
29#include <asm/types.h>
30
31/*
32 * These assembly macros mirror the C macros that follow below. They
33 * should always have identical functionality. See
34 * arch/xtensa/kernel/sys.S for usage.
35 */
36
37#define KERNEL_DS 0
38#define USER_DS 1
39
40#define get_ds (KERNEL_DS)
41
42/*
43 * get_fs reads current->thread.current_ds into a register.
44 * On Entry:
45 * <ad> anything
46 * <sp> stack
47 * On Exit:
48 * <ad> contains current->thread.current_ds
49 */
50 .macro get_fs ad, sp
51 GET_CURRENT(\ad,\sp)
52 l32i \ad, \ad, THREAD_CURRENT_DS
53 .endm
54
55/*
56 * set_fs sets current->thread.current_ds to some value.
57 * On Entry:
58 * <at> anything (temp register)
59 * <av> value to write
60 * <sp> stack
61 * On Exit:
62 * <at> destroyed (actually, current)
63 * <av> preserved, value to write
64 */
65 .macro set_fs at, av, sp
66 GET_CURRENT(\at,\sp)
67 s32i \av, \at, THREAD_CURRENT_DS
68 .endm
69
70/*
71 * kernel_ok determines whether we should bypass addr/size checking.
72 * See the equivalent C-macro version below for clarity.
73 * On success, kernel_ok branches to a label indicated by parameter
74 * <success>. This implies that the macro falls through to the next
75 * insruction on an error.
76 *
77 * Note that while this macro can be used independently, we designed
78 * in for optimal use in the access_ok macro below (i.e., we fall
79 * through on error).
80 *
81 * On Entry:
82 * <at> anything (temp register)
83 * <success> label to branch to on success; implies
84 * fall-through macro on error
85 * <sp> stack pointer
86 * On Exit:
87 * <at> destroyed (actually, current->thread.current_ds)
88 */
89
90#if ((KERNEL_DS != 0) || (USER_DS == 0))
91# error Assembly macro kernel_ok fails
92#endif
93 .macro kernel_ok at, sp, success
94 get_fs \at, \sp
95 beqz \at, \success
96 .endm
97
98/*
99 * user_ok determines whether the access to user-space memory is allowed.
100 * See the equivalent C-macro version below for clarity.
101 *
102 * On error, user_ok branches to a label indicated by parameter
103 * <error>. This implies that the macro falls through to the next
104 * instruction on success.
105 *
106 * Note that while this macro can be used independently, we designed
107 * in for optimal use in the access_ok macro below (i.e., we fall
108 * through on success).
109 *
110 * On Entry:
111 * <aa> register containing memory address
112 * <as> register containing memory size
113 * <at> temp register
114 * <error> label to branch to on error; implies fall-through
115 * macro on success
116 * On Exit:
117 * <aa> preserved
118 * <as> preserved
119 * <at> destroyed (actually, (TASK_SIZE + 1 - size))
120 */
121 .macro user_ok aa, as, at, error
122 movi \at, __XTENSA_UL_CONST(TASK_SIZE)
123 bgeu \as, \at, \error
124 sub \at, \at, \as
125 bgeu \aa, \at, \error
126 .endm
127
128/*
129 * access_ok determines whether a memory access is allowed. See the
130 * equivalent C-macro version below for clarity.
131 *
132 * On error, access_ok branches to a label indicated by parameter
133 * <error>. This implies that the macro falls through to the next
134 * instruction on success.
135 *
136 * Note that we assume success is the common case, and we optimize the
137 * branch fall-through case on success.
138 *
139 * On Entry:
140 * <aa> register containing memory address
141 * <as> register containing memory size
142 * <at> temp register
143 * <sp>
144 * <error> label to branch to on error; implies fall-through
145 * macro on success
146 * On Exit:
147 * <aa> preserved
148 * <as> preserved
149 * <at> destroyed
150 */
151 .macro access_ok aa, as, at, sp, error
152 kernel_ok \at, \sp, .Laccess_ok_\@
153 user_ok \aa, \as, \at, \error
154.Laccess_ok_\@:
155 .endm
156
157#else /* __ASSEMBLY__ not defined */
158
159#include <linux/sched.h>
160#include <asm/types.h>
161
162/*
163 * The fs value determines whether argument validity checking should
164 * be performed or not. If get_fs() == USER_DS, checking is
165 * performed, with get_fs() == KERNEL_DS, checking is bypassed.
166 *
167 * For historical reasons (Data Segment Register?), these macros are
168 * grossly misnamed.
169 */
170
171#define KERNEL_DS ((mm_segment_t) { 0 })
172#define USER_DS ((mm_segment_t) { 1 })
173
174#define get_ds() (KERNEL_DS)
175#define get_fs() (current->thread.current_ds)
176#define set_fs(val) (current->thread.current_ds = (val))
177
178#define segment_eq(a,b) ((a).seg == (b).seg)
179
180#define __kernel_ok (segment_eq(get_fs(), KERNEL_DS))
181#define __user_ok(addr,size) (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size)))
182#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
183#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
184
185/*
186 * These are the main single-value transfer routines. They
187 * automatically use the right size if we just have the right pointer
188 * type.
189 *
190 * This gets kind of ugly. We want to return _two_ values in
191 * "get_user()" and yet we don't want to do any pointers, because that
192 * is too much of a performance impact. Thus we have a few rather ugly
193 * macros here, and hide all the uglyness from the user.
194 *
195 * Careful to not
196 * (a) re-use the arguments for side effects (sizeof is ok)
197 * (b) require any knowledge of processes at this stage
198 */
199#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr)))
200#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr)))
201
202/*
203 * The "__xxx" versions of the user access functions are versions that
204 * do not verify the address space, that must have been done previously
205 * with a separate "access_ok()" call (this is used when we do multiple
206 * accesses to the same area of user memory).
207 */
208#define __put_user(x,ptr) __put_user_nocheck((x),(ptr),sizeof(*(ptr)))
209#define __get_user(x,ptr) __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
210
211
212extern long __put_user_bad(void);
213
214#define __put_user_nocheck(x,ptr,size) \
215({ \
216 long __pu_err; \
217 __put_user_size((x),(ptr),(size),__pu_err); \
218 __pu_err; \
219})
220
221#define __put_user_check(x,ptr,size) \
222({ \
223 long __pu_err = -EFAULT; \
224 __typeof__(*(ptr)) *__pu_addr = (ptr); \
225 if (access_ok(VERIFY_WRITE,__pu_addr,size)) \
226 __put_user_size((x),__pu_addr,(size),__pu_err); \
227 __pu_err; \
228})
229
230#define __put_user_size(x,ptr,size,retval) \
231do { \
232 int __cb; \
233 retval = 0; \
234 switch (size) { \
235 case 1: __put_user_asm(x,ptr,retval,1,"s8i",__cb); break; \
236 case 2: __put_user_asm(x,ptr,retval,2,"s16i",__cb); break; \
237 case 4: __put_user_asm(x,ptr,retval,4,"s32i",__cb); break; \
238 case 8: { \
239 __typeof__(*ptr) __v64 = x; \
240 retval = __copy_to_user(ptr,&__v64,8); \
241 break; \
242 } \
243 default: __put_user_bad(); \
244 } \
245} while (0)
246
247
248/*
249 * Consider a case of a user single load/store would cause both an
250 * unaligned exception and an MMU-related exception (unaligned
251 * exceptions happen first):
252 *
253 * User code passes a bad variable ptr to a system call.
254 * Kernel tries to access the variable.
255 * Unaligned exception occurs.
256 * Unaligned exception handler tries to make aligned accesses.
257 * Double exception occurs for MMU-related cause (e.g., page not mapped).
258 * do_page_fault() thinks the fault address belongs to the kernel, not the
259 * user, and panics.
260 *
261 * The kernel currently prohibits user unaligned accesses. We use the
262 * __check_align_* macros to check for unaligned addresses before
263 * accessing user space so we don't crash the kernel. Both
264 * __put_user_asm and __get_user_asm use these alignment macros, so
265 * macro-specific labels such as 0f, 1f, %0, %2, and %3 must stay in
266 * sync.
267 */
268
269#define __check_align_1 ""
270
271#define __check_align_2 \
272 " _bbci.l %3, 0, 1f \n" \
273 " movi %0, %4 \n" \
274 " _j 2f \n"
275
276#define __check_align_4 \
277 " _bbsi.l %3, 0, 0f \n" \
278 " _bbci.l %3, 1, 1f \n" \
279 "0: movi %0, %4 \n" \
280 " _j 2f \n"
281
282
283/*
284 * We don't tell gcc that we are accessing memory, but this is OK
285 * because we do not write to any memory gcc knows about, so there
286 * are no aliasing issues.
287 *
288 * WARNING: If you modify this macro at all, verify that the
289 * __check_align_* macros still work.
290 */
291#define __put_user_asm(x, addr, err, align, insn, cb) \
292 __asm__ __volatile__( \
293 __check_align_##align \
294 "1: "insn" %2, %3, 0 \n" \
295 "2: \n" \
296 " .section .fixup,\"ax\" \n" \
297 " .align 4 \n" \
298 "4: \n" \
299 " .long 2b \n" \
300 "5: \n" \
301 " l32r %1, 4b \n" \
302 " movi %0, %4 \n" \
303 " jx %1 \n" \
304 " .previous \n" \
305 " .section __ex_table,\"a\" \n" \
306 " .long 1b, 5b \n" \
307 " .previous" \
308 :"=r" (err), "=r" (cb) \
309 :"r" ((int)(x)), "r" (addr), "i" (-EFAULT), "0" (err))
310
311#define __get_user_nocheck(x,ptr,size) \
312({ \
313 long __gu_err, __gu_val; \
314 __get_user_size(__gu_val,(ptr),(size),__gu_err); \
315 (x) = (__typeof__(*(ptr)))__gu_val; \
316 __gu_err; \
317})
318
319#define __get_user_check(x,ptr,size) \
320({ \
321 long __gu_err = -EFAULT, __gu_val = 0; \
322 const __typeof__(*(ptr)) *__gu_addr = (ptr); \
323 if (access_ok(VERIFY_READ,__gu_addr,size)) \
324 __get_user_size(__gu_val,__gu_addr,(size),__gu_err); \
325 (x) = (__typeof__(*(ptr)))__gu_val; \
326 __gu_err; \
327})
328
329extern long __get_user_bad(void);
330
331#define __get_user_size(x,ptr,size,retval) \
332do { \
333 int __cb; \
334 retval = 0; \
335 switch (size) { \
336 case 1: __get_user_asm(x,ptr,retval,1,"l8ui",__cb); break; \
337 case 2: __get_user_asm(x,ptr,retval,2,"l16ui",__cb); break; \
338 case 4: __get_user_asm(x,ptr,retval,4,"l32i",__cb); break; \
339 case 8: retval = __copy_from_user(&x,ptr,8); break; \
340 default: (x) = __get_user_bad(); \
341 } \
342} while (0)
343
344
345/*
346 * WARNING: If you modify this macro at all, verify that the
347 * __check_align_* macros still work.
348 */
349#define __get_user_asm(x, addr, err, align, insn, cb) \
350 __asm__ __volatile__( \
351 __check_align_##align \
352 "1: "insn" %2, %3, 0 \n" \
353 "2: \n" \
354 " .section .fixup,\"ax\" \n" \
355 " .align 4 \n" \
356 "4: \n" \
357 " .long 2b \n" \
358 "5: \n" \
359 " l32r %1, 4b \n" \
360 " movi %2, 0 \n" \
361 " movi %0, %4 \n" \
362 " jx %1 \n" \
363 " .previous \n" \
364 " .section __ex_table,\"a\" \n" \
365 " .long 1b, 5b \n" \
366 " .previous" \
367 :"=r" (err), "=r" (cb), "=r" (x) \
368 :"r" (addr), "i" (-EFAULT), "0" (err))
369
370
371/*
372 * Copy to/from user space
373 */
374
375/*
376 * We use a generic, arbitrary-sized copy subroutine. The Xtensa
377 * architecture would cause heavy code bloat if we tried to inline
378 * these functions and provide __constant_copy_* equivalents like the
379 * i386 versions. __xtensa_copy_user is quite efficient. See the
380 * .fixup section of __xtensa_copy_user for a discussion on the
381 * X_zeroing equivalents for Xtensa.
382 */
383
384extern unsigned __xtensa_copy_user(void *to, const void *from, unsigned n);
385#define __copy_user(to,from,size) __xtensa_copy_user(to,from,size)
386
387
388static inline unsigned long
389__generic_copy_from_user_nocheck(void *to, const void *from, unsigned long n)
390{
391 return __copy_user(to,from,n);
392}
393
394static inline unsigned long
395__generic_copy_to_user_nocheck(void *to, const void *from, unsigned long n)
396{
397 return __copy_user(to,from,n);
398}
399
400static inline unsigned long
401__generic_copy_to_user(void *to, const void *from, unsigned long n)
402{
403 prefetch(from);
404 if (access_ok(VERIFY_WRITE, to, n))
405 return __copy_user(to,from,n);
406 return n;
407}
408
409static inline unsigned long
410__generic_copy_from_user(void *to, const void *from, unsigned long n)
411{
412 prefetchw(to);
413 if (access_ok(VERIFY_READ, from, n))
414 return __copy_user(to,from,n);
415 else
416 memset(to, 0, n);
417 return n;
418}
419
420#define copy_to_user(to,from,n) __generic_copy_to_user((to),(from),(n))
421#define copy_from_user(to,from,n) __generic_copy_from_user((to),(from),(n))
422#define __copy_to_user(to,from,n) __generic_copy_to_user_nocheck((to),(from),(n))
423#define __copy_from_user(to,from,n) __generic_copy_from_user_nocheck((to),(from),(n))
424#define __copy_to_user_inatomic __copy_to_user
425#define __copy_from_user_inatomic __copy_from_user
426
427
428/*
429 * We need to return the number of bytes not cleared. Our memset()
430 * returns zero if a problem occurs while accessing user-space memory.
431 * In that event, return no memory cleared. Otherwise, zero for
432 * success.
433 */
434
435static inline unsigned long
436__xtensa_clear_user(void *addr, unsigned long size)
437{
438 if ( ! memset(addr, 0, size) )
439 return size;
440 return 0;
441}
442
443static inline unsigned long
444clear_user(void *addr, unsigned long size)
445{
446 if (access_ok(VERIFY_WRITE, addr, size))
447 return __xtensa_clear_user(addr, size);
448 return size ? -EFAULT : 0;
449}
450
451#define __clear_user __xtensa_clear_user
452
453
454extern long __strncpy_user(char *, const char *, long);
455#define __strncpy_from_user __strncpy_user
456
457static inline long
458strncpy_from_user(char *dst, const char *src, long count)
459{
460 if (access_ok(VERIFY_READ, src, 1))
461 return __strncpy_from_user(dst, src, count);
462 return -EFAULT;
463}
464
465
466#define strlen_user(str) strnlen_user((str), TASK_SIZE - 1)
467
468/*
469 * Return the size of a string (including the ending 0!)
470 */
471extern long __strnlen_user(const char *, long);
472
473static inline long strnlen_user(const char *str, long len)
474{
475 unsigned long top = __kernel_ok ? ~0UL : TASK_SIZE - 1;
476
477 if ((unsigned long)str > top)
478 return 0;
479 return __strnlen_user(str, len);
480}
481
482
483struct exception_table_entry
484{
485 unsigned long insn, fixup;
486};
487
488/* Returns 0 if exception not found and fixup.unit otherwise. */
489
490extern unsigned long search_exception_table(unsigned long addr);
491extern void sort_exception_table(void);
492
493/* Returns the new pc */
494#define fixup_exception(map_reg, fixup_unit, pc) \
495({ \
496 fixup_unit; \
497})
498
499#endif /* __ASSEMBLY__ */
500#endif /* _XTENSA_UACCESS_H */
diff --git a/include/asm-xtensa/ucontext.h b/include/asm-xtensa/ucontext.h
deleted file mode 100644
index 94c94ed3e00a..000000000000
--- a/include/asm-xtensa/ucontext.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * include/asm-xtensa/ucontext.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_UCONTEXT_H
12#define _XTENSA_UCONTEXT_H
13
14struct ucontext {
15 unsigned long uc_flags;
16 struct ucontext *uc_link;
17 stack_t uc_stack;
18 struct sigcontext uc_mcontext;
19 sigset_t uc_sigmask; /* mask last for extensibility */
20};
21
22#endif /* _XTENSA_UCONTEXT_H */
diff --git a/include/asm-xtensa/unaligned.h b/include/asm-xtensa/unaligned.h
deleted file mode 100644
index 8f3424fc5d18..000000000000
--- a/include/asm-xtensa/unaligned.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Xtensa doesn't handle unaligned accesses efficiently.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10#ifndef _ASM_XTENSA_UNALIGNED_H
11#define _ASM_XTENSA_UNALIGNED_H
12
13#ifdef __XTENSA_EL__
14# include <linux/unaligned/le_memmove.h>
15# include <linux/unaligned/be_byteshift.h>
16# include <linux/unaligned/generic.h>
17# define get_unaligned __get_unaligned_le
18# define put_unaligned __put_unaligned_le
19#elif defined(__XTENSA_EB__)
20# include <linux/unaligned/be_memmove.h>
21# include <linux/unaligned/le_byteshift.h>
22# include <linux/unaligned/generic.h>
23# define get_unaligned __get_unaligned_be
24# define put_unaligned __put_unaligned_be
25#else
26# error processor byte order undefined!
27#endif
28
29#endif /* _ASM_XTENSA_UNALIGNED_H */
diff --git a/include/asm-xtensa/unistd.h b/include/asm-xtensa/unistd.h
deleted file mode 100644
index c092c8fbb2cf..000000000000
--- a/include/asm-xtensa/unistd.h
+++ /dev/null
@@ -1,735 +0,0 @@
1/*
2 * include/asm-xtensa/unistd.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_UNISTD_H
12#define _XTENSA_UNISTD_H
13
14#ifndef __SYSCALL
15# define __SYSCALL(nr,func,nargs)
16#endif
17
18#define __NR_spill 0
19__SYSCALL( 0, sys_ni_syscall, 0)
20#define __NR_xtensa 1
21__SYSCALL( 1, sys_ni_syscall, 0)
22#define __NR_available4 2
23__SYSCALL( 2, sys_ni_syscall, 0)
24#define __NR_available5 3
25__SYSCALL( 3, sys_ni_syscall, 0)
26#define __NR_available6 4
27__SYSCALL( 4, sys_ni_syscall, 0)
28#define __NR_available7 5
29__SYSCALL( 5, sys_ni_syscall, 0)
30#define __NR_available8 6
31__SYSCALL( 6, sys_ni_syscall, 0)
32#define __NR_available9 7
33__SYSCALL( 7, sys_ni_syscall, 0)
34
35/* File Operations */
36
37#define __NR_open 8
38__SYSCALL( 8, sys_open, 3)
39#define __NR_close 9
40__SYSCALL( 9, sys_close, 1)
41#define __NR_dup 10
42__SYSCALL( 10, sys_dup, 1)
43#define __NR_dup2 11
44__SYSCALL( 11, sys_dup2, 2)
45#define __NR_read 12
46__SYSCALL( 12, sys_read, 3)
47#define __NR_write 13
48__SYSCALL( 13, sys_write, 3)
49#define __NR_select 14
50__SYSCALL( 14, sys_select, 5)
51#define __NR_lseek 15
52__SYSCALL( 15, sys_lseek, 3)
53#define __NR_poll 16
54__SYSCALL( 16, sys_poll, 3)
55#define __NR__llseek 17
56__SYSCALL( 17, sys_llseek, 5)
57#define __NR_epoll_wait 18
58__SYSCALL( 18, sys_epoll_wait, 4)
59#define __NR_epoll_ctl 19
60__SYSCALL( 19, sys_epoll_ctl, 4)
61#define __NR_epoll_create 20
62__SYSCALL( 20, sys_epoll_create, 1)
63#define __NR_creat 21
64__SYSCALL( 21, sys_creat, 2)
65#define __NR_truncate 22
66__SYSCALL( 22, sys_truncate, 2)
67#define __NR_ftruncate 23
68__SYSCALL( 23, sys_ftruncate, 2)
69#define __NR_readv 24
70__SYSCALL( 24, sys_readv, 3)
71#define __NR_writev 25
72__SYSCALL( 25, sys_writev, 3)
73#define __NR_fsync 26
74__SYSCALL( 26, sys_fsync, 1)
75#define __NR_fdatasync 27
76__SYSCALL( 27, sys_fdatasync, 1)
77#define __NR_truncate64 28
78__SYSCALL( 28, sys_truncate64, 2)
79#define __NR_ftruncate64 29
80__SYSCALL( 29, sys_ftruncate64, 2)
81#define __NR_pread64 30
82__SYSCALL( 30, sys_pread64, 6)
83#define __NR_pwrite64 31
84__SYSCALL( 31, sys_pwrite64, 6)
85
86#define __NR_link 32
87__SYSCALL( 32, sys_link, 2)
88#define __NR_rename 33
89__SYSCALL( 33, sys_rename, 2)
90#define __NR_symlink 34
91__SYSCALL( 34, sys_symlink, 2)
92#define __NR_readlink 35
93__SYSCALL( 35, sys_readlink, 3)
94#define __NR_mknod 36
95__SYSCALL( 36, sys_mknod, 3)
96#define __NR_pipe 37
97__SYSCALL( 37, xtensa_pipe, 1)
98#define __NR_unlink 38
99__SYSCALL( 38, sys_unlink, 1)
100#define __NR_rmdir 39
101__SYSCALL( 39, sys_rmdir, 1)
102
103#define __NR_mkdir 40
104__SYSCALL( 40, sys_mkdir, 2)
105#define __NR_chdir 41
106__SYSCALL( 41, sys_chdir, 1)
107#define __NR_fchdir 42
108__SYSCALL( 42, sys_fchdir, 1)
109#define __NR_getcwd 43
110__SYSCALL( 43, sys_getcwd, 2)
111
112#define __NR_chmod 44
113__SYSCALL( 44, sys_chmod, 2)
114#define __NR_chown 45
115__SYSCALL( 45, sys_chown, 3)
116#define __NR_stat 46
117__SYSCALL( 46, sys_newstat, 2)
118#define __NR_stat64 47
119__SYSCALL( 47, sys_stat64, 2)
120
121#define __NR_lchown 48
122__SYSCALL( 48, sys_lchown, 3)
123#define __NR_lstat 49
124__SYSCALL( 49, sys_newlstat, 2)
125#define __NR_lstat64 50
126__SYSCALL( 50, sys_lstat64, 2)
127#define __NR_available51 51
128__SYSCALL( 51, sys_ni_syscall, 0)
129
130#define __NR_fchmod 52
131__SYSCALL( 52, sys_fchmod, 2)
132#define __NR_fchown 53
133__SYSCALL( 53, sys_fchown, 3)
134#define __NR_fstat 54
135__SYSCALL( 54, sys_newfstat, 2)
136#define __NR_fstat64 55
137__SYSCALL( 55, sys_fstat64, 2)
138
139#define __NR_flock 56
140__SYSCALL( 56, sys_flock, 2)
141#define __NR_access 57
142__SYSCALL( 57, sys_access, 2)
143#define __NR_umask 58
144__SYSCALL( 58, sys_umask, 1)
145#define __NR_getdents 59
146__SYSCALL( 59, sys_getdents, 3)
147#define __NR_getdents64 60
148__SYSCALL( 60, sys_getdents64, 3)
149#define __NR_fcntl64 61
150__SYSCALL( 61, sys_fcntl64, 3)
151#define __NR_available62 62
152__SYSCALL( 62, sys_ni_syscall, 0)
153#define __NR_fadvise64_64 63
154__SYSCALL( 63, xtensa_fadvise64_64, 6)
155#define __NR_utime 64 /* glibc 2.3.3 ?? */
156__SYSCALL( 64, sys_utime, 2)
157#define __NR_utimes 65
158__SYSCALL( 65, sys_utimes, 2)
159#define __NR_ioctl 66
160__SYSCALL( 66, sys_ioctl, 3)
161#define __NR_fcntl 67
162__SYSCALL( 67, sys_fcntl, 3)
163
164#define __NR_setxattr 68
165__SYSCALL( 68, sys_setxattr, 5)
166#define __NR_getxattr 69
167__SYSCALL( 69, sys_getxattr, 4)
168#define __NR_listxattr 70
169__SYSCALL( 70, sys_listxattr, 3)
170#define __NR_removexattr 71
171__SYSCALL( 71, sys_removexattr, 2)
172#define __NR_lsetxattr 72
173__SYSCALL( 72, sys_lsetxattr, 5)
174#define __NR_lgetxattr 73
175__SYSCALL( 73, sys_lgetxattr, 4)
176#define __NR_llistxattr 74
177__SYSCALL( 74, sys_llistxattr, 3)
178#define __NR_lremovexattr 75
179__SYSCALL( 75, sys_lremovexattr, 2)
180#define __NR_fsetxattr 76
181__SYSCALL( 76, sys_fsetxattr, 5)
182#define __NR_fgetxattr 77
183__SYSCALL( 77, sys_fgetxattr, 4)
184#define __NR_flistxattr 78
185__SYSCALL( 78, sys_flistxattr, 3)
186#define __NR_fremovexattr 79
187__SYSCALL( 79, sys_fremovexattr, 2)
188
189/* File Map / Shared Memory Operations */
190
191#define __NR_mmap2 80
192__SYSCALL( 80, xtensa_mmap2, 6)
193#define __NR_munmap 81
194__SYSCALL( 81, sys_munmap, 2)
195#define __NR_mprotect 82
196__SYSCALL( 82, sys_mprotect, 3)
197#define __NR_brk 83
198__SYSCALL( 83, sys_brk, 1)
199#define __NR_mlock 84
200__SYSCALL( 84, sys_mlock, 2)
201#define __NR_munlock 85
202__SYSCALL( 85, sys_munlock, 2)
203#define __NR_mlockall 86
204__SYSCALL( 86, sys_mlockall, 1)
205#define __NR_munlockall 87
206__SYSCALL( 87, sys_munlockall, 0)
207#define __NR_mremap 88
208__SYSCALL( 88, sys_mremap, 4)
209#define __NR_msync 89
210__SYSCALL( 89, sys_msync, 3)
211#define __NR_mincore 90
212__SYSCALL( 90, sys_mincore, 3)
213#define __NR_madvise 91
214__SYSCALL( 91, sys_madvise, 3)
215#define __NR_shmget 92
216__SYSCALL( 92, sys_shmget, 4)
217#define __NR_shmat 93
218__SYSCALL( 93, xtensa_shmat, 4)
219#define __NR_shmctl 94
220__SYSCALL( 94, sys_shmctl, 4)
221#define __NR_shmdt 95
222__SYSCALL( 95, sys_shmdt, 4)
223
224/* Socket Operations */
225
226#define __NR_socket 96
227__SYSCALL( 96, sys_socket, 3)
228#define __NR_setsockopt 97
229__SYSCALL( 97, sys_setsockopt, 5)
230#define __NR_getsockopt 98
231__SYSCALL( 98, sys_getsockopt, 5)
232#define __NR_shutdown 99
233__SYSCALL( 99, sys_shutdown, 2)
234
235#define __NR_bind 100
236__SYSCALL(100, sys_bind, 3)
237#define __NR_connect 101
238__SYSCALL(101, sys_connect, 3)
239#define __NR_listen 102
240__SYSCALL(102, sys_listen, 2)
241#define __NR_accept 103
242__SYSCALL(103, sys_accept, 3)
243
244#define __NR_getsockname 104
245__SYSCALL(104, sys_getsockname, 3)
246#define __NR_getpeername 105
247__SYSCALL(105, sys_getpeername, 3)
248#define __NR_sendmsg 106
249__SYSCALL(106, sys_sendmsg, 3)
250#define __NR_recvmsg 107
251__SYSCALL(107, sys_recvmsg, 3)
252#define __NR_send 108
253__SYSCALL(108, sys_send, 4)
254#define __NR_recv 109
255__SYSCALL(109, sys_recv, 4)
256#define __NR_sendto 110
257__SYSCALL(110, sys_sendto, 6)
258#define __NR_recvfrom 111
259__SYSCALL(111, sys_recvfrom, 6)
260
261#define __NR_socketpair 112
262__SYSCALL(112, sys_socketpair, 4)
263#define __NR_sendfile 113
264__SYSCALL(113, sys_sendfile, 4)
265#define __NR_sendfile64 114
266__SYSCALL(114, sys_sendfile64, 4)
267#define __NR_available115 115
268__SYSCALL(115, sys_ni_syscall, 0)
269
270/* Process Operations */
271
272#define __NR_clone 116
273__SYSCALL(116, xtensa_clone, 5)
274#define __NR_execve 117
275__SYSCALL(117, xtensa_execve, 3)
276#define __NR_exit 118
277__SYSCALL(118, sys_exit, 1)
278#define __NR_exit_group 119
279__SYSCALL(119, sys_exit_group, 1)
280#define __NR_getpid 120
281__SYSCALL(120, sys_getpid, 0)
282#define __NR_wait4 121
283__SYSCALL(121, sys_wait4, 4)
284#define __NR_waitid 122
285__SYSCALL(122, sys_waitid, 5)
286#define __NR_kill 123
287__SYSCALL(123, sys_kill, 2)
288#define __NR_tkill 124
289__SYSCALL(124, sys_tkill, 2)
290#define __NR_tgkill 125
291__SYSCALL(125, sys_tgkill, 3)
292#define __NR_set_tid_address 126
293__SYSCALL(126, sys_set_tid_address, 1)
294#define __NR_gettid 127
295__SYSCALL(127, sys_gettid, 0)
296#define __NR_setsid 128
297__SYSCALL(128, sys_setsid, 0)
298#define __NR_getsid 129
299__SYSCALL(129, sys_getsid, 1)
300#define __NR_prctl 130
301__SYSCALL(130, sys_prctl, 5)
302#define __NR_personality 131
303__SYSCALL(131, sys_personality, 1)
304#define __NR_getpriority 132
305__SYSCALL(132, sys_getpriority, 2)
306#define __NR_setpriority 133
307__SYSCALL(133, sys_setpriority, 3)
308#define __NR_setitimer 134
309__SYSCALL(134, sys_setitimer, 3)
310#define __NR_getitimer 135
311__SYSCALL(135, sys_getitimer, 2)
312#define __NR_setuid 136
313__SYSCALL(136, sys_setuid, 1)
314#define __NR_getuid 137
315__SYSCALL(137, sys_getuid, 0)
316#define __NR_setgid 138
317__SYSCALL(138, sys_setgid, 1)
318#define __NR_getgid 139
319__SYSCALL(139, sys_getgid, 0)
320#define __NR_geteuid 140
321__SYSCALL(140, sys_geteuid, 0)
322#define __NR_getegid 141
323__SYSCALL(141, sys_getegid, 0)
324#define __NR_setreuid 142
325__SYSCALL(142, sys_setreuid, 2)
326#define __NR_setregid 143
327__SYSCALL(143, sys_setregid, 2)
328#define __NR_setresuid 144
329__SYSCALL(144, sys_setresuid, 3)
330#define __NR_getresuid 145
331__SYSCALL(145, sys_getresuid, 3)
332#define __NR_setresgid 146
333__SYSCALL(146, sys_setresgid, 3)
334#define __NR_getresgid 147
335__SYSCALL(147, sys_getresgid, 3)
336#define __NR_setpgid 148
337__SYSCALL(148, sys_setpgid, 2)
338#define __NR_getpgid 149
339__SYSCALL(149, sys_getpgid, 1)
340#define __NR_getppid 150
341__SYSCALL(150, sys_getppid, 0)
342#define __NR_getpgrp 151
343__SYSCALL(151, sys_getpgrp, 0)
344
345#define __NR_reserved152 152 /* set_thread_area */
346__SYSCALL(152, sys_ni_syscall, 0)
347#define __NR_reserved153 153 /* get_thread_area */
348__SYSCALL(153, sys_ni_syscall, 0)
349#define __NR_times 154
350__SYSCALL(154, sys_times, 1)
351#define __NR_acct 155
352__SYSCALL(155, sys_acct, 1)
353#define __NR_sched_setaffinity 156
354__SYSCALL(156, sys_sched_setaffinity, 3)
355#define __NR_sched_getaffinity 157
356__SYSCALL(157, sys_sched_getaffinity, 3)
357#define __NR_capget 158
358__SYSCALL(158, sys_capget, 2)
359#define __NR_capset 159
360__SYSCALL(159, sys_capset, 2)
361#define __NR_ptrace 160
362__SYSCALL(160, sys_ptrace, 4)
363#define __NR_semtimedop 161
364__SYSCALL(161, sys_semtimedop, 5)
365#define __NR_semget 162
366__SYSCALL(162, sys_semget, 4)
367#define __NR_semop 163
368__SYSCALL(163, sys_semop, 4)
369#define __NR_semctl 164
370__SYSCALL(164, sys_semctl, 4)
371#define __NR_available165 165
372__SYSCALL(165, sys_ni_syscall, 0)
373#define __NR_msgget 166
374__SYSCALL(166, sys_msgget, 4)
375#define __NR_msgsnd 167
376__SYSCALL(167, sys_msgsnd, 4)
377#define __NR_msgrcv 168
378__SYSCALL(168, sys_msgrcv, 4)
379#define __NR_msgctl 169
380__SYSCALL(169, sys_msgctl, 4)
381#define __NR_available170 170
382__SYSCALL(170, sys_ni_syscall, 0)
383#define __NR_available171 171
384__SYSCALL(171, sys_ni_syscall, 0)
385
386/* File System */
387
388#define __NR_mount 172
389__SYSCALL(172, sys_mount, 5)
390#define __NR_swapon 173
391__SYSCALL(173, sys_swapon, 2)
392#define __NR_chroot 174
393__SYSCALL(174, sys_chroot, 1)
394#define __NR_pivot_root 175
395__SYSCALL(175, sys_pivot_root, 2)
396#define __NR_umount 176
397__SYSCALL(176, sys_umount, 2)
398#define __NR_swapoff 177
399__SYSCALL(177, sys_swapoff, 1)
400#define __NR_sync 178
401__SYSCALL(178, sys_sync, 0)
402#define __NR_available179 179
403__SYSCALL(179, sys_ni_syscall, 0)
404#define __NR_setfsuid 180
405__SYSCALL(180, sys_setfsuid, 1)
406#define __NR_setfsgid 181
407__SYSCALL(181, sys_setfsgid, 1)
408#define __NR_sysfs 182
409__SYSCALL(182, sys_sysfs, 3)
410#define __NR_ustat 183
411__SYSCALL(183, sys_ustat, 2)
412#define __NR_statfs 184
413__SYSCALL(184, sys_statfs, 2)
414#define __NR_fstatfs 185
415__SYSCALL(185, sys_fstatfs, 2)
416#define __NR_statfs64 186
417__SYSCALL(186, sys_statfs64, 3)
418#define __NR_fstatfs64 187
419__SYSCALL(187, sys_fstatfs64, 3)
420
421/* System */
422
423#define __NR_setrlimit 188
424__SYSCALL(188, sys_setrlimit, 2)
425#define __NR_getrlimit 189
426__SYSCALL(189, sys_getrlimit, 2)
427#define __NR_getrusage 190
428__SYSCALL(190, sys_getrusage, 2)
429#define __NR_futex 191
430__SYSCALL(191, sys_futex, 5)
431#define __NR_gettimeofday 192
432__SYSCALL(192, sys_gettimeofday, 2)
433#define __NR_settimeofday 193
434__SYSCALL(193, sys_settimeofday, 2)
435#define __NR_adjtimex 194
436__SYSCALL(194, sys_adjtimex, 1)
437#define __NR_nanosleep 195
438__SYSCALL(195, sys_nanosleep, 2)
439#define __NR_getgroups 196
440__SYSCALL(196, sys_getgroups, 2)
441#define __NR_setgroups 197
442__SYSCALL(197, sys_setgroups, 2)
443#define __NR_sethostname 198
444__SYSCALL(198, sys_sethostname, 2)
445#define __NR_setdomainname 199
446__SYSCALL(199, sys_setdomainname, 2)
447#define __NR_syslog 200
448__SYSCALL(200, sys_syslog, 3)
449#define __NR_vhangup 201
450__SYSCALL(201, sys_vhangup, 0)
451#define __NR_uselib 202
452__SYSCALL(202, sys_uselib, 1)
453#define __NR_reboot 203
454__SYSCALL(203, sys_reboot, 3)
455#define __NR_quotactl 204
456__SYSCALL(204, sys_quotactl, 4)
457#define __NR_nfsservctl 205
458__SYSCALL(205, sys_nfsservctl, 3)
459#define __NR__sysctl 206
460__SYSCALL(206, sys_sysctl, 1)
461#define __NR_bdflush 207
462__SYSCALL(207, sys_bdflush, 2)
463#define __NR_uname 208
464__SYSCALL(208, sys_newuname, 1)
465#define __NR_sysinfo 209
466__SYSCALL(209, sys_sysinfo, 1)
467#define __NR_init_module 210
468__SYSCALL(210, sys_init_module, 2)
469#define __NR_delete_module 211
470__SYSCALL(211, sys_delete_module, 1)
471
472#define __NR_sched_setparam 212
473__SYSCALL(212, sys_sched_setparam, 2)
474#define __NR_sched_getparam 213
475__SYSCALL(213, sys_sched_getparam, 2)
476#define __NR_sched_setscheduler 214
477__SYSCALL(214, sys_sched_setscheduler, 3)
478#define __NR_sched_getscheduler 215
479__SYSCALL(215, sys_sched_getscheduler, 1)
480#define __NR_sched_get_priority_max 216
481__SYSCALL(216, sys_sched_get_priority_max, 1)
482#define __NR_sched_get_priority_min 217
483__SYSCALL(217, sys_sched_get_priority_min, 1)
484#define __NR_sched_rr_get_interval 218
485__SYSCALL(218, sys_sched_rr_get_interval, 2)
486#define __NR_sched_yield 219
487__SYSCALL(219, sys_sched_yield, 0)
488#define __NR_available222 222
489__SYSCALL(222, sys_ni_syscall, 0)
490
491/* Signal Handling */
492
493#define __NR_restart_syscall 223
494__SYSCALL(223, sys_restart_syscall, 0)
495#define __NR_sigaltstack 224
496__SYSCALL(224, xtensa_sigaltstack, 2)
497#define __NR_rt_sigreturn 225
498__SYSCALL(225, xtensa_rt_sigreturn, 1)
499#define __NR_rt_sigaction 226
500__SYSCALL(226, sys_rt_sigaction, 4)
501#define __NR_rt_sigprocmask 227
502__SYSCALL(227, sys_rt_sigprocmask, 4)
503#define __NR_rt_sigpending 228
504__SYSCALL(228, sys_rt_sigpending, 2)
505#define __NR_rt_sigtimedwait 229
506__SYSCALL(229, sys_rt_sigtimedwait, 4)
507#define __NR_rt_sigqueueinfo 230
508__SYSCALL(230, sys_rt_sigqueueinfo, 3)
509#define __NR_rt_sigsuspend 231
510__SYSCALL(231, xtensa_rt_sigsuspend, 2)
511
512/* Message */
513
514#define __NR_mq_open 232
515__SYSCALL(232, sys_mq_open, 4)
516#define __NR_mq_unlink 233
517__SYSCALL(233, sys_mq_unlink, 1)
518#define __NR_mq_timedsend 234
519__SYSCALL(234, sys_mq_timedsend, 5)
520#define __NR_mq_timedreceive 235
521__SYSCALL(235, sys_mq_timedreceive, 5)
522#define __NR_mq_notify 236
523__SYSCALL(236, sys_mq_notify, 2)
524#define __NR_mq_getsetattr 237
525__SYSCALL(237, sys_mq_getsetattr, 3)
526#define __NR_available238 238
527__SYSCALL(238, sys_ni_syscall, 0)
528
529/* IO */
530
531#define __NR_io_setup 239
532__SYSCALL(239, sys_io_setup, 2)
533#define __NR_io_destroy 240
534__SYSCALL(240, sys_io_destroy, 1)
535#define __NR_io_submit 241
536__SYSCALL(241, sys_io_submit, 3)
537#define __NR_io_getevents 242
538__SYSCALL(242, sys_io_getevents, 5)
539#define __NR_io_cancel 243
540__SYSCALL(243, sys_io_cancel, 3)
541#define __NR_clock_settime 244
542__SYSCALL(244, sys_clock_settime, 2)
543#define __NR_clock_gettime 245
544__SYSCALL(245, sys_clock_gettime, 2)
545#define __NR_clock_getres 246
546__SYSCALL(246, sys_clock_getres, 2)
547#define __NR_clock_nanosleep 247
548__SYSCALL(247, sys_clock_nanosleep, 4)
549
550/* Timer */
551
552#define __NR_timer_create 248
553__SYSCALL(248, sys_timer_create, 3)
554#define __NR_timer_delete 249
555__SYSCALL(249, sys_timer_delete, 1)
556#define __NR_timer_settime 250
557__SYSCALL(250, sys_timer_settime, 4)
558#define __NR_timer_gettime 251
559__SYSCALL(251, sys_timer_gettime, 2)
560#define __NR_timer_getoverrun 252
561__SYSCALL(252, sys_timer_getoverrun, 1)
562
563/* System */
564
565#define __NR_reserved244 253
566__SYSCALL(253, sys_ni_syscall, 0)
567#define __NR_lookup_dcookie 254
568__SYSCALL(254, sys_lookup_dcookie, 4)
569#define __NR_available255 255
570__SYSCALL(255, sys_ni_syscall, 0)
571#define __NR_add_key 256
572__SYSCALL(256, sys_add_key, 5)
573#define __NR_request_key 257
574__SYSCALL(257, sys_request_key, 5)
575#define __NR_keyctl 258
576__SYSCALL(258, sys_keyctl, 5)
577#define __NR_available259 259
578__SYSCALL(259, sys_ni_syscall, 0)
579
580
581#define __NR_readahead 260
582__SYSCALL(260, sys_readahead, 5)
583#define __NR_remap_file_pages 261
584__SYSCALL(261, sys_remap_file_pages, 5)
585#define __NR_migrate_pages 262
586__SYSCALL(262, sys_migrate_pages, 0)
587#define __NR_mbind 263
588__SYSCALL(263, sys_mbind, 6)
589#define __NR_get_mempolicy 264
590__SYSCALL(264, sys_get_mempolicy, 5)
591#define __NR_set_mempolicy 265
592__SYSCALL(265, sys_set_mempolicy, 3)
593#define __NR_unshare 266
594__SYSCALL(266, sys_unshare, 1)
595#define __NR_move_pages 267
596__SYSCALL(267, sys_move_pages, 0)
597#define __NR_splice 268
598__SYSCALL(268, sys_splice, 0)
599#define __NR_tee 269
600__SYSCALL(269, sys_tee, 0)
601#define __NR_vmsplice 270
602__SYSCALL(270, sys_vmsplice, 0)
603#define __NR_available271 271
604__SYSCALL(271, sys_ni_syscall, 0)
605
606#define __NR_pselect6 272
607__SYSCALL(272, sys_pselect6, 0)
608#define __NR_ppoll 273
609__SYSCALL(273, sys_ppoll, 0)
610#define __NR_epoll_pwait 274
611__SYSCALL(274, sys_epoll_pwait, 0)
612#define __NR_available275 275
613__SYSCALL(275, sys_ni_syscall, 0)
614
615#define __NR_inotify_init 276
616__SYSCALL(276, sys_inotify_init, 0)
617#define __NR_inotify_add_watch 277
618__SYSCALL(277, sys_inotify_add_watch, 3)
619#define __NR_inotify_rm_watch 278
620__SYSCALL(278, sys_inotify_rm_watch, 2)
621#define __NR_available279 279
622__SYSCALL(279, sys_ni_syscall, 0)
623
624#define __NR_getcpu 280
625__SYSCALL(280, sys_getcpu, 0)
626#define __NR_kexec_load 281
627__SYSCALL(281, sys_ni_syscall, 0)
628
629#define __NR_ioprio_set 282
630__SYSCALL(282, sys_ioprio_set, 2)
631#define __NR_ioprio_get 283
632__SYSCALL(283, sys_ioprio_get, 3)
633
634#define __NR_set_robust_list 284
635__SYSCALL(284, sys_set_robust_list, 3)
636#define __NR_get_robust_list 285
637__SYSCALL(285, sys_get_robust_list, 3)
638#define __NR_reserved286 286 /* sync_file_rangeX */
639__SYSCALL(286, sys_ni_syscall, 3)
640#define __NR_available287 287
641__SYSCALL(287, sys_faccessat, 0)
642
643/* Relative File Operations */
644
645#define __NR_openat 288
646__SYSCALL(288, sys_openat, 4)
647#define __NR_mkdirat 289
648__SYSCALL(289, sys_mkdirat, 3)
649#define __NR_mknodat 290
650__SYSCALL(290, sys_mknodat, 4)
651#define __NR_unlinkat 291
652__SYSCALL(291, sys_unlinkat, 3)
653#define __NR_renameat 292
654__SYSCALL(292, sys_renameat, 4)
655#define __NR_linkat 293
656__SYSCALL(293, sys_linkat, 5)
657#define __NR_symlinkat 294
658__SYSCALL(294, sys_symlinkat, 3)
659#define __NR_readlinkat 295
660__SYSCALL(295, sys_readlinkat, 4)
661#define __NR_utimensat 296
662__SYSCALL(296, sys_utimensat, 0)
663#define __NR_fchownat 297
664__SYSCALL(297, sys_fchownat, 5)
665#define __NR_futimesat 298
666__SYSCALL(298, sys_futimesat, 4)
667#define __NR_fstatat64 299
668__SYSCALL(299, sys_fstatat64, 0)
669#define __NR_fchmodat 300
670__SYSCALL(300, sys_fchmodat, 4)
671#define __NR_faccessat 301
672__SYSCALL(301, sys_faccessat, 4)
673#define __NR_available302 302
674__SYSCALL(302, sys_ni_syscall, 0)
675#define __NR_available303 303
676__SYSCALL(303, sys_ni_syscall, 0)
677
678#define __NR_signalfd 304
679__SYSCALL(304, sys_signalfd, 3)
680/* 305 was __NR_timerfd */
681__SYSCALL(305, sys_ni_syscall, 0)
682#define __NR_eventfd 306
683__SYSCALL(306, sys_eventfd, 1)
684
685#define __NR_syscall_count 307
686
687/*
688 * sysxtensa syscall handler
689 *
690 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
691 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
692 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
693 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
694 * a2 a6 a3 a4 a5
695 */
696
697#define SYS_XTENSA_RESERVED 0 /* don't use this */
698#define SYS_XTENSA_ATOMIC_SET 1 /* set variable */
699#define SYS_XTENSA_ATOMIC_EXG_ADD 2 /* exchange memory and add */
700#define SYS_XTENSA_ATOMIC_ADD 3 /* add to memory */
701#define SYS_XTENSA_ATOMIC_CMP_SWP 4 /* compare and swap */
702
703#define SYS_XTENSA_COUNT 5 /* count */
704
705#ifdef __KERNEL__
706
707/*
708 * "Conditional" syscalls
709 *
710 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
711 * but it doesn't work on all toolchains, so we just do it by hand
712 */
713#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
714
715#define __ARCH_WANT_STAT64
716#define __ARCH_WANT_SYS_UTIME
717#define __ARCH_WANT_SYS_LLSEEK
718#define __ARCH_WANT_SYS_RT_SIGACTION
719#define __ARCH_WANT_SYS_RT_SIGSUSPEND
720#define __ARCH_WANT_SYS_GETPGRP
721
722/*
723 * Ignore legacy system calls in the checksyscalls.sh script
724 */
725
726#define __IGNORE_fork /* use clone */
727#define __IGNORE_time
728#define __IGNORE_alarm /* use setitimer */
729#define __IGNORE_pause
730#define __IGNORE_mmap /* use mmap2 */
731#define __IGNORE_vfork /* use clone */
732#define __IGNORE_fadvise64 /* use fadvise64_64 */
733
734#endif /* __KERNEL__ */
735#endif /* _XTENSA_UNISTD_H */
diff --git a/include/asm-xtensa/user.h b/include/asm-xtensa/user.h
deleted file mode 100644
index 2c3ed23354a8..000000000000
--- a/include/asm-xtensa/user.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * include/asm-xtensa/user.h
3 *
4 * Xtensa Processor version.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_USER_H
14#define _XTENSA_USER_H
15
16/* This file usually defines a 'struct user' structure. However, it it only
17 * used for a.out file, which are not supported on Xtensa.
18 */
19
20#endif /* _XTENSA_USER_H */
diff --git a/include/asm-xtensa/variant-dc232b/core.h b/include/asm-xtensa/variant-dc232b/core.h
deleted file mode 100644
index 525bd3d90154..000000000000
--- a/include/asm-xtensa/variant-dc232b/core.h
+++ /dev/null
@@ -1,424 +0,0 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1999-2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CORE_CONFIGURATION_H
12#define _XTENSA_CORE_CONFIGURATION_H
13
14
15/****************************************************************************
16 Parameters Useful for Any Code, USER or PRIVILEGED
17 ****************************************************************************/
18
19/*
20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21 * configured, and a value of 0 otherwise. These macros are always defined.
22 */
23
24
25/*----------------------------------------------------------------------
26 ISA
27 ----------------------------------------------------------------------*/
28
29#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
32#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
33#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
34#define XCHAL_HAVE_DEBUG 1 /* debug option */
35#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
39#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
40#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
41#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
42#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
44#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
45#define XCHAL_HAVE_L32R 1 /* L32R instruction */
46#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
49#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
50#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
51#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
52#define XCHAL_HAVE_ABS 1 /* ABS instruction */
53/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
54/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
55#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
56#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
57#define XCHAL_HAVE_SPECULATION 0 /* speculation */
58#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
59#define XCHAL_NUM_CONTEXTS 1 /* */
60#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
61#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
62#define XCHAL_HAVE_PRID 1 /* processor ID register */
63#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
64#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
65#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
67#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
68#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
69#define XCHAL_HAVE_FP 0 /* floating point pkg */
70#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
71#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
72#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
73
74
75/*----------------------------------------------------------------------
76 MISC
77 ----------------------------------------------------------------------*/
78
79#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
80#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
81#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
82/* In T1050, applies to selected core load and store instructions (see ISA): */
83#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
84#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
85
86#define XCHAL_SW_VERSION 701001 /* sw version of this header */
87
88#define XCHAL_CORE_ID "dc232b" /* alphanum core name
89 (CoreID) set in the Xtensa
90 Processor Generator */
91
92#define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)"
93#define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */
94
95/*
96 * These definitions describe the hardware targeted by this software.
97 */
98#define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/
99#define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/
100#define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */
101#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */
102#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
103#define XCHAL_HW_VERSION 221001 /* major*100+minor */
104#define XCHAL_HW_REL_LX2 1
105#define XCHAL_HW_REL_LX2_1 1
106#define XCHAL_HW_REL_LX2_1_1 1
107#define XCHAL_HW_CONFIGID_RELIABLE 1
108/* If software targets a *range* of hardware versions, these are the bounds: */
109#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */
110#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
111#define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */
112#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */
113#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
114#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
115
116
117/*----------------------------------------------------------------------
118 CACHE
119 ----------------------------------------------------------------------*/
120
121#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
122#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
123#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
124#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
125
126#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
127#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
128
129#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
130
131
132
133
134/****************************************************************************
135 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
136 ****************************************************************************/
137
138
139#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
140
141/*----------------------------------------------------------------------
142 CACHE
143 ----------------------------------------------------------------------*/
144
145#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
146
147/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
148
149/* Number of cache sets in log2(lines per way): */
150#define XCHAL_ICACHE_SETWIDTH 7
151#define XCHAL_DCACHE_SETWIDTH 7
152
153/* Cache set associativity (number of ways): */
154#define XCHAL_ICACHE_WAYS 4
155#define XCHAL_DCACHE_WAYS 4
156
157/* Cache features: */
158#define XCHAL_ICACHE_LINE_LOCKABLE 1
159#define XCHAL_DCACHE_LINE_LOCKABLE 1
160#define XCHAL_ICACHE_ECC_PARITY 0
161#define XCHAL_DCACHE_ECC_PARITY 0
162
163/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
164#define XCHAL_CA_BITS 4
165
166
167/*----------------------------------------------------------------------
168 INTERNAL I/D RAM/ROMs and XLMI
169 ----------------------------------------------------------------------*/
170
171#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
172#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
173#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
174#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
176#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
177
178
179/*----------------------------------------------------------------------
180 INTERRUPTS and TIMERS
181 ----------------------------------------------------------------------*/
182
183#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
184#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
185#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
186#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
187#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
188#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
189#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
190#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
191#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
192 (not including level zero) */
193#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
194 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
195
196/* Masks of interrupts at each interrupt level: */
197#define XCHAL_INTLEVEL1_MASK 0x001F80FF
198#define XCHAL_INTLEVEL2_MASK 0x00000100
199#define XCHAL_INTLEVEL3_MASK 0x00200E00
200#define XCHAL_INTLEVEL4_MASK 0x00001000
201#define XCHAL_INTLEVEL5_MASK 0x00002000
202#define XCHAL_INTLEVEL6_MASK 0x00000000
203#define XCHAL_INTLEVEL7_MASK 0x00004000
204
205/* Masks of interrupts at each range 1..n of interrupt levels: */
206#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
207#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
208#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
209#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
210#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
211#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
212#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
213
214/* Level of each interrupt: */
215#define XCHAL_INT0_LEVEL 1
216#define XCHAL_INT1_LEVEL 1
217#define XCHAL_INT2_LEVEL 1
218#define XCHAL_INT3_LEVEL 1
219#define XCHAL_INT4_LEVEL 1
220#define XCHAL_INT5_LEVEL 1
221#define XCHAL_INT6_LEVEL 1
222#define XCHAL_INT7_LEVEL 1
223#define XCHAL_INT8_LEVEL 2
224#define XCHAL_INT9_LEVEL 3
225#define XCHAL_INT10_LEVEL 3
226#define XCHAL_INT11_LEVEL 3
227#define XCHAL_INT12_LEVEL 4
228#define XCHAL_INT13_LEVEL 5
229#define XCHAL_INT14_LEVEL 7
230#define XCHAL_INT15_LEVEL 1
231#define XCHAL_INT16_LEVEL 1
232#define XCHAL_INT17_LEVEL 1
233#define XCHAL_INT18_LEVEL 1
234#define XCHAL_INT19_LEVEL 1
235#define XCHAL_INT20_LEVEL 1
236#define XCHAL_INT21_LEVEL 3
237#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
238#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
239#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
240 EXCSAVE/EPS/EPC_n, RFI n) */
241
242/* Type of each interrupt: */
243#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
244#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
245#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
246#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
247#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
248#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
249#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
250#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
251#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
252#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
253#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
254#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
255#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
256#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
257#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
258#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
259#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
260#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
261#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
262#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
263#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
264#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
265
266/* Masks of interrupts for each type of interrupt: */
267#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
268#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
269#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
270#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
271#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
272#define XCHAL_INTTYPE_MASK_NMI 0x00004000
273#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
274
275/* Interrupt numbers assigned to specific interrupt sources: */
276#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
277#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
278#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
279#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
280#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
281
282/* Interrupt numbers for levels at which only one interrupt is configured: */
283#define XCHAL_INTLEVEL2_NUM 8
284#define XCHAL_INTLEVEL4_NUM 12
285#define XCHAL_INTLEVEL5_NUM 13
286#define XCHAL_INTLEVEL7_NUM 14
287/* (There are many interrupts each at level(s) 1, 3.) */
288
289
290/*
291 * External interrupt vectors/levels.
292 * These macros describe how Xtensa processor interrupt numbers
293 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
294 * map to external BInterrupt<n> pins, for those interrupts
295 * configured as external (level-triggered, edge-triggered, or NMI).
296 * See the Xtensa processor databook for more details.
297 */
298
299/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
300#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
301#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
302#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
303#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
304#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
305#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
306#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
307#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
308#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
309#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
310#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
311#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
312#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
313#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
314#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
315#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
316#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
317
318
319/*----------------------------------------------------------------------
320 EXCEPTIONS and VECTORS
321 ----------------------------------------------------------------------*/
322
323#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
324 number: 1 == XEA1 (old)
325 2 == XEA2 (new)
326 0 == XEAX (extern) */
327#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
328#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
329#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
330#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
331#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
332#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
333#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
334#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */
335#define XCHAL_VECBASE_RESET_PADDR 0x00000000
336#define XCHAL_RESET_VECBASE_OVERLAP 0
337
338#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
339#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
340#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500
341#define XCHAL_RESET_VECTOR1_PADDR 0x00000500
342#define XCHAL_RESET_VECTOR_VADDR 0xFE000000
343#define XCHAL_RESET_VECTOR_PADDR 0xFE000000
344#define XCHAL_USER_VECOFS 0x00000340
345#define XCHAL_USER_VECTOR_VADDR 0xD0000340
346#define XCHAL_USER_VECTOR_PADDR 0x00000340
347#define XCHAL_KERNEL_VECOFS 0x00000300
348#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300
349#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300
350#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
351#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0
352#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0
353#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
354#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
355#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
356#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
357#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
358#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
359#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
360#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
361#define XCHAL_INTLEVEL2_VECOFS 0x00000180
362#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180
363#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180
364#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
365#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0
366#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0
367#define XCHAL_INTLEVEL4_VECOFS 0x00000200
368#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200
369#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200
370#define XCHAL_INTLEVEL5_VECOFS 0x00000240
371#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240
372#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240
373#define XCHAL_INTLEVEL6_VECOFS 0x00000280
374#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280
375#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280
376#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
377#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
378#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
379#define XCHAL_NMI_VECOFS 0x000002C0
380#define XCHAL_NMI_VECTOR_VADDR 0xD00002C0
381#define XCHAL_NMI_VECTOR_PADDR 0x000002C0
382#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
383#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
384#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
385
386
387/*----------------------------------------------------------------------
388 DEBUG
389 ----------------------------------------------------------------------*/
390
391#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
392#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
393#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
394#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
395
396
397/*----------------------------------------------------------------------
398 MMU
399 ----------------------------------------------------------------------*/
400
401/* See core-matmap.h header file for more details. */
402
403#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
404#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
405#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
406#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
407#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
408#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
409#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
410 [autorefill] and protection)
411 usable for an MMU-based OS */
412/* If none of the above last 4 are set, it's a custom TLB configuration. */
413#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
414#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
415
416#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
417#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
418#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
419
420#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
421
422
423#endif /* _XTENSA_CORE_CONFIGURATION_H */
424
diff --git a/include/asm-xtensa/variant-dc232b/tie-asm.h b/include/asm-xtensa/variant-dc232b/tie-asm.h
deleted file mode 100644
index ed4f53f529db..000000000000
--- a/include/asm-xtensa/variant-dc232b/tie-asm.h
+++ /dev/null
@@ -1,122 +0,0 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2007 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (1 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-8, 4, 4
41 rsr \at1, ACCLO // MAC16 accumulator
42 rsr \at2, ACCHI
43 s32i \at1, \ptr, .Lxchal_ofs_ + 0
44 s32i \at2, \ptr, .Lxchal_ofs_ + 4
45 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
46 .endif
47 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
48 xchal_sa_align \ptr, 0, 1024-16, 4, 4
49 rsr \at1, M0 // MAC16 registers
50 rsr \at2, M1
51 s32i \at1, \ptr, .Lxchal_ofs_ + 0
52 s32i \at2, \ptr, .Lxchal_ofs_ + 4
53 rsr \at1, M2
54 rsr \at2, M3
55 s32i \at1, \ptr, .Lxchal_ofs_ + 8
56 s32i \at2, \ptr, .Lxchal_ofs_ + 12
57 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
58 .endif
59 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
60 xchal_sa_align \ptr, 0, 1024-4, 4, 4
61 rsr \at1, SCOMPARE1 // conditional store option
62 s32i \at1, \ptr, .Lxchal_ofs_ + 0
63 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
64 .endif
65 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
66 xchal_sa_align \ptr, 0, 1024-4, 4, 4
67 rur \at1, THREADPTR // threadptr option
68 s32i \at1, \ptr, .Lxchal_ofs_ + 0
69 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
70 .endif
71 .endm // xchal_ncp_store
72
73/* Macro to save all non-coprocessor (extra) custom TIE and optional state
74 * (not including zero-overhead loop registers).
75 * Save area ptr (clobbered): ptr (1 byte aligned)
76 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
77 */
78 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
79 xchal_sa_start \continue, \ofs
80 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select
81 xchal_sa_align \ptr, 0, 1024-8, 4, 4
82 l32i \at1, \ptr, .Lxchal_ofs_ + 0
83 l32i \at2, \ptr, .Lxchal_ofs_ + 4
84 wsr \at1, ACCLO // MAC16 accumulator
85 wsr \at2, ACCHI
86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
87 .endif
88 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
89 xchal_sa_align \ptr, 0, 1024-16, 4, 4
90 l32i \at1, \ptr, .Lxchal_ofs_ + 0
91 l32i \at2, \ptr, .Lxchal_ofs_ + 4
92 wsr \at1, M0 // MAC16 registers
93 wsr \at2, M1
94 l32i \at1, \ptr, .Lxchal_ofs_ + 8
95 l32i \at2, \ptr, .Lxchal_ofs_ + 12
96 wsr \at1, M2
97 wsr \at2, M3
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16
99 .endif
100 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
101 xchal_sa_align \ptr, 0, 1024-4, 4, 4
102 l32i \at1, \ptr, .Lxchal_ofs_ + 0
103 wsr \at1, SCOMPARE1 // conditional store option
104 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
105 .endif
106 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
107 xchal_sa_align \ptr, 0, 1024-4, 4, 4
108 l32i \at1, \ptr, .Lxchal_ofs_ + 0
109 wur \at1, THREADPTR // threadptr option
110 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
111 .endif
112 .endm // xchal_ncp_load
113
114
115
116#define XCHAL_NCP_NUM_ATMPS 2
117
118
119#define XCHAL_SA_NUM_ATMPS 2
120
121#endif /*_XTENSA_CORE_TIE_ASM_H*/
122
diff --git a/include/asm-xtensa/variant-dc232b/tie.h b/include/asm-xtensa/variant-dc232b/tie.h
deleted file mode 100644
index 018e81af4393..000000000000
--- a/include/asm-xtensa/variant-dc232b/tie.h
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2007 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 1 /* number of coprocessors */
17#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP7_NAME "XTIOP"
23#define XCHAL_CP7_IDENT XTIOP
24#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
26#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
27
28/* Filler info for unassigned coprocessors, to simplify arrays etc: */
29#define XCHAL_CP0_SA_SIZE 0
30#define XCHAL_CP0_SA_ALIGN 1
31#define XCHAL_CP1_SA_SIZE 0
32#define XCHAL_CP1_SA_ALIGN 1
33#define XCHAL_CP2_SA_SIZE 0
34#define XCHAL_CP2_SA_ALIGN 1
35#define XCHAL_CP3_SA_SIZE 0
36#define XCHAL_CP3_SA_ALIGN 1
37#define XCHAL_CP4_SA_SIZE 0
38#define XCHAL_CP4_SA_ALIGN 1
39#define XCHAL_CP5_SA_SIZE 0
40#define XCHAL_CP5_SA_ALIGN 1
41#define XCHAL_CP6_SA_SIZE 0
42#define XCHAL_CP6_SA_ALIGN 1
43
44/* Save area for non-coprocessor optional and custom (TIE) state: */
45#define XCHAL_NCP_SA_SIZE 32
46#define XCHAL_NCP_SA_ALIGN 4
47
48/* Total save area for optional and custom state (NCP + CPn): */
49#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */
50#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
51
52/*
53 * Detailed contents of save areas.
54 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
55 * before expanding the XCHAL_xxx_SA_LIST() macros.
56 *
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
58 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
59 *
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
61 * ccused = set if used by compiler without special options or code
62 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
63 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
64 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
65 * name = lowercase reg name (no quotes)
66 * galign = group byte alignment (power of 2) (galign >= align)
67 * align = register byte alignment (power of 2)
68 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
69 * (not including any pad bytes required to galign this or next reg)
70 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
71 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
72 * regnum = reg index in regfile, or special/TIE-user reg number
73 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
74 * gapsz = intervening bits, if bitsz bits not stored contiguously
75 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
76 * reset = register reset value (or 0 if undefined at reset)
77 * x = reserved for future use (0 until then)
78 *
79 * To filter out certain registers, e.g. to expand only the non-global
80 * registers used by the compiler, you can do something like this:
81 *
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
83 * #define SELCC0(p...)
84 * #define SELCC1(abikind,p...) SELAK##abikind(p)
85 * #define SELAK0(p...) REG(p)
86 * #define SELAK1(p...) REG(p)
87 * #define SELAK2(p...)
88 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
89 * ...what you want to expand...
90 */
91
92#define XCHAL_NCP_SA_NUM 8
93#define XCHAL_NCP_SA_LIST(s) \
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
101 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
102
103#define XCHAL_CP0_SA_NUM 0
104#define XCHAL_CP0_SA_LIST(s) /* empty */
105
106#define XCHAL_CP1_SA_NUM 0
107#define XCHAL_CP1_SA_LIST(s) /* empty */
108
109#define XCHAL_CP2_SA_NUM 0
110#define XCHAL_CP2_SA_LIST(s) /* empty */
111
112#define XCHAL_CP3_SA_NUM 0
113#define XCHAL_CP3_SA_LIST(s) /* empty */
114
115#define XCHAL_CP4_SA_NUM 0
116#define XCHAL_CP4_SA_LIST(s) /* empty */
117
118#define XCHAL_CP5_SA_NUM 0
119#define XCHAL_CP5_SA_LIST(s) /* empty */
120
121#define XCHAL_CP6_SA_NUM 0
122#define XCHAL_CP6_SA_LIST(s) /* empty */
123
124#define XCHAL_CP7_SA_NUM 0
125#define XCHAL_CP7_SA_LIST(s) /* empty */
126
127/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
128#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
129
130#endif /*_XTENSA_CORE_TIE_H*/
131
diff --git a/include/asm-xtensa/variant-fsf/core.h b/include/asm-xtensa/variant-fsf/core.h
deleted file mode 100644
index 2f337605c744..000000000000
--- a/include/asm-xtensa/variant-fsf/core.h
+++ /dev/null
@@ -1,359 +0,0 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1999-2006 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CORE_H
12#define _XTENSA_CORE_H
13
14
15/****************************************************************************
16 Parameters Useful for Any Code, USER or PRIVILEGED
17 ****************************************************************************/
18
19/*
20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21 * configured, and a value of 0 otherwise. These macros are always defined.
22 */
23
24
25/*----------------------------------------------------------------------
26 ISA
27 ----------------------------------------------------------------------*/
28
29#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
30#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
32#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
33#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
34#define XCHAL_HAVE_DEBUG 1 /* debug option */
35#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
39#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
40#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
41#define XCHAL_HAVE_MUL16 0 /* MUL16S/MUL16U instructions */
42#define XCHAL_HAVE_MUL32 0 /* MULL instruction */
43#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
44#define XCHAL_HAVE_L32R 1 /* L32R instruction */
45#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
46#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
47#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
48#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
49#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
50#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
51#define XCHAL_HAVE_ABS 1 /* ABS instruction */
52/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
53/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
54#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
55#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
56#define XCHAL_HAVE_SPECULATION 0 /* speculation */
57#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
58#define XCHAL_NUM_CONTEXTS 1 /* */
59#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
60#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
61#define XCHAL_HAVE_PRID 1 /* processor ID register */
62#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
63#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
64#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
65#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
66#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
67#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
68#define XCHAL_HAVE_FP 0 /* floating point pkg */
69#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
70#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
71#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
72
73
74/*----------------------------------------------------------------------
75 MISC
76 ----------------------------------------------------------------------*/
77
78#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
79#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
80#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
81/* In T1050, applies to selected core load and store instructions (see ISA): */
82#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
83#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
84
85#define XCHAL_CORE_ID "fsf" /* alphanum core name
86 (CoreID) set in the Xtensa
87 Processor Generator */
88
89#define XCHAL_BUILD_UNIQUE_ID 0x00006700 /* 22-bit sw build ID */
90
91/*
92 * These definitions describe the hardware targeted by this software.
93 */
94#define XCHAL_HW_CONFIGID0 0xC103C3FF /* ConfigID hi 32 bits*/
95#define XCHAL_HW_CONFIGID1 0x0C006700 /* ConfigID lo 32 bits*/
96#define XCHAL_HW_VERSION_NAME "LX2.0.0" /* full version name */
97#define XCHAL_HW_VERSION_MAJOR 2200 /* major ver# of targeted hw */
98#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */
99#define XTHAL_HW_REL_LX2 1
100#define XTHAL_HW_REL_LX2_0 1
101#define XTHAL_HW_REL_LX2_0_0 1
102#define XCHAL_HW_CONFIGID_RELIABLE 1
103/* If software targets a *range* of hardware versions, these are the bounds: */
104#define XCHAL_HW_MIN_VERSION_MAJOR 2200 /* major v of earliest tgt hw */
105#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */
106#define XCHAL_HW_MAX_VERSION_MAJOR 2200 /* major v of latest tgt hw */
107#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */
108
109
110/*----------------------------------------------------------------------
111 CACHE
112 ----------------------------------------------------------------------*/
113
114#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
115#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
116#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
117#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
118
119#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
120#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
121
122#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
123
124
125
126
127/****************************************************************************
128 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
129 ****************************************************************************/
130
131
132#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
133
134/*----------------------------------------------------------------------
135 CACHE
136 ----------------------------------------------------------------------*/
137
138#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
139
140/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
141
142/* Number of cache sets in log2(lines per way): */
143#define XCHAL_ICACHE_SETWIDTH 8
144#define XCHAL_DCACHE_SETWIDTH 8
145
146/* Cache set associativity (number of ways): */
147#define XCHAL_ICACHE_WAYS 2
148#define XCHAL_DCACHE_WAYS 2
149
150/* Cache features: */
151#define XCHAL_ICACHE_LINE_LOCKABLE 0
152#define XCHAL_DCACHE_LINE_LOCKABLE 0
153#define XCHAL_ICACHE_ECC_PARITY 0
154#define XCHAL_DCACHE_ECC_PARITY 0
155
156/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
157#define XCHAL_CA_BITS 4
158
159
160/*----------------------------------------------------------------------
161 INTERNAL I/D RAM/ROMs and XLMI
162 ----------------------------------------------------------------------*/
163
164#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
165#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
166#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
167#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
169#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
170
171
172/*----------------------------------------------------------------------
173 INTERRUPTS and TIMERS
174 ----------------------------------------------------------------------*/
175
176#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
177#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
178#define XCHAL_HAVE_NMI 0 /* non-maskable interrupt */
179#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
180#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
181#define XCHAL_NUM_INTERRUPTS 17 /* number of interrupts */
182#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
183#define XCHAL_NUM_EXTINTERRUPTS 10 /* num of external interrupts */
184#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
185 (not including level zero) */
186#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
187 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
188
189/* Masks of interrupts at each interrupt level: */
190#define XCHAL_INTLEVEL1_MASK 0x000064F9
191#define XCHAL_INTLEVEL2_MASK 0x00008902
192#define XCHAL_INTLEVEL3_MASK 0x00011204
193#define XCHAL_INTLEVEL4_MASK 0x00000000
194#define XCHAL_INTLEVEL5_MASK 0x00000000
195#define XCHAL_INTLEVEL6_MASK 0x00000000
196#define XCHAL_INTLEVEL7_MASK 0x00000000
197
198/* Masks of interrupts at each range 1..n of interrupt levels: */
199#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000064F9
200#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x0000EDFB
201#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0001FFFF
202#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0001FFFF
203#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0001FFFF
204#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0001FFFF
205#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0001FFFF
206
207/* Level of each interrupt: */
208#define XCHAL_INT0_LEVEL 1
209#define XCHAL_INT1_LEVEL 2
210#define XCHAL_INT2_LEVEL 3
211#define XCHAL_INT3_LEVEL 1
212#define XCHAL_INT4_LEVEL 1
213#define XCHAL_INT5_LEVEL 1
214#define XCHAL_INT6_LEVEL 1
215#define XCHAL_INT7_LEVEL 1
216#define XCHAL_INT8_LEVEL 2
217#define XCHAL_INT9_LEVEL 3
218#define XCHAL_INT10_LEVEL 1
219#define XCHAL_INT11_LEVEL 2
220#define XCHAL_INT12_LEVEL 3
221#define XCHAL_INT13_LEVEL 1
222#define XCHAL_INT14_LEVEL 1
223#define XCHAL_INT15_LEVEL 2
224#define XCHAL_INT16_LEVEL 3
225#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
226#define XCHAL_HAVE_DEBUG_EXTERN_INT 0 /* OCD external db interrupt */
227
228/* Type of each interrupt: */
229#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
230#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
231#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
232#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
233#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
234#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
235#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
236#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_EDGE
237#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
238#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
239#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
240#define XCHAL_INT11_TYPE XTHAL_INTTYPE_TIMER
241#define XCHAL_INT12_TYPE XTHAL_INTTYPE_TIMER
242#define XCHAL_INT13_TYPE XTHAL_INTTYPE_SOFTWARE
243#define XCHAL_INT14_TYPE XTHAL_INTTYPE_SOFTWARE
244#define XCHAL_INT15_TYPE XTHAL_INTTYPE_SOFTWARE
245#define XCHAL_INT16_TYPE XTHAL_INTTYPE_SOFTWARE
246
247/* Masks of interrupts for each type of interrupt: */
248#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFE0000
249#define XCHAL_INTTYPE_MASK_SOFTWARE 0x0001E000
250#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000380
251#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000007F
252#define XCHAL_INTTYPE_MASK_TIMER 0x00001C00
253#define XCHAL_INTTYPE_MASK_NMI 0x00000000
254#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
255
256/* Interrupt numbers assigned to specific interrupt sources: */
257#define XCHAL_TIMER0_INTERRUPT 10 /* CCOMPARE0 */
258#define XCHAL_TIMER1_INTERRUPT 11 /* CCOMPARE1 */
259#define XCHAL_TIMER2_INTERRUPT 12 /* CCOMPARE2 */
260#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
261
262/* Interrupt numbers for levels at which only one interrupt is configured: */
263/* (There are many interrupts each at level(s) 1, 2, 3.) */
264
265
266/*
267 * External interrupt vectors/levels.
268 * These macros describe how Xtensa processor interrupt numbers
269 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
270 * map to external BInterrupt<n> pins, for those interrupts
271 * configured as external (level-triggered, edge-triggered, or NMI).
272 * See the Xtensa processor databook for more details.
273 */
274
275/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
276#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
277#define XCHAL_EXTINT1_NUM 1 /* (intlevel 2) */
278#define XCHAL_EXTINT2_NUM 2 /* (intlevel 3) */
279#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
280#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
281#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
282#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
283#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
284#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */
285#define XCHAL_EXTINT9_NUM 9 /* (intlevel 3) */
286
287
288/*----------------------------------------------------------------------
289 EXCEPTIONS and VECTORS
290 ----------------------------------------------------------------------*/
291
292#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
293 number: 1 == XEA1 (old)
294 2 == XEA2 (new)
295 0 == XEAX (extern) */
296#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
297#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
298#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
299#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
300#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
301
302#define XCHAL_RESET_VECTOR_VADDR 0xFE000020
303#define XCHAL_RESET_VECTOR_PADDR 0xFE000020
304#define XCHAL_USER_VECTOR_VADDR 0xD0000220
305#define XCHAL_USER_VECTOR_PADDR 0x00000220
306#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000200
307#define XCHAL_KERNEL_VECTOR_PADDR 0x00000200
308#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD0000290
309#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x00000290
310#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000
311#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000
312#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000240
313#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000240
314#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD0000250
315#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x00000250
316#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xFE000520
317#define XCHAL_INTLEVEL4_VECTOR_PADDR 0xFE000520
318#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
319#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
320
321
322/*----------------------------------------------------------------------
323 DEBUG
324 ----------------------------------------------------------------------*/
325
326#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
327#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
328#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
329#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
330
331
332/*----------------------------------------------------------------------
333 MMU
334 ----------------------------------------------------------------------*/
335
336/* See <xtensa/config/core-matmap.h> header file for more details. */
337
338#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
339#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */
340#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
341#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
342#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
343#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
344#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
345 [autorefill] and protection)
346 usable for an MMU-based OS */
347/* If none of the above last 4 are set, it's a custom TLB configuration. */
348#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
349#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
350
351#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
352#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
353#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
354
355#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
356
357
358#endif /* _XTENSA_CORE_CONFIGURATION_H */
359
diff --git a/include/asm-xtensa/variant-fsf/tie-asm.h b/include/asm-xtensa/variant-fsf/tie-asm.h
deleted file mode 100644
index 68a73bf4ffc5..000000000000
--- a/include/asm-xtensa/variant-fsf/tie-asm.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (1 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rur \at1, THREADPTR // threadptr option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (1 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wur \at1, THREADPTR // threadptr option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67#define XCHAL_SA_NUM_ATMPS 1
68
69#endif /*_XTENSA_CORE_TIE_ASM_H*/
70
diff --git a/include/asm-xtensa/variant-fsf/tie.h b/include/asm-xtensa/variant-fsf/tie.h
deleted file mode 100644
index bf4020116df5..000000000000
--- a/include/asm-xtensa/variant-fsf/tie.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2007 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 0 /* number of coprocessors */
17#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP7_NAME "XTIOP"
23#define XCHAL_CP7_IDENT XTIOP
24#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */
25#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */
26#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */
27
28/* Filler info for unassigned coprocessors, to simplify arrays etc: */
29#define XCHAL_NCP_SA_SIZE 0
30#define XCHAL_NCP_SA_ALIGN 1
31#define XCHAL_CP0_SA_SIZE 0
32#define XCHAL_CP0_SA_ALIGN 1
33#define XCHAL_CP1_SA_SIZE 0
34#define XCHAL_CP1_SA_ALIGN 1
35#define XCHAL_CP2_SA_SIZE 0
36#define XCHAL_CP2_SA_ALIGN 1
37#define XCHAL_CP3_SA_SIZE 0
38#define XCHAL_CP3_SA_ALIGN 1
39#define XCHAL_CP4_SA_SIZE 0
40#define XCHAL_CP4_SA_ALIGN 1
41#define XCHAL_CP5_SA_SIZE 0
42#define XCHAL_CP5_SA_ALIGN 1
43#define XCHAL_CP6_SA_SIZE 0
44#define XCHAL_CP6_SA_ALIGN 1
45
46/* Save area for non-coprocessor optional and custom (TIE) state: */
47#define XCHAL_NCP_SA_SIZE 0
48#define XCHAL_NCP_SA_ALIGN 1
49
50/* Total save area for optional and custom state (NCP + CPn): */
51#define XCHAL_TOTAL_SA_SIZE 0 /* with 16-byte align padding */
52#define XCHAL_TOTAL_SA_ALIGN 1 /* actual minimum alignment */
53
54#define XCHAL_NCP_SA_NUM 0
55#define XCHAL_NCP_SA_LIST(s)
56#define XCHAL_CP0_SA_NUM 0
57#define XCHAL_CP0_SA_LIST(s)
58#define XCHAL_CP1_SA_NUM 0
59#define XCHAL_CP1_SA_LIST(s)
60#define XCHAL_CP2_SA_NUM 0
61#define XCHAL_CP2_SA_LIST(s)
62#define XCHAL_CP3_SA_NUM 0
63#define XCHAL_CP3_SA_LIST(s)
64#define XCHAL_CP4_SA_NUM 0
65#define XCHAL_CP4_SA_LIST(s)
66#define XCHAL_CP5_SA_NUM 0
67#define XCHAL_CP5_SA_LIST(s)
68#define XCHAL_CP6_SA_NUM 0
69#define XCHAL_CP6_SA_LIST(s)
70#define XCHAL_CP7_SA_NUM 0
71#define XCHAL_CP7_SA_LIST(s)
72
73/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
74#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
75
76#endif /*_XTENSA_CORE_TIE_H*/
77
diff --git a/include/asm-xtensa/vga.h b/include/asm-xtensa/vga.h
deleted file mode 100644
index 1fd8cab3a297..000000000000
--- a/include/asm-xtensa/vga.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * include/asm-xtensa/vga.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_VGA_H
12#define _XTENSA_VGA_H
13
14#define VGA_MAP_MEM(x,s) (unsigned long)phys_to_virt(x)
15
16#define vga_readb(x) (*(x))
17#define vga_writeb(x,y) (*(y) = (x))
18
19#endif
diff --git a/include/asm-xtensa/xor.h b/include/asm-xtensa/xor.h
deleted file mode 100644
index e7b1f083991d..000000000000
--- a/include/asm-xtensa/xor.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-xtensa/xor.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_XOR_H
12#define _XTENSA_XOR_H
13
14#include <asm-generic/xor.h>
15
16#endif